更新 README.md

README.md

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-# EDA-for-student
-
+# EDA-for-student
+
+## Verilog集成开发环境
+- Intel Quartus Prime Design Suite \[[官方下载链接](https://www.intel.com/content/www/us/en/products/details/fpga/development-tools/quartus-prime/resource.html)\]
+- AMD Vivado Design Suite \[[官方下载链接](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools.html)\]
+
+## Verilog仿真工具
+- 闭源仿真工具ModelSim \[[官方下载链接](https://www.intel.com/content/www/us/en/software-kit/750666/modelsim-intel-fpgas-standard-edition-software-version-20-1-1.html)\]
+- 开源仿真工具Verilator \[[Github下载链接](https://github.com/verilator/verilator)\] \[[本地下载链接](http://cloud.sunlab.top:3000/TJU-SUN-LAB/verilator)\]
+
+## 综合工具
+- 开源综合工具yosys \[[Github下载链接](https://github.com/YosysHQ/yosys)\]
+
+## 学习资料
+- FPGA Tutorial \[[Github下载链接](https://github.com/LeiWang1999/FPGA)\]
+- Verilog必做练习题HDLBits \[[官方网站](https://hdlbits.01xz.net/wiki/Main_Page)\]
+- 另一个Verilog Practice \[[Github下载链接](https://github.com/xiaop1/Verilog-Practice)\]
+- Basic_verilog \[[Github下载链接](https://github.com/pConst/basic_verilog)\]
+- 32-Verilog-Mini-Projects \[[Github下载链接](https://github.com/sudhamshu091/32-Verilog-Mini-Projects)\]