waveform_acquisition_FPGA_code/puart2/clkgen.qip

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2025-12-11 18:35:48 +08:00
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "17.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "clkgen.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clkgen_inst.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clkgen_bb.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clkgen.ppf"]