20 lines
7.3 KiB
Plaintext
20 lines
7.3 KiB
Plaintext
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1765447235218 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Power Analyzer Quartus Prime " "Running Quartus Prime Power Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1765447235229 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 11 18:00:35 2025 " "Processing started: Thu Dec 11 18:00:35 2025" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1765447235229 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Power Analyzer" 0 -1 1765447235229 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_pow --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10 " "Command: quartus_pow --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10" { } { } 0 0 "Command: %1!s!" 0 0 "Power Analyzer" 0 -1 1765447235229 ""}
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{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Power Analyzer" 0 -1 1765447235534 ""}
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{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Power Analyzer" 0 -1 1765447235534 ""}
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{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "intan_m10.sdc " "Synopsys Design Constraints File file not found: 'intan_m10.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Power Analyzer" 0 -1 1765447235796 ""}
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{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "sys_clk " "Node: sys_clk was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi_master_2164:u_spi_master_2164\|cnt\[1\] sys_clk " "Register spi_master_2164:u_spi_master_2164\|cnt\[1\] is being clocked by sys_clk" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1765447235797 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Power Analyzer" 0 -1 1765447235797 "|ddr_ctrl|sys_clk"}
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{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi_master_2164:u_spi_master_2164\|cs_n " "Node: spi_master_2164:u_spi_master_2164\|cs_n was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register state\[2\] spi_master_2164:u_spi_master_2164\|cs_n " "Register state\[2\] is being clocked by spi_master_2164:u_spi_master_2164\|cs_n" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1765447235797 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Power Analyzer" 0 -1 1765447235797 "|ddr_ctrl|spi_master_2164:u_spi_master_2164|cs_n"}
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{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Power Analyzer" 0 -1 1765447235798 ""}
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{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Node: clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 83.333 " "Node: clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 83.333" { } { } 0 332056 "%1!s!" 0 0 "Design Software" 0 -1 1765447235799 ""} } { } 0 332056 "%1!s!" 0 0 "Power Analyzer" 0 -1 1765447235799 ""}
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{ "Info" "IPVA_PVA_START_CALCULATION" "" "Starting Vectorless Power Activity Estimation" { } { } 0 223000 "Starting Vectorless Power Activity Estimation" 0 0 "Power Analyzer" 0 -1 1765447235803 ""}
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{ "Warning" "WPUTIL_PUTIL_NO_CLK_DOMAINS_FOUND" "" "Relative toggle rates could not be calculated because no clock domain could be identified for some nodes" { } { } 0 222013 "Relative toggle rates could not be calculated because no clock domain could be identified for some nodes" 0 0 "Power Analyzer" 0 -1 1765447235804 ""}
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{ "Info" "IPVA_PVA_END_CALCULATION" "" "Completed Vectorless Power Activity Estimation" { } { } 0 223001 "Completed Vectorless Power Activity Estimation" 0 0 "Power Analyzer" 0 -1 1765447235806 ""}
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{ "Info" "IPATFAM_USING_ADVANCED_IO_POWER" "" "Using Advanced I/O Power to simulate I/O buffers with the specified board trace model" { } { } 0 218000 "Using Advanced I/O Power to simulate I/O buffers with the specified board trace model" 0 0 "Power Analyzer" 0 -1 1765447235961 ""}
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{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Power Analyzer" 0 -1 1765447235996 ""}
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{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Power Analyzer" 0 -1 1765447236365 ""}
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{ "Info" "IPAN_AVG_TOGGLE_RATE_PER_DESIGN" "0.000 millions of transitions / sec " "Average toggle rate for this design is 0.000 millions of transitions / sec" { } { } 0 215049 "Average toggle rate for this design is %1!s!" 0 0 "Power Analyzer" 0 -1 1765447236695 ""}
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{ "Info" "IPAN_PAN_TOTAL_POWER_ESTIMATION" "149.66 mW " "Total thermal power estimate for the design is 149.66 mW" { } { { "e:/quartuslite/quartus/bin64/Report_Window_01.qrpt" "" { Report "e:/quartuslite/quartus/bin64/Report_Window_01.qrpt" "Compiler" "" "" "" "" { } "PowerPlay Power Analyzer Summary" } } } 0 215031 "Total thermal power estimate for the design is %1!s!" 0 0 "Power Analyzer" 0 -1 1765447236811 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "Power Analyzer 0 s 7 s Quartus Prime " "Quartus Prime Power Analyzer was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4812 " "Peak virtual memory: 4812 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1765447237015 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 11 18:00:37 2025 " "Processing ended: Thu Dec 11 18:00:37 2025" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1765447237015 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1765447237015 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1765447237015 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Power Analyzer" 0 -1 1765447237015 ""}
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