waveform_acquisition_FPGA_code/puart2/ddr_ctrl.v.bak

module ddr_ctrl(
	input sys_clk,		// 12M on-board oscillator
	input rst_n,
	
	// 2164
	input miso,
	output mosi,
	output cs_n,
	output sclk,
	
	// for simulation
	output reg [24:0] state,
	output reg [24:0] next,
	
	output [31:0] dout
);
	
	localparam [4:0] 	s0 = 0,
							s1 = 1,
							s2 = 2,
							s3 = 3,
							s4 = 4,
							s5 = 5,
							s6 = 6,
							s7 = 7,
							s8 = 8,
							s9 = 9,
							s10 = 10,
							s11 = 11,
							s12 = 12,
							s13 = 13,
							s14 = 14,
							s15 = 15,
							s16 = 16,
							s17 = 17,
							s18 = 18,
							s19 = 19,
							s20 = 20,
							s21 = 21,
							s22 = 22,
							s23 = 23,
							s24 = 24;	// read reg 63
	
//	reg [24:0] state, next;

	reg 	[15:0] 	din_r;
	wire 	[15:0]	din;
//	wire 	[31:0]	dout;
	wire 				done;
//	reg 				state;
//	reg 	[5:0]		sel;
//	reg   [4:0]   	din_t;
	
	
	assign din = din_r;
	
	
	always @ (posedge cs_n or negedge rst_n) begin
		if(!rst_n) begin
			state 		<= 25'd0;
			state[s0] 	<= 1'b1;
		end
		else state <= next;
	end
	
	
	always @ (*) begin
		next 		= 24'd0;
		din_r 	= {2'b11,6'd63,8'h00};
		case(1'b1)	// reverse case
			state[s0]: 	begin din_r<={2'b11,6'd63,8'h00}; 	next[s1] = 1'b1; 		end
			state[s1]: 	begin din_r<={2'b11,6'd63,8'h00}; 	next[s2] = 1'b1; 		end
			state[s2]: 	begin din_r<={2'b10,6'd0,8'hDE}; 	next[s3] = 1'b1; 		end
			state[s3]: 	begin din_r<={2'b10,6'd1,8'h42}; 	next[s4] = 1'b1; 		end
			state[s4]: 	begin din_r<={2'b10,6'd2,8'h04}; 	next[s5] = 1'b1; 		end
			state[s5]: 	begin din_r<={2'b10,6'd3,8'h00}; 	next[s6] = 1'b1; 		end
			state[s6]: 	begin din_r<={2'b10,6'd4,8'h80}; 	next[s7] = 1'b1; 		end
			state[s7]: 	begin din_r<={2'b10,6'd5,8'h00}; 	next[s8] = 1'b1; 		end
			state[s8]: 	begin din_r<={2'b10,6'd6,8'h80}; 	next[s9] = 1'b1; 		end
			state[s9]: 	begin din_r<={2'b10,6'd7,8'h00}; 	next[s10] = 1'b1;		end
			state[s10]: begin din_r<={2'b10,6'd8,8'h16}; 	next[s11] = 1'b1; 	end
			state[s11]: begin din_r<={2'b10,6'd9,8'h80}; 	next[s12] = 1'b1; 	end
			state[s12]: begin din_r<={2'b10,6'd10,8'h17}; 	next[s13] = 1'b1; 	end
			state[s13]: begin din_r<={2'b10,6'd11,8'h80}; 	next[s14] = 1'b1; 	end
			state[s14]: begin din_r<={2'b10,6'd12,8'h2C}; 	next[s15] = 1'b1; 	end
			state[s15]: begin din_r<={2'b10,6'd13,8'h86}; 	next[s16] = 1'b1; 	end
			state[s16]: begin din_r<={2'b10,6'd14,8'hFF}; 	next[s17] = 1'b1; 	end
			state[s17]: begin din_r<={2'b10,6'd15,8'hFF}; 	next[s18] = 1'b1; 	end
			state[s18]: begin din_r<={2'b10,6'd16,8'hFF}; 	next[s19] = 1'b1; 	end
			state[s19]: begin din_r<={2'b10,6'd17,8'hFF}; 	next[s20] = 1'b1; 	end
			state[s20]: begin din_r<={2'b10,6'd18,8'h00}; 	next[s21] = 1'b1; 	end
			state[s21]: begin din_r<={2'b10,6'd19,8'h00}; 	next[s22] = 1'b1; 	end
			state[s22]: begin din_r<={2'b10,6'd20,8'h00}; 	next[s23] = 1'b1; 	end
			state[s23]: begin din_r<={2'b10,6'd21,8'h00}; 	next[s24] = 1'b1; 	end
			state[s24]: begin din_r<={2'b11,6'd63,8'h00}; 	next[s24] = 1'b1; 	end
		endcase
	end 
	
	
	spi_master_2164 u_spi_master_2164(
		.sys_clk(sys_clk),
		.rst_n(rst_n),
		.din(din),
		.dout(dout),
		.done(done),
		.sclk(sclk),
		.cs_n(cs_n),
		.mosi(mosi),
		.miso(miso),
		.cnt()
	);


	
//	assign din = (state)? {3'b000, din_t, 8'b00000001}:din_r;
//	
//	always @ (posedge cs_n or negedge rst_n) begin
//		if (!rst_n) begin state <= 1'b0; sel <= 'd0; din_r <= 'd0; end
//		else begin 
//			case(sel)
//				6'd0: din_r<={2'b11,6'd62,8'h00};
//				6'd1: din_r<={2'b11,6'd63,8'h00};
//				6'd2: din_r<={2'b10,6'd0,8'hDE};
//				6'd3: din_r<={2'b10,6'd1,8'h42};
//				6'd4: din_r<={2'b10,6'd2,8'h04};
//				6'd5: din_r<={2'b10,6'd3,8'h00};
//				6'd6: din_r<={2'b10,6'd4,8'h80};
//				6'd7: din_r<={2'b10,6'd5,8'h00};
//				6'd8: din_r<={2'b10,6'd6,8'h80};
//				6'd9: din_r<={2'b10,6'd7,8'h00};
//				6'd10: din_r<={2'b10,6'd8,8'h16};
//				6'd11: din_r<={2'b10,6'd9,8'h80};
//				6'd12: din_r<={2'b10,6'd10,8'h17};
//				6'd13: din_r<={2'b10,6'd11,8'h80};
//				6'd14: din_r<={2'b10,6'd12,8'h2C};
//				6'd15: din_r<={2'b10,6'd13,8'h86};
//				6'd16: din_r<={2'b10,6'd14,8'hFF};
//				6'd17: din_r<={2'b10,6'd15,8'hFF};
//				6'd18: din_r<={2'b10,6'd16,8'hFF};
//				6'd19: din_r<={2'b10,6'd17,8'hFF};
//				6'd20: din_r<={2'b10,6'd18,8'h00};
//				6'd21: din_r<={2'b10,6'd19,8'h00};
//				6'd22: din_r<={2'b10,6'd20,8'h00};
//				6'd23: din_r<={2'b10,6'd21,8'h00};
//				default: din_r<={2'b11,6'd63,8'h00};
//			endcase
//			if (sel<24) sel <= sel + 1'b1;
//			else state <= 1;	// no need to reset sel since we only initialize once
//		end
//	end
//	
//	
//	
//	always @ (posedge cs_n or negedge rst_n) begin
//		 if (!rst_n) din_t <= 0;
//		 else if (state) din_t <= din_t + 1'b1;
//		 else din_t <= 0;
//	end

	

endmodule