89 lines
4.6 KiB
Plaintext
89 lines
4.6 KiB
Plaintext
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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 2017 Intel Corporation. All rights reserved.
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# Your use of Intel Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Intel Program License
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# Subscription Agreement, the Intel Quartus Prime License Agreement,
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# the Intel FPGA IP License Agreement, or other applicable license
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# agreement, including, without limitation, that your use is for
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# the sole purpose of programming logic devices manufactured by
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# Intel and sold by Intel or its authorized distributors. Please
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# refer to the applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus Prime
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# Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
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# Date created = 20:28:17 April 12, 2024
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# intan_m10_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus Prime software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "MAX 10"
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set_global_assignment -name DEVICE 10M08SAM153C8G
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set_global_assignment -name TOP_LEVEL_ENTITY ddr_ctrl
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:28:17 APRIL 12, 2024"
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set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
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set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
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set_location_assignment PIN_J5 -to sys_clk
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set_location_assignment PIN_P6 -to cs_n
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set_location_assignment PIN_P4 -to miso
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set_location_assignment PIN_L7 -to mosi
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set_location_assignment PIN_J14 -to rst_n
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cs_n
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to miso
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to mosi
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to rst_n
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set_location_assignment PIN_R5 -to sclk
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sclk
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sys_clk
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set_location_assignment PIN_J12 -to test_flag
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to test_flag
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set_location_assignment PIN_N15 -to test_flag_led
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to test_flag_led
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set_location_assignment PIN_M12 -to convert_flag_led
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to convert_flag_led
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set_global_assignment -name NUM_PARALLEL_PROCESSORS 4
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_location_assignment PIN_B14 -to sclk_ESP32
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set_location_assignment PIN_B13 -to cs_ESP32
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set_location_assignment PIN_A14 -to MOSI_ESP32
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set_global_assignment -name VERILOG_FILE spi_master_2164.v
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set_global_assignment -name VERILOG_FILE ddr_ctrl.v
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set_global_assignment -name QIP_FILE clk_gen.qip
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set_global_assignment -name VERILOG_FILE ../../20240625.v
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set_global_assignment -name VERILOG_FILE spi_master_esp32.v
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set_global_assignment -name VERILOG_FILE uart_tx.v
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set_location_assignment PIN_P8 -to tx
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to tx
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cs_ESP32
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MOSI_ESP32
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sclk_ESP32
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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