310 lines
30 KiB
Plaintext
310 lines
30 KiB
Plaintext
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Power Analyzer report for intan_m10
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Thu Dec 11 18:00:36 2025
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Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Parallel Compilation
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3. Power Analyzer Summary
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4. Power Analyzer Settings
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5. Indeterminate Toggle Rates
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6. Operating Conditions Used
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7. Thermal Power Dissipation by Block
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8. Thermal Power Dissipation by Block Type
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9. Thermal Power Dissipation by Hierarchy
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10. Core Dynamic Thermal Power Dissipation by Clock Domain
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11. Current Drawn from Voltage Supplies Summary
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12. VCCIO Supply Current Drawn by I/O Bank
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13. VCCIO Supply Current Drawn by Voltage
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14. Confidence Metric Details
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15. Signal Activities
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16. Power Analyzer Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 2017 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details.
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+------------------------------------------+
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; Parallel Compilation ;
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+----------------------------+-------------+
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; Processors ; Number ;
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+----------------------------+-------------+
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; Number detected on machine ; 8 ;
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; Maximum allowed ; 4 ;
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; ; ;
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; Average used ; 1.13 ;
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; Maximum used ; 4 ;
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; ; ;
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; Usage by Processor ; % Time Used ;
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; Processor 1 ; 100.0% ;
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; Processors 2-4 ; 4.3% ;
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+----------------------------+-------------+
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+-------------------------------------------------------------------------------------------+
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; Power Analyzer Summary ;
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+----------------------------------------+--------------------------------------------------+
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; Power Analyzer Status ; Successful - Thu Dec 11 18:00:36 2025 ;
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; Quartus Prime Version ; 17.1.0 Build 590 10/25/2017 SJ Lite Edition ;
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; Revision Name ; intan_m10 ;
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; Top-level Entity Name ; ddr_ctrl ;
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; Family ; MAX 10 ;
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; Device ; 10M08SAM153C8G ;
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; Power Models ; Final ;
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; Total Thermal Power Dissipation ; 149.66 mW ;
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; Core Dynamic Thermal Power Dissipation ; 0.00 mW ;
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; Core Static Thermal Power Dissipation ; 121.22 mW ;
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; I/O Thermal Power Dissipation ; 28.44 mW ;
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; Power Estimation Confidence ; Low: user provided insufficient toggle rate data ;
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+----------------------------------------+--------------------------------------------------+
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+------------------------------------------------------------------------------------------------------------------------------------+
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; Power Analyzer Settings ;
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+----------------------------------------------------------------------------+---------------------------------------+---------------+
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; Option ; Setting ; Default Value ;
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+----------------------------------------------------------------------------+---------------------------------------+---------------+
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; Maximum processors allowed for parallel compilation ; 4 ; ;
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; Use smart compilation ; Off ; Off ;
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; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
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; Enable compact report table ; Off ; Off ;
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; Default Power Input I/O Toggle Rate ; 12.5% ; 12.5% ;
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; Preset Cooling Solution ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; ;
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; Board thermal model ; None (CONSERVATIVE) ; ;
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; Default Power Toggle Rate ; 12.5% ; 12.5% ;
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; Use vectorless estimation ; On ; On ;
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; Use Input Files ; Off ; Off ;
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; Filter Glitches in VCD File Reader ; On ; On ;
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; Power Analyzer Report Signal Activity ; Off ; Off ;
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; Power Analyzer Report Power Dissipation ; Off ; Off ;
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; Device Power Characteristics ; TYPICAL ; TYPICAL ;
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; Automatically Compute Junction Temperature ; On ; On ;
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; Specified Junction Temperature ; 25 ; 25 ;
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; Ambient Temperature ; 25 ; 25 ;
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; Use Custom Cooling Solution ; Off ; Off ;
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; Board Temperature ; 25 ; 25 ;
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+----------------------------------------------------------------------------+---------------------------------------+---------------+
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+-----------------------------------------------------------------------------------------------------------------------------------+
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; Indeterminate Toggle Rates ;
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+-----------------------------------------------------------------------------------------------------+-----------------------------+
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; Node ; Reason ;
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+-----------------------------------------------------------------------------------------------------+-----------------------------+
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; clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|wire_pll1_clk[0] ; No valid clock domain found ;
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; test_flag ; No valid clock domain found ;
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; rst_n ; No valid clock domain found ;
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; sys_clk ; No valid clock domain found ;
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; miso ; No valid clock domain found ;
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; clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|wire_pll1_clk[0]~clkctrl ; No valid clock domain found ;
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; spi_master_2164:u_spi_master_2164|cs_n~clkctrl ; No valid clock domain found ;
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+-----------------------------------------------------------------------------------------------------+-----------------------------+
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+--------------------------------------------------------------------------+
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; Operating Conditions Used ;
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+---------------------------------------------+----------------------------+
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; Setting ; Value ;
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+---------------------------------------------+----------------------------+
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; Device power characteristics ; Typical ;
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; ; ;
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; Voltages ; ;
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; VCCA ; 3.00 V ;
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; VCC_ONE ; 3.00 V ;
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; 3.3-V LVTTL I/O Standard ; 3.3 V ;
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; 3.3-V LVCMOS I/O Standard ; 3.3 V ;
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; 2.5 V I/O Standard ; 2.5 V ;
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; 3.3 V Schmitt Trigger I/O Standard ; 3.3 V ;
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; 2.5 V Schmitt Trigger I/O Standard ; 2.5 V ;
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; ; ;
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; Auto computed junction temperature ; 28.8 degrees Celsius ;
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; Ambient temperature ; 25.0 degrees Celsius ;
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; Junction-to-Case thermal resistance ; 11.00 degrees Celsius/Watt ;
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; Case-to-Heat Sink thermal resistance ; 0.10 degrees Celsius/Watt ;
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; Heat Sink-to-Ambient thermal resistance ; 14.30 degrees Celsius/Watt ;
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; ; ;
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; Board model used ; None ;
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+---------------------------------------------+----------------------------+
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+----------------------------------------------------------------------------------------------------------------------------------------------+
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; Thermal Power Dissipation by Block ;
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+------------+------------+---------------------+-----------------------------+--------------------------------+-------------------------------+
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; Block Name ; Block Type ; Total Thermal Power ; Block Thermal Dynamic Power ; Block Thermal Static Power (1) ; Routing Thermal Dynamic Power ;
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+------------+------------+---------------------+-----------------------------+--------------------------------+-------------------------------+
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(1) The "Thermal Power Dissipation by Block" Table has been hidden. To show this table, please select the "Write power dissipation by block to report file" option under "PowerPlay Power Analyzer Settings".
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+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Thermal Power Dissipation by Block Type ;
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+---------------------+-----------------------------------+-----------------------------+--------------------------------+-------------------------------+-----------------------------------------------------------+
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; Block Type ; Total Thermal Power by Block Type ; Block Thermal Dynamic Power ; Block Thermal Static Power (1) ; Routing Thermal Dynamic Power ; Block Average Toggle Rate (millions of transitions / sec) ;
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+---------------------+-----------------------------------+-----------------------------+--------------------------------+-------------------------------+-----------------------------------------------------------+
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; Combinational cell ; 0.00 mW ; 0.00 mW ; -- ; 0.00 mW ; 0.000 ;
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; Clock control block ; 0.00 mW ; 0.00 mW ; -- ; 0.00 mW ; 0.000 ;
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; Register cell ; 0.00 mW ; 0.00 mW ; -- ; 0.00 mW ; 0.000 ;
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; I/O ; 0.78 mW ; 0.00 mW ; 0.78 mW ; 0.00 mW ; 0.000 ;
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; Voltage Regulator ; 0.76 mW ; 0.00 mW ; 0.76 mW ; -- ; -- ;
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+---------------------+-----------------------------------+-----------------------------+--------------------------------+-------------------------------+-----------------------------------------------------------+
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(1) The "Block Thermal Static Power" for all block types except Pins and the Voltage Regulator, if one exists, is part of the "Core Static Thermal Power Dissipation" value found on the PowerPlay Power Analyzer-->Summary report panel. The "Core Static Thermal Power Dissipation" also contains the thermal static power dissipated by the routing.
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+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Thermal Power Dissipation by Hierarchy ;
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+--------------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+--------------------------------------------------------------------------------------+
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; Compilation Hierarchy Node ; Total Thermal Power by Hierarchy (1) ; Block Thermal Dynamic Power (1) ; Block Thermal Static Power (1)(2) ; Routing Thermal Dynamic Power (1) ; Full Hierarchy Name ;
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+--------------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+--------------------------------------------------------------------------------------+
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; |ddr_ctrl ; 1.55 mW (1.55 mW) ; 0.00 mW (0.00 mW) ; 1.55 mW (1.55 mW) ; 0.00 mW (0.00 mW) ; |ddr_ctrl ;
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; |hard_block:auto_generated_inst ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |ddr_ctrl|hard_block:auto_generated_inst ;
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; |clk_gen:clk_gen_inst ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |ddr_ctrl|clk_gen:clk_gen_inst ;
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; |altpll:altpll_component ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |ddr_ctrl|clk_gen:clk_gen_inst|altpll:altpll_component ;
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; |clk_gen_altpll:auto_generated ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |ddr_ctrl|clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated ;
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; |spi_master_esp32:tranfer ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |ddr_ctrl|spi_master_esp32:tranfer ;
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; |spi_master_2164:u_spi_master_2164 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |ddr_ctrl|spi_master_2164:u_spi_master_2164 ;
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; |uart_tx:u_uart_pc ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |ddr_ctrl|uart_tx:u_uart_pc ;
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+--------------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+--------------------------------------------------------------------------------------+
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(1) Value in parentheses is the power consumed at that level of hierarchy. Value not in parentheses is the power consumed at that level of hierarchy plus the power consumed by all levels of hierarchy below it.
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(2) The "Block Thermal Static Power" for all levels of hierarchy except the top-level hierarchy is part of the "Core Static Thermal Power Dissipation" value found on the PowerPlay Power Analyzer-->Summary report panel. The "Core Static Thermal Power Dissipation" also contains the thermal static power dissipated by the routing.
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+--------------------------------------------------------------------+
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; Core Dynamic Thermal Power Dissipation by Clock Domain ;
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+-----------------+-----------------------+--------------------------+
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; Clock Domain ; Clock Frequency (MHz) ; Total Core Dynamic Power ;
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+-----------------+-----------------------+--------------------------+
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; No clock domain ; 0.00 ; 0.00 ;
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+-----------------+-----------------------+--------------------------+
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+------------------------------------------------------------------------------------------------------------------------------------+
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; Current Drawn from Voltage Supplies Summary ;
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+----------------+-------------------------+---------------------------+--------------------------+----------------------------------+
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; Voltage Supply ; Total Current Drawn (1) ; Dynamic Current Drawn (1) ; Static Current Drawn (1) ; Minimum Power Supply Current (2) ;
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+----------------+-------------------------+---------------------------+--------------------------+----------------------------------+
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; VCCIO ; 8.79 mA ; 0.00 mA ; 8.79 mA ; 8.79 mA ;
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; VCCA ; 3.03 mA ; 0.00 mA ; 3.03 mA ; 3.03 mA ;
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; VCC_ONE ; 37.38 mA ; 0.00 mA ; 37.38 mA ; 37.38 mA ;
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+----------------+-------------------------+---------------------------+--------------------------+----------------------------------+
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(1) Currents reported in columns "Total Current Drawn", "Dynamic Current Drawn", and "Static Current Drawn" are sufficient for user operation of the device.
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(2) Currents reported in column "Minimum Power Supply Current" are sufficient for power-up, configuration, and user operation of the device.
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+-----------------------------------------------------------------------------------------------+
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; VCCIO Supply Current Drawn by I/O Bank ;
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+----------+---------------+---------------------+-----------------------+----------------------+
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; I/O Bank ; VCCIO Voltage ; Total Current Drawn ; Dynamic Current Drawn ; Static Current Drawn ;
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+----------+---------------+---------------------+-----------------------+----------------------+
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; 1A ; 2.5V ; 0.25 mA ; 0.00 mA ; 0.25 mA ;
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; 1B ; 2.5V ; 0.26 mA ; 0.00 mA ; 0.26 mA ;
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; 2 ; 3.3V ; 1.62 mA ; 0.00 mA ; 1.62 mA ;
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; 3 ; 3.3V ; 1.68 mA ; 0.00 mA ; 1.68 mA ;
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; 4 ; -- ; -- ; -- ; -- ;
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; 5 ; 3.3V ; 1.65 mA ; 0.00 mA ; 1.65 mA ;
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; 6 ; 3.3V ; 1.62 mA ; 0.00 mA ; 1.62 mA ;
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; 7 ; -- ; -- ; -- ; -- ;
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; 8 ; 3.3V ; 1.72 mA ; 0.00 mA ; 1.72 mA ;
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+----------+---------------+---------------------+-----------------------+----------------------+
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+-----------------------------------------------------------------------------------------------------------------------------------+
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; VCCIO Supply Current Drawn by Voltage ;
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+---------------+-------------------------+---------------------------+--------------------------+----------------------------------+
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; VCCIO Voltage ; Total Current Drawn (1) ; Dynamic Current Drawn (1) ; Static Current Drawn (1) ; Minimum Power Supply Current (2) ;
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+---------------+-------------------------+---------------------------+--------------------------+----------------------------------+
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; 2.5V ; 0.51 mA ; 0.00 mA ; 0.51 mA ; 0.51 mA ;
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; 3.3V ; 8.28 mA ; 0.00 mA ; 8.28 mA ; 8.28 mA ;
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+---------------+-------------------------+---------------------------+--------------------------+----------------------------------+
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(1) Currents reported in columns "Total Current Drawn", "Dynamic Current Drawn", and "Static Current Drawn" are sufficient for user operation of the device.
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(2) Currents reported in column "Minimum Power Supply Current" are sufficient for power-up, configuration, and user operation of the device.
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+--------------------------------------------------------------------------------------------------------------------------------------------------+
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; Confidence Metric Details ;
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+----------------------------------------------------------------------------------------+-------------+------------+--------------+---------------+
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; Data Source ; Total ; Pin ; Registered ; Combinational ;
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+----------------------------------------------------------------------------------------+-------------+------------+--------------+---------------+
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; Simulation (from file) ; ; ; ; ;
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; -- Number of signals with Toggle Rate from Simulation ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ;
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; -- Number of signals with Static Probability from Simulation ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ;
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; ; ; ; ; ;
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; Node, entity or clock assignment ; ; ; ; ;
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; -- Number of signals with Toggle Rate from Node, entity or clock assignment ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ;
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; -- Number of signals with Static Probability from Node, entity or clock assignment ; 2 (0.5%) ; 0 (0.0%) ; 0 (0.0%) ; 2 (1.0%) ;
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; ; ; ; ; ;
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; Vectorless estimation ; ; ; ; ;
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; -- Number of signals with Toggle Rate from Vectorless estimation ; 355 (97.0%) ; 11 (52.4%) ; 135 (100.0%) ; 209 (99.5%) ;
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; -- Number of signals with Zero toggle rate, from Vectorless estimation ; 19 (5.2%) ; 6 (28.6%) ; 0 (0.0%) ; 13 (6.2%) ;
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; -- Number of signals with Static Probability from Vectorless estimation ; 353 (96.4%) ; 11 (52.4%) ; 135 (100.0%) ; 207 (98.6%) ;
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; ; ; ; ; ;
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; Default assignment ; ; ; ; ;
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; -- Number of signals with Toggle Rate from Default assignment ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ;
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; -- Number of signals with Static Probability from Default assignment ; 11 (3.0%) ; 10 (47.6%) ; 0 (0.0%) ; 1 (0.5%) ;
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; ; ; ; ; ;
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; Assumed 0 ; ; ; ; ;
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; -- Number of signals with Toggle Rate assumed 0 ; 11 (3.0%) ; 10 (47.6%) ; 0 (0.0%) ; 1 (0.5%) ;
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+----------------------------------------------------------------------------------------+-------------+------------+--------------+---------------+
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+---------------------------------------------------------------------------------------------------------------------------------------------+
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; Signal Activities ;
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+--------+------+---------------------------------------------+-------------------------+--------------------+--------------------------------+
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; Signal ; Type ; Toggle Rate (millions of transitions / sec) ; Toggle Rate Data Source ; Static Probability ; Static Probability Data Source ;
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+--------+------+---------------------------------------------+-------------------------+--------------------+--------------------------------+
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(1) The "Signal Activity" Table has been hidden. To show this table, please select the "Write signal activities to report file" option under "PowerPlay Power Analyzer Settings".
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+-------------------------+
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; Power Analyzer Messages ;
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+-------------------------+
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Info: *******************************************************************
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Info: Running Quartus Prime Power Analyzer
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Info: Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
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Info: Processing started: Thu Dec 11 18:00:35 2025
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Info: Command: quartus_pow --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10
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Info (21077): Low junction temperature is 0 degrees C
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Info (21077): High junction temperature is 85 degrees C
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Critical Warning (332012): Synopsys Design Constraints File file not found: 'intan_m10.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
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Warning (332060): Node: sys_clk was determined to be a clock but was found without an associated clock assignment.
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Info (13166): Register spi_master_2164:u_spi_master_2164|cnt[1] is being clocked by sys_clk
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Warning (332060): Node: spi_master_2164:u_spi_master_2164|cs_n was determined to be a clock but was found without an associated clock assignment.
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Info (13166): Register state[2] is being clocked by spi_master_2164:u_spi_master_2164|cs_n
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Warning (332068): No clocks defined in design.
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Warning (332056): PLL cross checking found inconsistent PLL clock settings:
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Warning (332056): Node: clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 83.333
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Info (223000): Starting Vectorless Power Activity Estimation
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Warning (222013): Relative toggle rates could not be calculated because no clock domain could be identified for some nodes
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Info (223001): Completed Vectorless Power Activity Estimation
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Info (218000): Using Advanced I/O Power to simulate I/O buffers with the specified board trace model
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Info (334003): Started post-fitting delay annotation
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Info (334004): Delay annotation completed successfully
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Info (215049): Average toggle rate for this design is 0.000 millions of transitions / sec
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Info (215031): Total thermal power estimate for the design is 149.66 mW
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Info: Quartus Prime Power Analyzer was successful. 0 errors, 7 warnings
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Info: Peak virtual memory: 4812 megabytes
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Info: Processing ended: Thu Dec 11 18:00:37 2025
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Info: Elapsed time: 00:00:02
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Info: Total CPU time (on all processors): 00:00:02
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