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waveform_acquisition_FPGA_code/puart2/output_files/intan_m10.map.rpt

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2025-12-11 18:35:48 +08:00
Analysis & Synthesis report for intan_m10
Thu Dec 11 18:00:25 2025
Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. Analysis & Synthesis IP Cores Summary
9. State Machine - |ddr_ctrl|state_top
10. State Machine - |ddr_ctrl|uart_tx:u_uart_pc|byte_select
11. State Machine - |ddr_ctrl|uart_tx:u_uart_pc|tx_state
12. State Machine - |ddr_ctrl|spi_master_esp32:tranfer|state
13. Registers Removed During Synthesis
14. Removed Registers Triggering Further Register Optimizations
15. General Register Statistics
16. Inverted Register Statistics
17. Multiplexer Restructuring Statistics (Restructuring Performed)
18. Parameter Settings for User Entity Instance: Top-level Entity: |ddr_ctrl
19. Parameter Settings for User Entity Instance: clk_gen:clk_gen_inst|altpll:altpll_component
20. Parameter Settings for User Entity Instance: uart_tx:u_uart_pc
21. altpll Parameter Settings by Entity Instance
22. Port Connectivity Checks: "spi_master_2164:u_spi_master_2164"
23. Port Connectivity Checks: "clk_gen:clk_gen_inst"
24. Post-Synthesis Netlist Statistics for Top Partition
25. Elapsed Time Per Partition
26. Analysis & Synthesis Messages
27. Analysis & Synthesis Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2017 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
+----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+---------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Dec 11 18:00:25 2025 ;
; Quartus Prime Version ; 17.1.0 Build 590 10/25/2017 SJ Lite Edition ;
; Revision Name ; intan_m10 ;
; Top-level Entity Name ; ddr_ctrl ;
; Family ; MAX 10 ;
; Total logic elements ; 198 ;
; Total combinational functions ; 121 ;
; Dedicated logic registers ; 135 ;
; Total registers ; 135 ;
; Total pins ; 13 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 1 ;
; UFM blocks ; 0 ;
; ADC blocks ; 0 ;
+------------------------------------+---------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device ; 10M08SAM153C8G ; ;
; Top-level entity name ; ddr_ctrl ; intan_m10 ;
; Family name ; MAX 10 ; Cyclone V ;
; Maximum processors allowed for parallel compilation ; 4 ; ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Infer RAMs from Raw Logic ; On ; On ;
; Parallel Synthesis ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto DSP Block Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Timing-Driven Synthesis ; On ; On ;
; Report Parameter Settings ; On ; On ;
; Report Source Assignments ; On ; On ;
; Report Connectivity Checks ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Auto Gated Clock Conversion ; Off ; Off ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Resource Aware Inference For Block RAM ; On ; On ;
+----------------------------------------------------------------------------+--------------------+--------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 8 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 4 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processors 2-4 ; 0.0% ;
+----------------------------+-------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------+------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+------------------------------+------------------------------------------------------------------+---------+
; spi_master_2164.v ; yes ; User Verilog HDL File ; E:/FPGA/puart2/spi_master_2164.v ; ;
; ddr_ctrl.v ; yes ; User Verilog HDL File ; E:/FPGA/puart2/ddr_ctrl.v ; ;
; clk_gen.v ; yes ; User Wizard-Generated File ; E:/FPGA/puart2/clk_gen.v ; ;
; spi_master_esp32.v ; yes ; User Verilog HDL File ; E:/FPGA/puart2/spi_master_esp32.v ; ;
; uart_tx.v ; yes ; User Verilog HDL File ; E:/FPGA/puart2/uart_tx.v ; ;
; altpll.tdf ; yes ; Megafunction ; e:/quartuslite/quartus/libraries/megafunctions/altpll.tdf ; ;
; aglobal171.inc ; yes ; Megafunction ; e:/quartuslite/quartus/libraries/megafunctions/aglobal171.inc ; ;
; stratix_pll.inc ; yes ; Megafunction ; e:/quartuslite/quartus/libraries/megafunctions/stratix_pll.inc ; ;
; stratixii_pll.inc ; yes ; Megafunction ; e:/quartuslite/quartus/libraries/megafunctions/stratixii_pll.inc ; ;
; cycloneii_pll.inc ; yes ; Megafunction ; e:/quartuslite/quartus/libraries/megafunctions/cycloneii_pll.inc ; ;
; db/clk_gen_altpll.v ; yes ; Auto-Generated Megafunction ; E:/FPGA/puart2/db/clk_gen_altpll.v ; ;
+----------------------------------+-----------------+------------------------------+------------------------------------------------------------------+---------+
+-------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+---------------------------------------------------------------------------------------------+
; Resource ; Usage ;
+---------------------------------------------+---------------------------------------------------------------------------------------------+
; Estimated Total logic elements ; 198 ;
; ; ;
; Total combinational functions ; 121 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 60 ;
; -- 3 input functions ; 30 ;
; -- <=2 input functions ; 31 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 100 ;
; -- arithmetic mode ; 21 ;
; ; ;
; Total registers ; 135 ;
; -- Dedicated logic registers ; 135 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 13 ;
; ; ;
; Embedded Multiplier 9-bit elements ; 0 ;
; ; ;
; Total PLLs ; 1 ;
; -- PLLs ; 1 ;
; ; ;
; Maximum fan-out node ; clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|wire_pll1_clk[0] ;
; Maximum fan-out ; 105 ;
; Total fan-out ; 843 ;
; Average fan-out ; 2.98 ;
+---------------------------------------------+---------------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+------------------------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+--------------------------------------------------------------------------------------+-----------------+--------------+
; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ;
+------------------------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+--------------------------------------------------------------------------------------+-----------------+--------------+
; |ddr_ctrl ; 121 (33) ; 135 (52) ; 0 ; 0 ; 0 ; 0 ; 0 ; 13 ; 0 ; 0 ; |ddr_ctrl ; ddr_ctrl ; work ;
; |clk_gen:clk_gen_inst| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ddr_ctrl|clk_gen:clk_gen_inst ; clk_gen ; work ;
; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ddr_ctrl|clk_gen:clk_gen_inst|altpll:altpll_component ; altpll ; work ;
; |clk_gen_altpll:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ddr_ctrl|clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated ; clk_gen_altpll ; work ;
; |spi_master_2164:u_spi_master_2164| ; 37 (37) ; 43 (43) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ddr_ctrl|spi_master_2164:u_spi_master_2164 ; spi_master_2164 ; work ;
; |uart_tx:u_uart_pc| ; 51 (51) ; 40 (40) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ddr_ctrl|uart_tx:u_uart_pc ; uart_tx ; work ;
+------------------------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+--------------------------------------------------------------------------------------+-----------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary ;
+--------+--------------+---------+--------------+--------------+--------------------------------+-----------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ;
+--------+--------------+---------+--------------+--------------+--------------------------------+-----------------+
; Altera ; ALTPLL ; 17.1 ; N/A ; N/A ; |ddr_ctrl|clk_gen:clk_gen_inst ; clk_gen.v ;
+--------+--------------+---------+--------------+--------------+--------------------------------+-----------------+
Encoding Type: One-Hot
+------------------------------------------------------------------------------------------------+
; State Machine - |ddr_ctrl|state_top ;
+---------------------+---------------------+-----------------+-----------------+----------------+
; Name ; state_top.SEND_uart ; state_top.SEND2 ; state_top.SEND1 ; state_top.IDLE ;
+---------------------+---------------------+-----------------+-----------------+----------------+
; state_top.IDLE ; 0 ; 0 ; 0 ; 0 ;
; state_top.SEND1 ; 0 ; 0 ; 1 ; 1 ;
; state_top.SEND2 ; 0 ; 1 ; 0 ; 1 ;
; state_top.SEND_uart ; 1 ; 0 ; 0 ; 1 ;
+---------------------+---------------------+-----------------+-----------------+----------------+
Encoding Type: One-Hot
+---------------------------------------------------------+
; State Machine - |ddr_ctrl|uart_tx:u_uart_pc|byte_select ;
+----------------+----------------------------------------+
; Name ; byte_select.01 ;
+----------------+----------------------------------------+
; byte_select.00 ; 0 ;
; byte_select.01 ; 1 ;
+----------------+----------------------------------------+
Encoding Type: One-Hot
+------------------------------------------------------+
; State Machine - |ddr_ctrl|uart_tx:u_uart_pc|tx_state ;
+---------------+--------------------------------------+
; Name ; tx_state.0001 ;
+---------------+--------------------------------------+
; tx_state.0000 ; 0 ;
; tx_state.0001 ; 1 ;
+---------------+--------------------------------------+
Encoding Type: One-Hot
+-----------------------------------------------------------+
; State Machine - |ddr_ctrl|spi_master_esp32:tranfer|state ;
+----------------+------------+------------+----------------+
; Name ; state.IDLE ; state.DONE ; state.TRANSFER ;
+----------------+------------+------------+----------------+
; state.IDLE ; 0 ; 0 ; 0 ;
; state.TRANSFER ; 1 ; 0 ; 1 ;
; state.DONE ; 1 ; 1 ; 0 ;
+----------------+------------+------------+----------------+
+--------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+----------------------------------------------+---------------------------------------------+
; Register name ; Reason for Removal ;
+----------------------------------------------+---------------------------------------------+
; uart_tx:u_uart_pc|tx_shift_reg[9] ; Stuck at VCC due to stuck port data_in ;
; state_top~8 ; Lost fanout ;
; state_top~9 ; Lost fanout ;
; uart_tx:u_uart_pc|byte_select~6 ; Lost fanout ;
; uart_tx:u_uart_pc|tx_state~7 ; Lost fanout ;
; uart_tx:u_uart_pc|tx_state~8 ; Lost fanout ;
; uart_tx:u_uart_pc|tx_state~9 ; Lost fanout ;
; state_top.SEND2 ; Stuck at GND due to stuck port data_in ;
; start2 ; Stuck at GND due to stuck port data_in ;
; spi_master_esp32:tranfer|shift_reg[13] ; Stuck at GND due to stuck port clock_enable ;
; spi_master_esp32:tranfer|bit_cnt[0..3] ; Stuck at GND due to stuck port clock_enable ;
; spi_master_esp32:tranfer|done ; Stuck at GND due to stuck port clock_enable ;
; spi_master_esp32:tranfer|shift_reg[0..12,15] ; Stuck at GND due to stuck port clock_enable ;
; spi_master_esp32:tranfer|cs ; Stuck at VCC due to stuck port clock_enable ;
; spi_master_esp32:tranfer|sclk_reg ; Stuck at GND due to stuck port clock_enable ;
; spi_master_esp32:tranfer|shift_reg[14] ; Stuck at GND due to stuck port clock_enable ;
; spi_master_esp32:tranfer|state.TRANSFER ; Stuck at GND due to stuck port data_in ;
; spi_master_esp32:tranfer|state.DONE ; Stuck at GND due to stuck port data_in ;
; spi_master_esp32:tranfer|state.IDLE ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 35 ; ;
+----------------------------------------------+---------------------------------------------+
+------------------------------------------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations ;
+-----------------+---------------------------+--------------------------------------------------------------------------------------+
; Register name ; Reason for Removal ; Registers Removed due to This Register ;
+-----------------+---------------------------+--------------------------------------------------------------------------------------+
; state_top.SEND2 ; Stuck at GND ; start2, spi_master_esp32:tranfer|shift_reg[13], spi_master_esp32:tranfer|bit_cnt[3], ;
; ; due to stuck port data_in ; spi_master_esp32:tranfer|bit_cnt[2], spi_master_esp32:tranfer|bit_cnt[1], ;
; ; ; spi_master_esp32:tranfer|bit_cnt[0], spi_master_esp32:tranfer|done, ;
; ; ; spi_master_esp32:tranfer|shift_reg[12], spi_master_esp32:tranfer|shift_reg[11], ;
; ; ; spi_master_esp32:tranfer|shift_reg[10], spi_master_esp32:tranfer|shift_reg[9], ;
; ; ; spi_master_esp32:tranfer|shift_reg[8], spi_master_esp32:tranfer|shift_reg[7], ;
; ; ; spi_master_esp32:tranfer|shift_reg[6], spi_master_esp32:tranfer|shift_reg[5], ;
; ; ; spi_master_esp32:tranfer|shift_reg[4], spi_master_esp32:tranfer|shift_reg[3], ;
; ; ; spi_master_esp32:tranfer|shift_reg[2], spi_master_esp32:tranfer|shift_reg[1], ;
; ; ; spi_master_esp32:tranfer|shift_reg[0], spi_master_esp32:tranfer|shift_reg[15], ;
; ; ; spi_master_esp32:tranfer|cs, spi_master_esp32:tranfer|sclk_reg, ;
; ; ; spi_master_esp32:tranfer|shift_reg[14] ;
+-----------------+---------------------------+--------------------------------------------------------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 135 ;
; Number of registers using Synchronous Clear ; 7 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 90 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 68 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+---------------------------------------------------+
; Inverted Register Statistics ;
+-----------------------------------------+---------+
; Inverted Register ; Fan out ;
+-----------------------------------------+---------+
; spi_master_2164:u_spi_master_2164|cs_n ; 32 ;
; uart_tx:u_uart_pc|tx_shift_reg[0] ; 1 ;
; state[0] ; 3 ;
; uart_tx:u_uart_pc|tx_shift_reg[1] ; 1 ;
; uart_tx:u_uart_pc|tx_shift_reg[2] ; 1 ;
; uart_tx:u_uart_pc|tx_shift_reg[3] ; 1 ;
; uart_tx:u_uart_pc|tx_shift_reg[4] ; 1 ;
; uart_tx:u_uart_pc|tx_shift_reg[5] ; 1 ;
; uart_tx:u_uart_pc|tx_shift_reg[6] ; 1 ;
; uart_tx:u_uart_pc|tx_shift_reg[7] ; 1 ;
; uart_tx:u_uart_pc|tx_shift_reg[8] ; 1 ;
; Total number of inverted registers = 11 ; ;
+-----------------------------------------+---------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------+
; 4:1 ; 15 bits ; 30 LEs ; 15 LEs ; 15 LEs ; Yes ; |ddr_ctrl|spi_master_esp32:tranfer|shift_reg[2] ;
; 3:1 ; 7 bits ; 14 LEs ; 7 LEs ; 7 LEs ; Yes ; |ddr_ctrl|uart_tx:u_uart_pc|tx_shift_reg[4] ;
; 7:1 ; 4 bits ; 16 LEs ; 8 LEs ; 8 LEs ; No ; |ddr_ctrl|Selector3 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------+
+--------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |ddr_ctrl ;
+----------------+-------+-------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+-------------------------------------------------+
; IDLE ; 00 ; Unsigned Binary ;
; SEND1 ; 01 ; Unsigned Binary ;
; SEND2 ; 10 ; Unsigned Binary ;
; SEND_uart ; 11 ; Unsigned Binary ;
+----------------+-------+-------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: clk_gen:clk_gen_inst|altpll:altpll_component ;
+-------------------------------+---------------------------+-------------------------------+
; Parameter Name ; Value ; Type ;
+-------------------------------+---------------------------+-------------------------------+
; OPERATION_MODE ; NORMAL ; Untyped ;
; PLL_TYPE ; AUTO ; Untyped ;
; LPM_HINT ; CBX_MODULE_PREFIX=clk_gen ; Untyped ;
; QUALIFY_CONF_DONE ; OFF ; Untyped ;
; COMPENSATE_CLOCK ; CLK0 ; Untyped ;
; SCAN_CHAIN ; LONG ; Untyped ;
; PRIMARY_CLOCK ; INCLK0 ; Untyped ;
; INCLK0_INPUT_FREQUENCY ; 83333 ; Signed Integer ;
; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ;
; GATE_LOCK_SIGNAL ; NO ; Untyped ;
; GATE_LOCK_COUNTER ; 0 ; Untyped ;
; LOCK_HIGH ; 1 ; Untyped ;
; LOCK_LOW ; 1 ; Untyped ;
; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ;
; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ;
; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ;
; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ;
; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ;
; SKIP_VCO ; OFF ; Untyped ;
; SWITCH_OVER_COUNTER ; 0 ; Untyped ;
; SWITCH_OVER_TYPE ; AUTO ; Untyped ;
; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ;
; BANDWIDTH ; 0 ; Untyped ;
; BANDWIDTH_TYPE ; AUTO ; Untyped ;
; SPREAD_FREQUENCY ; 0 ; Untyped ;
; DOWN_SPREAD ; 0 ; Untyped ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ;
; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ;
; CLK9_MULTIPLY_BY ; 0 ; Untyped ;
; CLK8_MULTIPLY_BY ; 0 ; Untyped ;
; CLK7_MULTIPLY_BY ; 0 ; Untyped ;
; CLK6_MULTIPLY_BY ; 0 ; Untyped ;
; CLK5_MULTIPLY_BY ; 1 ; Untyped ;
; CLK4_MULTIPLY_BY ; 1 ; Untyped ;
; CLK3_MULTIPLY_BY ; 1 ; Untyped ;
; CLK2_MULTIPLY_BY ; 1 ; Untyped ;
; CLK1_MULTIPLY_BY ; 12 ; Signed Integer ;
; CLK0_MULTIPLY_BY ; 6 ; Signed Integer ;
; CLK9_DIVIDE_BY ; 0 ; Untyped ;
; CLK8_DIVIDE_BY ; 0 ; Untyped ;
; CLK7_DIVIDE_BY ; 0 ; Untyped ;
; CLK6_DIVIDE_BY ; 0 ; Untyped ;
; CLK5_DIVIDE_BY ; 1 ; Untyped ;
; CLK4_DIVIDE_BY ; 1 ; Untyped ;
; CLK3_DIVIDE_BY ; 1 ; Untyped ;
; CLK2_DIVIDE_BY ; 1 ; Untyped ;
; CLK1_DIVIDE_BY ; 625 ; Signed Integer ;
; CLK0_DIVIDE_BY ; 625 ; Signed Integer ;
; CLK9_PHASE_SHIFT ; 0 ; Untyped ;
; CLK8_PHASE_SHIFT ; 0 ; Untyped ;
; CLK7_PHASE_SHIFT ; 0 ; Untyped ;
; CLK6_PHASE_SHIFT ; 0 ; Untyped ;
; CLK5_PHASE_SHIFT ; 0 ; Untyped ;
; CLK4_PHASE_SHIFT ; 0 ; Untyped ;
; CLK3_PHASE_SHIFT ; 0 ; Untyped ;
; CLK2_PHASE_SHIFT ; 0 ; Untyped ;
; CLK1_PHASE_SHIFT ; 0 ; Untyped ;
; CLK0_PHASE_SHIFT ; 0 ; Untyped ;
; CLK5_TIME_DELAY ; 0 ; Untyped ;
; CLK4_TIME_DELAY ; 0 ; Untyped ;
; CLK3_TIME_DELAY ; 0 ; Untyped ;
; CLK2_TIME_DELAY ; 0 ; Untyped ;
; CLK1_TIME_DELAY ; 0 ; Untyped ;
; CLK0_TIME_DELAY ; 0 ; Untyped ;
; CLK9_DUTY_CYCLE ; 50 ; Untyped ;
; CLK8_DUTY_CYCLE ; 50 ; Untyped ;
; CLK7_DUTY_CYCLE ; 50 ; Untyped ;
; CLK6_DUTY_CYCLE ; 50 ; Untyped ;
; CLK5_DUTY_CYCLE ; 50 ; Untyped ;
; CLK4_DUTY_CYCLE ; 50 ; Untyped ;
; CLK3_DUTY_CYCLE ; 50 ; Untyped ;
; CLK2_DUTY_CYCLE ; 50 ; Untyped ;
; CLK1_DUTY_CYCLE ; 50 ; Signed Integer ;
; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ;
; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; LOCK_WINDOW_UI ; 0.05 ; Untyped ;
; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ;
; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ;
; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ;
; DPA_MULTIPLY_BY ; 0 ; Untyped ;
; DPA_DIVIDE_BY ; 1 ; Untyped ;
; DPA_DIVIDER ; 0 ; Untyped ;
; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ;
; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ;
; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ;
; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ;
; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ;
; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ;
; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ;
; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ;
; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ;
; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ;
; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ;
; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ;
; EXTCLK3_TIME_DELAY ; 0 ; Untyped ;
; EXTCLK2_TIME_DELAY ; 0 ; Untyped ;
; EXTCLK1_TIME_DELAY ; 0 ; Untyped ;
; EXTCLK0_TIME_DELAY ; 0 ; Untyped ;
; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ;
; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ;
; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ;
; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ;
; VCO_MULTIPLY_BY ; 0 ; Untyped ;
; VCO_DIVIDE_BY ; 0 ; Untyped ;
; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ;
; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ;
; VCO_MIN ; 0 ; Untyped ;
; VCO_MAX ; 0 ; Untyped ;
; VCO_CENTER ; 0 ; Untyped ;
; PFD_MIN ; 0 ; Untyped ;
; PFD_MAX ; 0 ; Untyped ;
; M_INITIAL ; 0 ; Untyped ;
; M ; 0 ; Untyped ;
; N ; 1 ; Untyped ;
; M2 ; 1 ; Untyped ;
; N2 ; 1 ; Untyped ;
; SS ; 1 ; Untyped ;
; C0_HIGH ; 0 ; Untyped ;
; C1_HIGH ; 0 ; Untyped ;
; C2_HIGH ; 0 ; Untyped ;
; C3_HIGH ; 0 ; Untyped ;
; C4_HIGH ; 0 ; Untyped ;
; C5_HIGH ; 0 ; Untyped ;
; C6_HIGH ; 0 ; Untyped ;
; C7_HIGH ; 0 ; Untyped ;
; C8_HIGH ; 0 ; Untyped ;
; C9_HIGH ; 0 ; Untyped ;
; C0_LOW ; 0 ; Untyped ;
; C1_LOW ; 0 ; Untyped ;
; C2_LOW ; 0 ; Untyped ;
; C3_LOW ; 0 ; Untyped ;
; C4_LOW ; 0 ; Untyped ;
; C5_LOW ; 0 ; Untyped ;
; C6_LOW ; 0 ; Untyped ;
; C7_LOW ; 0 ; Untyped ;
; C8_LOW ; 0 ; Untyped ;
; C9_LOW ; 0 ; Untyped ;
; C0_INITIAL ; 0 ; Untyped ;
; C1_INITIAL ; 0 ; Untyped ;
; C2_INITIAL ; 0 ; Untyped ;
; C3_INITIAL ; 0 ; Untyped ;
; C4_INITIAL ; 0 ; Untyped ;
; C5_INITIAL ; 0 ; Untyped ;
; C6_INITIAL ; 0 ; Untyped ;
; C7_INITIAL ; 0 ; Untyped ;
; C8_INITIAL ; 0 ; Untyped ;
; C9_INITIAL ; 0 ; Untyped ;
; C0_MODE ; BYPASS ; Untyped ;
; C1_MODE ; BYPASS ; Untyped ;
; C2_MODE ; BYPASS ; Untyped ;
; C3_MODE ; BYPASS ; Untyped ;
; C4_MODE ; BYPASS ; Untyped ;
; C5_MODE ; BYPASS ; Untyped ;
; C6_MODE ; BYPASS ; Untyped ;
; C7_MODE ; BYPASS ; Untyped ;
; C8_MODE ; BYPASS ; Untyped ;
; C9_MODE ; BYPASS ; Untyped ;
; C0_PH ; 0 ; Untyped ;
; C1_PH ; 0 ; Untyped ;
; C2_PH ; 0 ; Untyped ;
; C3_PH ; 0 ; Untyped ;
; C4_PH ; 0 ; Untyped ;
; C5_PH ; 0 ; Untyped ;
; C6_PH ; 0 ; Untyped ;
; C7_PH ; 0 ; Untyped ;
; C8_PH ; 0 ; Untyped ;
; C9_PH ; 0 ; Untyped ;
; L0_HIGH ; 1 ; Untyped ;
; L1_HIGH ; 1 ; Untyped ;
; G0_HIGH ; 1 ; Untyped ;
; G1_HIGH ; 1 ; Untyped ;
; G2_HIGH ; 1 ; Untyped ;
; G3_HIGH ; 1 ; Untyped ;
; E0_HIGH ; 1 ; Untyped ;
; E1_HIGH ; 1 ; Untyped ;
; E2_HIGH ; 1 ; Untyped ;
; E3_HIGH ; 1 ; Untyped ;
; L0_LOW ; 1 ; Untyped ;
; L1_LOW ; 1 ; Untyped ;
; G0_LOW ; 1 ; Untyped ;
; G1_LOW ; 1 ; Untyped ;
; G2_LOW ; 1 ; Untyped ;
; G3_LOW ; 1 ; Untyped ;
; E0_LOW ; 1 ; Untyped ;
; E1_LOW ; 1 ; Untyped ;
; E2_LOW ; 1 ; Untyped ;
; E3_LOW ; 1 ; Untyped ;
; L0_INITIAL ; 1 ; Untyped ;
; L1_INITIAL ; 1 ; Untyped ;
; G0_INITIAL ; 1 ; Untyped ;
; G1_INITIAL ; 1 ; Untyped ;
; G2_INITIAL ; 1 ; Untyped ;
; G3_INITIAL ; 1 ; Untyped ;
; E0_INITIAL ; 1 ; Untyped ;
; E1_INITIAL ; 1 ; Untyped ;
; E2_INITIAL ; 1 ; Untyped ;
; E3_INITIAL ; 1 ; Untyped ;
; L0_MODE ; BYPASS ; Untyped ;
; L1_MODE ; BYPASS ; Untyped ;
; G0_MODE ; BYPASS ; Untyped ;
; G1_MODE ; BYPASS ; Untyped ;
; G2_MODE ; BYPASS ; Untyped ;
; G3_MODE ; BYPASS ; Untyped ;
; E0_MODE ; BYPASS ; Untyped ;
; E1_MODE ; BYPASS ; Untyped ;
; E2_MODE ; BYPASS ; Untyped ;
; E3_MODE ; BYPASS ; Untyped ;
; L0_PH ; 0 ; Untyped ;
; L1_PH ; 0 ; Untyped ;
; G0_PH ; 0 ; Untyped ;
; G1_PH ; 0 ; Untyped ;
; G2_PH ; 0 ; Untyped ;
; G3_PH ; 0 ; Untyped ;
; E0_PH ; 0 ; Untyped ;
; E1_PH ; 0 ; Untyped ;
; E2_PH ; 0 ; Untyped ;
; E3_PH ; 0 ; Untyped ;
; M_PH ; 0 ; Untyped ;
; C1_USE_CASC_IN ; OFF ; Untyped ;
; C2_USE_CASC_IN ; OFF ; Untyped ;
; C3_USE_CASC_IN ; OFF ; Untyped ;
; C4_USE_CASC_IN ; OFF ; Untyped ;
; C5_USE_CASC_IN ; OFF ; Untyped ;
; C6_USE_CASC_IN ; OFF ; Untyped ;
; C7_USE_CASC_IN ; OFF ; Untyped ;
; C8_USE_CASC_IN ; OFF ; Untyped ;
; C9_USE_CASC_IN ; OFF ; Untyped ;
; CLK0_COUNTER ; G0 ; Untyped ;
; CLK1_COUNTER ; G0 ; Untyped ;
; CLK2_COUNTER ; G0 ; Untyped ;
; CLK3_COUNTER ; G0 ; Untyped ;
; CLK4_COUNTER ; G0 ; Untyped ;
; CLK5_COUNTER ; G0 ; Untyped ;
; CLK6_COUNTER ; E0 ; Untyped ;
; CLK7_COUNTER ; E1 ; Untyped ;
; CLK8_COUNTER ; E2 ; Untyped ;
; CLK9_COUNTER ; E3 ; Untyped ;
; L0_TIME_DELAY ; 0 ; Untyped ;
; L1_TIME_DELAY ; 0 ; Untyped ;
; G0_TIME_DELAY ; 0 ; Untyped ;
; G1_TIME_DELAY ; 0 ; Untyped ;
; G2_TIME_DELAY ; 0 ; Untyped ;
; G3_TIME_DELAY ; 0 ; Untyped ;
; E0_TIME_DELAY ; 0 ; Untyped ;
; E1_TIME_DELAY ; 0 ; Untyped ;
; E2_TIME_DELAY ; 0 ; Untyped ;
; E3_TIME_DELAY ; 0 ; Untyped ;
; M_TIME_DELAY ; 0 ; Untyped ;
; N_TIME_DELAY ; 0 ; Untyped ;
; EXTCLK3_COUNTER ; E3 ; Untyped ;
; EXTCLK2_COUNTER ; E2 ; Untyped ;
; EXTCLK1_COUNTER ; E1 ; Untyped ;
; EXTCLK0_COUNTER ; E0 ; Untyped ;
; ENABLE0_COUNTER ; L0 ; Untyped ;
; ENABLE1_COUNTER ; L0 ; Untyped ;
; CHARGE_PUMP_CURRENT ; 2 ; Untyped ;
; LOOP_FILTER_R ; 1.000000 ; Untyped ;
; LOOP_FILTER_C ; 5 ; Untyped ;
; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ;
; LOOP_FILTER_R_BITS ; 9999 ; Untyped ;
; LOOP_FILTER_C_BITS ; 9999 ; Untyped ;
; VCO_POST_SCALE ; 0 ; Untyped ;
; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ;
; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ;
; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ;
; INTENDED_DEVICE_FAMILY ; MAX 10 ; Untyped ;
; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA2 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ;
; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ;
; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ;
; PORT_CLK0 ; PORT_USED ; Untyped ;
; PORT_CLK1 ; PORT_USED ; Untyped ;
; PORT_CLK2 ; PORT_UNUSED ; Untyped ;
; PORT_CLK3 ; PORT_UNUSED ; Untyped ;
; PORT_CLK4 ; PORT_UNUSED ; Untyped ;
; PORT_CLK5 ; PORT_UNUSED ; Untyped ;
; PORT_CLK6 ; PORT_UNUSED ; Untyped ;
; PORT_CLK7 ; PORT_UNUSED ; Untyped ;
; PORT_CLK8 ; PORT_UNUSED ; Untyped ;
; PORT_CLK9 ; PORT_UNUSED ; Untyped ;
; PORT_SCANDATA ; PORT_UNUSED ; Untyped ;
; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ;
; PORT_SCANDONE ; PORT_UNUSED ; Untyped ;
; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ;
; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ;
; PORT_INCLK1 ; PORT_UNUSED ; Untyped ;
; PORT_INCLK0 ; PORT_USED ; Untyped ;
; PORT_FBIN ; PORT_UNUSED ; Untyped ;
; PORT_PLLENA ; PORT_UNUSED ; Untyped ;
; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ;
; PORT_ARESET ; PORT_UNUSED ; Untyped ;
; PORT_PFDENA ; PORT_UNUSED ; Untyped ;
; PORT_SCANCLK ; PORT_UNUSED ; Untyped ;
; PORT_SCANACLR ; PORT_UNUSED ; Untyped ;
; PORT_SCANREAD ; PORT_UNUSED ; Untyped ;
; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ;
; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_LOCKED ; PORT_UNUSED ; Untyped ;
; PORT_CONFIGUPDATE ; PORT_UNUSED ; Untyped ;
; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ;
; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ;
; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ;
; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ;
; PORT_SCANCLKENA ; PORT_UNUSED ; Untyped ;
; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ;
; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ;
; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ;
; M_TEST_SOURCE ; 5 ; Untyped ;
; C0_TEST_SOURCE ; 5 ; Untyped ;
; C1_TEST_SOURCE ; 5 ; Untyped ;
; C2_TEST_SOURCE ; 5 ; Untyped ;
; C3_TEST_SOURCE ; 5 ; Untyped ;
; C4_TEST_SOURCE ; 5 ; Untyped ;
; C5_TEST_SOURCE ; 5 ; Untyped ;
; C6_TEST_SOURCE ; 5 ; Untyped ;
; C7_TEST_SOURCE ; 5 ; Untyped ;
; C8_TEST_SOURCE ; 5 ; Untyped ;
; C9_TEST_SOURCE ; 5 ; Untyped ;
; CBXI_PARAMETER ; clk_gen_altpll ; Untyped ;
; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ;
; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ;
; WIDTH_CLOCK ; 5 ; Signed Integer ;
; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ;
; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ;
; DEVICE_FAMILY ; MAX 10 ; Untyped ;
; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ;
; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+-------------------------------+---------------------------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart_tx:u_uart_pc ;
+----------------+--------+--------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+--------+--------------------------------------+
; BAUD_RATE ; 115200 ; Signed Integer ;
; CLOCK_FREQ ; 115200 ; Signed Integer ;
+----------------+--------+--------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+------------------------------------------------------------------------------+
; altpll Parameter Settings by Entity Instance ;
+-------------------------------+----------------------------------------------+
; Name ; Value ;
+-------------------------------+----------------------------------------------+
; Number of entity instances ; 1 ;
; Entity Instance ; clk_gen:clk_gen_inst|altpll:altpll_component ;
; -- OPERATION_MODE ; NORMAL ;
; -- PLL_TYPE ; AUTO ;
; -- PRIMARY_CLOCK ; INCLK0 ;
; -- INCLK0_INPUT_FREQUENCY ; 83333 ;
; -- INCLK1_INPUT_FREQUENCY ; 0 ;
; -- VCO_MULTIPLY_BY ; 0 ;
; -- VCO_DIVIDE_BY ; 0 ;
+-------------------------------+----------------------------------------------+
+---------------------------------------------------------------+
; Port Connectivity Checks: "spi_master_2164:u_spi_master_2164" ;
+------+--------+----------+------------------------------------+
; Port ; Type ; Severity ; Details ;
+------+--------+----------+------------------------------------+
; cnt ; Output ; Info ; Explicitly unconnected ;
+------+--------+----------+------------------------------------+
+----------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "clk_gen:clk_gen_inst" ;
+------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+------+--------+----------+-------------------------------------------------------------------------------------+
; c1 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+------+--------+----------+-------------------------------------------------------------------------------------+
+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-----------------------+-----------------------------+
; Type ; Count ;
+-----------------------+-----------------------------+
; boundary_port ; 13 ;
; cycloneiii_ff ; 135 ;
; CLR ; 58 ;
; CLR SCLR ; 7 ;
; ENA ; 43 ;
; ENA CLR ; 25 ;
; plain ; 2 ;
; cycloneiii_lcell_comb ; 126 ;
; arith ; 21 ;
; 2 data inputs ; 20 ;
; 3 data inputs ; 1 ;
; normal ; 105 ;
; 0 data inputs ; 2 ;
; 1 data inputs ; 7 ;
; 2 data inputs ; 7 ;
; 3 data inputs ; 29 ;
; 4 data inputs ; 60 ;
; cycloneiii_pll ; 1 ;
; ; ;
; Max LUT depth ; 8.00 ;
; Average LUT depth ; 3.04 ;
+-----------------------+-----------------------------+
+-------------------------------+
; Elapsed Time Per Partition ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top ; 00:00:00 ;
+----------------+--------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
Info: Processing started: Thu Dec 11 18:00:15 2025
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off intan_m10 -c intan_m10
Info (20032): Parallel compilation is enabled and will use up to 4 processors
Info (12021): Found 1 design units, including 1 entities, in source file spi_master_2164.v
Info (12023): Found entity 1: spi_master_2164 File: E:/FPGA/puart2/spi_master_2164.v Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file ddr_ctrl.v
Info (12023): Found entity 1: ddr_ctrl File: E:/FPGA/puart2/ddr_ctrl.v Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file clk_gen.v
Info (12023): Found entity 1: clk_gen File: E:/FPGA/puart2/clk_gen.v Line: 39
Warning (12019): Can't analyze file -- file ../../20240625.v is missing
Info (12021): Found 1 design units, including 1 entities, in source file spi_master_esp32.v
Info (12023): Found entity 1: spi_master_esp32 File: E:/FPGA/puart2/spi_master_esp32.v Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file uart_tx.v
Info (12023): Found entity 1: uart_tx File: E:/FPGA/puart2/uart_tx.v Line: 1
Info (12127): Elaborating entity "ddr_ctrl" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at ddr_ctrl.v(71): object "received_data" assigned a value but never read File: E:/FPGA/puart2/ddr_ctrl.v Line: 71
Warning (10763): Verilog HDL warning at ddr_ctrl.v(153): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness File: E:/FPGA/puart2/ddr_ctrl.v Line: 153
Warning (10208): Verilog HDL Case Statement warning at ddr_ctrl.v(153): honored full_case synthesis attribute - differences between design synthesis and simulation may occur File: E:/FPGA/puart2/ddr_ctrl.v Line: 153
Info (12128): Elaborating entity "clk_gen" for hierarchy "clk_gen:clk_gen_inst" File: E:/FPGA/puart2/ddr_ctrl.v Line: 204
Info (12128): Elaborating entity "altpll" for hierarchy "clk_gen:clk_gen_inst|altpll:altpll_component" File: E:/FPGA/puart2/clk_gen.v Line: 94
Info (12130): Elaborated megafunction instantiation "clk_gen:clk_gen_inst|altpll:altpll_component" File: E:/FPGA/puart2/clk_gen.v Line: 94
Info (12133): Instantiated megafunction "clk_gen:clk_gen_inst|altpll:altpll_component" with the following parameter: File: E:/FPGA/puart2/clk_gen.v Line: 94
Info (12134): Parameter "bandwidth_type" = "AUTO"
Info (12134): Parameter "clk0_divide_by" = "625"
Info (12134): Parameter "clk0_duty_cycle" = "50"
Info (12134): Parameter "clk0_multiply_by" = "6"
Info (12134): Parameter "clk0_phase_shift" = "0"
Info (12134): Parameter "clk1_divide_by" = "625"
Info (12134): Parameter "clk1_duty_cycle" = "50"
Info (12134): Parameter "clk1_multiply_by" = "12"
Info (12134): Parameter "clk1_phase_shift" = "0"
Info (12134): Parameter "compensate_clock" = "CLK0"
Info (12134): Parameter "inclk0_input_frequency" = "83333"
Info (12134): Parameter "intended_device_family" = "MAX 10"
Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=clk_gen"
Info (12134): Parameter "lpm_type" = "altpll"
Info (12134): Parameter "operation_mode" = "NORMAL"
Info (12134): Parameter "pll_type" = "AUTO"
Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
Info (12134): Parameter "port_areset" = "PORT_UNUSED"
Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
Info (12134): Parameter "port_inclk0" = "PORT_USED"
Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
Info (12134): Parameter "port_locked" = "PORT_UNUSED"
Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
Info (12134): Parameter "port_clk0" = "PORT_USED"
Info (12134): Parameter "port_clk1" = "PORT_USED"
Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
Info (12134): Parameter "width_clock" = "5"
Info (12021): Found 1 design units, including 1 entities, in source file db/clk_gen_altpll.v
Info (12023): Found entity 1: clk_gen_altpll File: E:/FPGA/puart2/db/clk_gen_altpll.v Line: 29
Info (12128): Elaborating entity "clk_gen_altpll" for hierarchy "clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated" File: e:/quartuslite/quartus/libraries/megafunctions/altpll.tdf Line: 897
Info (12128): Elaborating entity "spi_master_2164" for hierarchy "spi_master_2164:u_spi_master_2164" File: E:/FPGA/puart2/ddr_ctrl.v Line: 221
Info (12128): Elaborating entity "spi_master_esp32" for hierarchy "spi_master_esp32:tranfer" File: E:/FPGA/puart2/ddr_ctrl.v Line: 234
Warning (10230): Verilog HDL assignment warning at spi_master_esp32.v(50): truncated value with size 32 to match size of target (4) File: E:/FPGA/puart2/spi_master_esp32.v Line: 50
Info (12128): Elaborating entity "uart_tx" for hierarchy "uart_tx:u_uart_pc" File: E:/FPGA/puart2/ddr_ctrl.v Line: 243
Warning (10230): Verilog HDL assignment warning at uart_tx.v(32): truncated value with size 32 to match size of target (16) File: E:/FPGA/puart2/uart_tx.v Line: 32
Warning (10230): Verilog HDL assignment warning at uart_tx.v(74): truncated value with size 32 to match size of target (4) File: E:/FPGA/puart2/uart_tx.v Line: 74
Info (13000): Registers with preset signals will power-up high File: E:/FPGA/puart2/spi_master_2164.v Line: 11
Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "MOSI_ESP32" is stuck at GND File: E:/FPGA/puart2/ddr_ctrl.v Line: 12
Warning (13410): Pin "cs_ESP32" is stuck at VCC File: E:/FPGA/puart2/ddr_ctrl.v Line: 13
Warning (13410): Pin "sclk_ESP32" is stuck at GND File: E:/FPGA/puart2/ddr_ctrl.v Line: 14
Info (286030): Timing-Driven Synthesis is running
Info (17049): 6 registers lost all their fanouts during netlist optimizations.
Info (144001): Generated suppressed messages file E:/FPGA/puart2/output_files/intan_m10.map.smsg
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL
Warning (15899): PLL "clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected File: E:/FPGA/puart2/db/clk_gen_altpll.v Line: 43
Info (21057): Implemented 213 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 4 input pins
Info (21059): Implemented 9 output pins
Info (21061): Implemented 199 logic cells
Info (21065): Implemented 1 PLLs
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings
Info: Peak virtual memory: 4766 megabytes
Info: Processing ended: Thu Dec 11 18:00:25 2025
Info: Elapsed time: 00:00:10
Info: Total CPU time (on all processors): 00:00:21
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in E:/FPGA/puart2/output_files/intan_m10.map.smsg.