TJU-SUN-LAB
/
waveform_acquisition_FPGA_code
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

update

This commit is contained in:
dsfsdf 2025-12-11 18:35:48 +08:00
commit 58bb0da74b
308 changed files with 17759 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
puart2/.qsys_edit/filters.xml Normal file
View File

@ -0,0 +1,2 @@
<?xml version="1.0" encoding="UTF-8"?>
<filters version="17.1" />

12
puart2/.qsys_edit/preferences.xml Normal file
View File

@ -0,0 +1,12 @@
<?xml version="1.0" encoding="UTF-8"?>
<preferences>
<debug showDebugMenu="0" />
<systemtable filter="All Interfaces">
<columns>
<connections preferredWidth="47" />
<irq preferredWidth="34" />
</columns>
</systemtable>
<library expandedCategories="Project,Library" />
<window width="1100" height="800" x="0" y="0" />
</preferences>

52
puart2/__intan_m10.auto.qarlog Normal file
View File

@ -0,0 +1,52 @@
Quartus Prime Archive log -- E:/FPGA/SPItransfer/20240726/__intan_m10.auto.qarlog
Archive: E:/FPGA/SPItransfer/20240726/__intan_m10.auto.qar
Date: Sat Sep 21 09:52:33 2024
Quartus Prime 17.1.0 Build 590 10/25/2017 SJ Lite Edition
=========== Files Selected: ===========
E:/FPGA/SPItransfer/20240726/clk_gen.qip
E:/FPGA/SPItransfer/20240726/clk_gen.v
E:/FPGA/SPItransfer/20240726/db/clk_gen_altpll.v
E:/FPGA/SPItransfer/20240726/db/intan_m10.cbx.xml
E:/FPGA/SPItransfer/20240726/db/intan_m10.qpf
E:/FPGA/SPItransfer/20240726/ddr_ctrl.v
E:/FPGA/SPItransfer/20240726/output_files/intan_m10.asm.rpt
E:/FPGA/SPItransfer/20240726/output_files/intan_m10.cdf
E:/FPGA/SPItransfer/20240726/output_files/intan_m10.done
E:/FPGA/SPItransfer/20240726/output_files/intan_m10.eda.rpt
E:/FPGA/SPItransfer/20240726/output_files/intan_m10.fit.rpt
E:/FPGA/SPItransfer/20240726/output_files/intan_m10.fit.smsg
E:/FPGA/SPItransfer/20240726/output_files/intan_m10.fit.summary
E:/FPGA/SPItransfer/20240726/output_files/intan_m10.flow.rpt
E:/FPGA/SPItransfer/20240726/output_files/intan_m10.jdi
E:/FPGA/SPItransfer/20240726/output_files/intan_m10.map.rpt
E:/FPGA/SPItransfer/20240726/output_files/intan_m10.map.smsg
E:/FPGA/SPItransfer/20240726/output_files/intan_m10.map.summary
E:/FPGA/SPItransfer/20240726/output_files/intan_m10.pin
E:/FPGA/SPItransfer/20240726/output_files/intan_m10.pof
E:/FPGA/SPItransfer/20240726/output_files/intan_m10.pow.rpt
E:/FPGA/SPItransfer/20240726/output_files/intan_m10.pow.summary
E:/FPGA/SPItransfer/20240726/output_files/intan_m10.sld
E:/FPGA/SPItransfer/20240726/output_files/intan_m10.sof
E:/FPGA/SPItransfer/20240726/output_files/intan_m10.sta.rpt
E:/FPGA/SPItransfer/20240726/output_files/intan_m10.sta.summary
E:/FPGA/SPItransfer/20240726/spi_master_2164.v
E:/FPGA/SPItransfer/20240726/spi_master_esp32.v
clk_gen.ppf
clk_gen_bb.v
clk_gen_inst.v
clkgen.ppf
clkgen.qip
clkgen.v
clkgen_bb.v
clkgen_inst.v
ddr_ctrl_tb.v
e:/quartuslite/quartus/bin64/assignment_defaults.qdf
intan_m10.qsf
intan_m10.v
intan_m10_assignment_defaults.qdf
======= Total: 41 files to archive =======
================ Status: ===============
All files archived successfully.

10
puart2/clk_gen.ppf Normal file
View File

@ -0,0 +1,10 @@
<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="MAX 10" variation_name="clk_gen" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="c0" direction="output" scope="external" source="clock" />
<pin name="c1" direction="output" scope="external" source="clock" />
</global>
</pinplan>

7
puart2/clk_gen.qip Normal file
View File

@ -0,0 +1,7 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "17.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "clk_gen.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clk_gen_inst.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clk_gen_bb.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clk_gen.ppf"]

332
puart2/clk_gen.v Normal file
View File

@ -0,0 +1,332 @@
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: clk_gen.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.1.0 Build 590 10/25/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module clk_gen (
inclk0,
c0,
c1);
input inclk0;
output c0;
output c1;
wire [0:0] sub_wire2 = 1'h0;
wire [4:0] sub_wire3;
wire sub_wire0 = inclk0;
wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
wire [1:1] sub_wire5 = sub_wire3[1:1];
wire [0:0] sub_wire4 = sub_wire3[0:0];
wire c0 = sub_wire4;
wire c1 = sub_wire5;
altpll altpll_component (
.inclk (sub_wire1),
.clk (sub_wire3),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 625,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 6,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 625,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 12,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 83333,
altpll_component.intended_device_family = "MAX 10",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=clk_gen",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "104"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "52"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.115200"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "0.230400"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "12.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.11520000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "0.23040000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clk_gen.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "625"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "6"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "625"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "12"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "83333"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

219
puart2/clk_gen_bb.v Normal file
View File

@ -0,0 +1,219 @@
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: clk_gen.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.1.0 Build 590 10/25/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
module clk_gen (
inclk0,
c0,
c1);
input inclk0;
output c0;
output c1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "104"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "52"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.115200"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "0.230400"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "12.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.11520000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "0.23040000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clk_gen.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "625"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "6"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "625"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "12"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "83333"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

5
puart2/clk_gen_inst.v Normal file
View File

@ -0,0 +1,5 @@
clk_gen clk_gen_inst (
.inclk0 ( inclk0_sig ),
.c0 ( c0_sig ),
.c1 ( c1_sig )
);

9
puart2/clkgen.ppf Normal file
View File

@ -0,0 +1,9 @@
<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="MAX 10" variation_name="clkgen" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="c0" direction="output" scope="external" source="clock" />
</global>
</pinplan>

7
puart2/clkgen.qip Normal file
View File

@ -0,0 +1,7 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "17.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "clkgen.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clkgen_inst.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clkgen_bb.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clkgen.ppf"]

305
puart2/clkgen.v Normal file
View File

@ -0,0 +1,305 @@
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: clkgen.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.1.0 Build 590 10/25/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module clkgen (
inclk0,
c0);
input inclk0;
output c0;
wire [0:0] sub_wire2 = 1'h0;
wire [4:0] sub_wire3;
wire sub_wire0 = inclk0;
wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
wire [0:0] sub_wire4 = sub_wire3[0:0];
wire c0 = sub_wire4;
altpll altpll_component (
.inclk (sub_wire1),
.clk (sub_wire3),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 6,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 83333,
altpll_component.intended_device_family = "MAX 10",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=clkgen",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "6"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "2.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "12.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clkgen.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "6"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "83333"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

198
puart2/clkgen_bb.v Normal file
View File

@ -0,0 +1,198 @@
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: clkgen.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.1.0 Build 590 10/25/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
module clkgen (
inclk0,
c0);
input inclk0;
output c0;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "6"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "2.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "12.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clkgen.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "6"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "83333"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

4
puart2/clkgen_inst.v Normal file
View File

@ -0,0 +1,4 @@
clkgen clkgen_inst (
.inclk0 ( inclk0_sig ),
.c0 ( c0_sig )
);

BIN
puart2/db/.cmp.kpt Normal file
View File

Binary file not shown.

96
puart2/db/clk_gen_altpll.v Normal file
View File

@ -0,0 +1,96 @@
//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=625 clk0_duty_cycle=50 clk0_multiply_by=6 clk0_phase_shift="0" clk1_divide_by=625 clk1_duty_cycle=50 clk1_multiply_by=12 clk1_phase_shift="0" compensate_clock="CLK0" device_family="MAX 10" inclk0_input_frequency=83333 intended_device_family="MAX 10" lpm_hint="CBX_MODULE_PREFIX=clk_gen" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 clk inclk CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
//VERSION_BEGIN 17.1 cbx_altclkbuf 2017:10:25:18:06:52:SJ cbx_altiobuf_bidir 2017:10:25:18:06:52:SJ cbx_altiobuf_in 2017:10:25:18:06:52:SJ cbx_altiobuf_out 2017:10:25:18:06:52:SJ cbx_altpll 2017:10:25:18:06:53:SJ cbx_cycloneii 2017:10:25:18:06:53:SJ cbx_lpm_add_sub 2017:10:25:18:06:53:SJ cbx_lpm_compare 2017:10:25:18:06:53:SJ cbx_lpm_counter 2017:10:25:18:06:53:SJ cbx_lpm_decode 2017:10:25:18:06:53:SJ cbx_lpm_mux 2017:10:25:18:06:53:SJ cbx_mgl 2017:10:25:18:08:29:SJ cbx_nadder 2017:10:25:18:06:53:SJ cbx_stratix 2017:10:25:18:06:53:SJ cbx_stratixii 2017:10:25:18:06:53:SJ cbx_stratixiii 2017:10:25:18:06:53:SJ cbx_stratixv 2017:10:25:18:06:53:SJ cbx_util_mgl 2017:10:25:18:06:53:SJ VERSION_END
//CBXI_INSTANCE_NAME="ddr_ctrl_clk_gen_clk_gen_inst_altpll_altpll_component"
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors. Please
// refer to the applicable agreement for further details.
//synthesis_resources = fiftyfivenm_pll 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module clk_gen_altpll
(
clk,
inclk) /* synthesis synthesis_clearbox=1 */;
output [4:0] clk;
input [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] wire_pll1_clk;
wire wire_pll1_fbout;
fiftyfivenm_pll pll1
(
.activeclock(),
.clk(wire_pll1_clk),
.clkbad(),
.fbin(wire_pll1_fbout),
.fbout(wire_pll1_fbout),
.inclk(inclk),
.locked(),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll1.bandwidth_type = "auto",
pll1.clk0_divide_by = 625,
pll1.clk0_duty_cycle = 50,
pll1.clk0_multiply_by = 6,
pll1.clk0_phase_shift = "0",
pll1.clk1_divide_by = 625,
pll1.clk1_duty_cycle = 50,
pll1.clk1_multiply_by = 12,
pll1.clk1_phase_shift = "0",
pll1.compensate_clock = "clk0",
pll1.inclk0_input_frequency = 83333,
pll1.operation_mode = "normal",
pll1.pll_type = "auto",
pll1.lpm_type = "fiftyfivenm_pll";
assign
clk = {wire_pll1_clk[4:0]};
endmodule //clk_gen_altpll
//VALID FILE

BIN
puart2/db/intan_m10.(0).cnf.cdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.(0).cnf.hdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.(1).cnf.cdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.(1).cnf.hdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.(10).cnf.cdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.(10).cnf.hdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.(2).cnf.cdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.(2).cnf.hdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.(3).cnf.cdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.(3).cnf.hdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.(4).cnf.cdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.(4).cnf.hdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.(5).cnf.cdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.(5).cnf.hdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.(6).cnf.cdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.(6).cnf.hdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.(7).cnf.cdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.(7).cnf.hdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.(8).cnf.cdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.(8).cnf.hdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.(9).cnf.cdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.(9).cnf.hdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.ace_cmp.bpm Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.ace_cmp.cdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.ace_cmp.hdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.ae.hdb Normal file
View File

Binary file not shown.

21
puart2/db/intan_m10.archive.qmsg Normal file
View File

@ -0,0 +1,21 @@
{ "Info" "0" "" "File Set 'Source control' contains:" { { "Info" "0" "" "Project source and settings files" { } { } 0 0 "Project source and settings files" 0 0 "0" 0 0 1726883553136 ""} { "Info" "0" "" "Automatically detected source files" { } { } 0 0 "Automatically detected source files" 0 0 "0" 0 0 1726883553136 ""} } { } 0 0 "File Set 'Source control' contains:" 0 0 "Shell" 0 0 1726883553136 ""}
{ "Warning" "0" "" "Hierarchical Platform Designer systems and custom IP components(_hw.tcl and associated files) are not archived by the Quartus Archiver" { } { } 0 0 "Hierarchical Platform Designer systems and custom IP components(_hw.tcl and associated files) are not archived by the Quartus Archiver" 0 0 "Shell" 0 0 1726883553166 ""}
{ "Critical Warning" "0" "" "Analysis & Elaboration was not run successfully." { { "Critical Warning" "0" "" "The 'Automatically detected source files' file subset will attempt to guess which files are needed. The archive file will likely be larger than required and may still be incomplete." { } { } 1 0 "The 'Automatically detected source files' file subset will attempt to guess which files are needed. The archive file will likely be larger than required and may still be incomplete." 0 0 "0" 0 0 1726883553166 ""} } { } 1 0 "Analysis & Elaboration was not run successfully." 0 0 "Shell" 0 0 1726883553166 ""}
{ "Warning" "WPRJ_ARC_TCL_HDB_REQUIRE_FILES_NOT_EXIST" "20240625.v " "Can't find required hierarchy file 20240625.v" { } { } 0 225003 "Can't find required hierarchy file %1!s!" 0 0 "Shell" 0 -1 1726883553176 ""}
{ "Info" "0" "" "Parsing: spi_master_2164.v" { } { } 0 0 "Parsing: spi_master_2164.v" 0 0 "Shell" 0 0 1726883553306 ""}
{ "Info" "0" "" "Parsing: ddr_ctrl.v" { } { } 0 0 "Parsing: ddr_ctrl.v" 0 0 "Shell" 0 0 1726883553306 ""}
{ "Info" "0" "" "Parsing: clk_gen.v" { } { } 0 0 "Parsing: clk_gen.v" 0 0 "Shell" 0 0 1726883553306 ""}
{ "Info" "0" "" "Parsing: clk_gen_inst.v" { } { } 0 0 "Parsing: clk_gen_inst.v" 0 0 "Shell" 0 0 1726883553306 ""}
{ "Info" "0" "" "Parsing: clk_gen_bb.v" { } { } 0 0 "Parsing: clk_gen_bb.v" 0 0 "Shell" 0 0 1726883553316 ""}
{ "Info" "0" "" "Parsing: spi_master_esp32.v" { } { } 0 0 "Parsing: spi_master_esp32.v" 0 0 "Shell" 0 0 1726883553316 ""}
{ "Info" "0" "" "Parsing: intan_m10.v" { } { } 0 0 "Parsing: intan_m10.v" 0 0 "Shell" 0 0 1726883553316 ""}
{ "Info" "0" "" "Archive will store files relative to the closest common parent directory" { } { } 0 0 "Archive will store files relative to the closest common parent directory" 0 0 "Shell" 0 0 1726883553316 ""}
{ "Info" "IPRJ_ARC_TCL_TCL_USING_COMMON_DIR" "E:/FPGA/SPItransfer/20240726/ " "Using common directory E:/FPGA/SPItransfer/20240726/" { } { } 0 13213 "Using common directory %1!s!" 0 0 "Shell" 0 -1 1726883553336 ""}
{ "Info" "0" "" "----------------------------------------------------------" { } { } 0 0 "----------------------------------------------------------" 0 0 "Shell" 0 0 1726883553366 ""}
{ "Info" "0" "" "----------------------------------------------------------" { } { } 0 0 "----------------------------------------------------------" 0 0 "Shell" 0 0 1726883553366 ""}
{ "Info" "0" "" "Generated archive 'E:/FPGA/SPItransfer/20240726/uart_tx.qar'" { } { } 0 0 "Generated archive 'E:/FPGA/SPItransfer/20240726/uart_tx.qar'" 0 0 "Shell" 0 0 1726883553366 ""}
{ "Info" "0" "" "----------------------------------------------------------" { } { } 0 0 "----------------------------------------------------------" 0 0 "Shell" 0 0 1726883553366 ""}
{ "Info" "0" "" "----------------------------------------------------------" { } { } 0 0 "----------------------------------------------------------" 0 0 "Shell" 0 0 1726883553366 ""}
{ "Info" "0" "" "Generated report 'intan_m10.archive.rpt'" { } { } 0 0 "Generated report 'intan_m10.archive.rpt'" 0 0 "Shell" 0 0 1726883553376 ""}
{ "Error" "EQEXE_TCL_SCRIPT_STATUS" "e:/quartuslite/quartus/common/tcl/apps/qpm/qar.tcl " "Evaluation of Tcl script e:/quartuslite/quartus/common/tcl/apps/qpm/qar.tcl unsuccessful" { } { } 0 23031 "Evaluation of Tcl script %1!s! unsuccessful" 0 0 "Shell" 0 -1 1726883553376 ""}
{ "Error" "EQEXE_ERROR_COUNT" "Shell 6 s 17 s Quartus Prime " "Quartus Prime Shell was unsuccessful. 6 errors, 17 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "4826 " "Peak virtual memory: 4826 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1726883553376 ""} { "Error" "EQEXE_END_BANNER_TIME" "Sat Sep 21 09:52:33 2024 " "Processing ended: Sat Sep 21 09:52:33 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1726883553376 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1726883553376 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:20 " "Total CPU time (on all processors): 00:00:20" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1726883553376 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Shell" 0 -1 1726883553376 ""}

21
puart2/db/intan_m10.archiver.cache Normal file
View File

@ -0,0 +1,21 @@
file:E:/FPGA/SPItransfer/20240726/intan_m10.v
ts:1726883210
init:
file:E:/FPGA/SPItransfer/20240726/spi_master_esp32.v
ts:1726153605
init:
file:E:/FPGA/SPItransfer/20240726/clk_gen.v
ts:1726279939
init:
file:E:/FPGA/SPItransfer/20240726/spi_master_2164.v
ts:1726034143
init:
file:E:/FPGA/SPItransfer/20240726/clk_gen_inst.v
ts:1726279939
init:
file:E:/FPGA/SPItransfer/20240726/clk_gen_bb.v
ts:1726279939
init:
file:E:/FPGA/SPItransfer/20240726/ddr_ctrl.v
ts:1726883080
init:

6
puart2/db/intan_m10.asm.qmsg Normal file
View File

@ -0,0 +1,6 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1765447233049 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1765447233062 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 11 18:00:32 2025 " "Processing started: Thu Dec 11 18:00:32 2025" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1765447233062 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1765447233062 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1765447233063 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1765447233787 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1765447233821 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4672 " "Peak virtual memory: 4672 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1765447234216 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 11 18:00:34 2025 " "Processing ended: Thu Dec 11 18:00:34 2025" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1765447234216 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1765447234216 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1765447234216 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1765447234216 ""}

BIN
puart2/db/intan_m10.asm.rdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.asm_labs.ddb Normal file
View File

Binary file not shown.

5
puart2/db/intan_m10.cbx.xml Normal file
View File

@ -0,0 +1,5 @@
<?xml version="1.0" ?>
<LOG_ROOT>
<PROJECT NAME="intan_m10">
</PROJECT>
</LOG_ROOT>

BIN
puart2/db/intan_m10.cmp.bpm Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.cmp.cdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.cmp.hdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.cmp.idb Normal file
View File

Binary file not shown.

54
puart2/db/intan_m10.cmp.logdb Normal file
View File

@ -0,0 +1,54 @@
v1
IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,
IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os.,Critical,0 such failures found.,,I/O,,
IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
IO_RULES_MATRIX,Total Pass,13;0;13;0;0;13;13;0;13;13;0;0;0;0;4;0;0;4;0;0;0;0;0;0;0;0;0;13;0;0,
IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,Total Inapplicable,0;13;0;13;13;0;0;13;0;0;13;13;13;13;9;13;13;9;13;13;13;13;13;13;13;13;13;0;13;13,
IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,mosi,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,cs_n,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,sclk,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,MOSI_ESP32,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,cs_ESP32,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,sclk_ESP32,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,tx,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,test_flag_led,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,convert_flag_led,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,test_flag,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,rst_n,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,sys_clk,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,miso,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_SUMMARY,Total I/O Rules,30,
IO_RULES_SUMMARY,Number of I/O Rules Passed,9,
IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,21,

BIN
puart2/db/intan_m10.cmp.rdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.cmp_merge.kpt Normal file
View File

Binary file not shown.

3
puart2/db/intan_m10.db_info Normal file
View File

@ -0,0 +1,3 @@
Quartus_Version = Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
Version_Index = 453135872
Creation_Time = Thu Dec 11 17:21:09 2025

BIN
puart2/db/intan_m10.eco.cdb Normal file
View File

Binary file not shown.

54
puart2/db/intan_m10.fit.qmsg Normal file
View File

@ -0,0 +1,54 @@
{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "4 " "Parallel compilation is enabled and will use up to 4 processors" { } { } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Fitter" 0 -1 1765447227432 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "intan_m10 10M08SAM153C8G " "Selected device 10M08SAM153C8G for design \"intan_m10\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1765447227440 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1765447227474 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1765447227474 ""}
{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|pll1 MAX 10 PLL " "Implemented PLL \"clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|pll1\" as MAX 10 PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] 6 625 0 0 " "Implementing clock multiplication of 6, clock division of 625, and phase shift of 0 degrees (0 ps) for clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/clk_gen_altpll.v" "" { Text "E:/FPGA/puart2/db/clk_gen_altpll.v" 43 -1 0 } } { "" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 124 14177 15141 0 0 "" 0 "" "" } } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Design Software" 0 -1 1765447227517 ""} } { { "db/clk_gen_altpll.v" "" { Text "E:/FPGA/puart2/db/clk_gen_altpll.v" 43 -1 0 } } { "" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 124 14177 15141 0 0 "" 0 "" "" } } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1765447227517 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1765447227564 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1765447227572 ""}
{ "Critical Warning" "WFCUDA_FCUDA_SPS_DEVICE_POWER_LIMITATION" "" "Review the Power Analyzer report file (<design>.pow.rpt) to ensure your design is within the maximum power utilization limit of the single power-supply target device and to avoid functional failures." { } { } 1 16562 "Review the Power Analyzer report file (<design>.pow.rpt) to ensure your design is within the maximum power utilization limit of the single power-supply target device and to avoid functional failures." 0 0 "Fitter" 0 -1 1765447227690 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M08SAM153C8GES " "Device 10M08SAM153C8GES is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1765447227701 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M04SAM153C8G " "Device 10M04SAM153C8G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1765447227701 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1765447227701 ""}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "8 " "Fitter converted 8 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TMS~ G1 " "Pin ~ALTERA_TMS~ is reserved at location G1" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { ~ALTERA_TMS~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 395 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765447227702 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TCK~ J1 " "Pin ~ALTERA_TCK~ is reserved at location J1" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { ~ALTERA_TCK~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 397 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765447227702 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDI~ H5 " "Pin ~ALTERA_TDI~ is reserved at location H5" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDI~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 399 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765447227702 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDO~ H4 " "Pin ~ALTERA_TDO~ is reserved at location H4" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDO~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 401 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765447227702 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONFIG_SEL~ D8 " "Pin ~ALTERA_CONFIG_SEL~ is reserved at location D8" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONFIG_SEL~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 403 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765447227702 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCONFIG~ E8 " "Pin ~ALTERA_nCONFIG~ is reserved at location E8" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCONFIG~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 405 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765447227702 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nSTATUS~ D6 " "Pin ~ALTERA_nSTATUS~ is reserved at location D6" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { ~ALTERA_nSTATUS~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 407 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765447227702 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONF_DONE~ E6 " "Pin ~ALTERA_CONF_DONE~ is reserved at location E6" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONF_DONE~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 409 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765447227702 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1765447227702 ""}
{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" { } { } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1765447227703 ""}
{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1765447227703 ""}
{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1765447227703 ""}
{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1765447227703 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1765447227703 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "intan_m10.sdc " "Synopsys Design Constraints File file not found: 'intan_m10.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1765447228110 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "generated clocks " "No user constrained generated clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1765447228110 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1765447228111 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1765447228114 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1765447228114 ""}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1765447228114 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C1 of PLL_1) " "Automatically promoted node clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C1 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1765447228130 ""} } { { "db/clk_gen_altpll.v" "" { Text "E:/FPGA/puart2/db/clk_gen_altpll.v" 77 -1 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 124 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1765447228130 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "spi_master_2164:u_spi_master_2164\|cs_n " "Automatically promoted node spi_master_2164:u_spi_master_2164\|cs_n " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1765447228130 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "cs_n~output " "Destination node cs_n~output" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 9 0 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 376 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1765447228130 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1765447228130 ""} } { { "spi_master_2164.v" "" { Text "E:/FPGA/puart2/spi_master_2164.v" 11 -1 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 119 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1765447228130 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1765447228429 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1765447228430 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1765447228430 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1765447228431 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1765447228431 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1765447228432 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1765447228432 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1765447228432 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1765447228442 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1765447228443 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1765447228443 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1765447228463 ""}
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1765447228466 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1765447228928 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1765447228977 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1765447228986 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1765447229349 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1765447229349 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1765447229707 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X10_Y0 X20_Y12 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X10_Y0 to location X20_Y12" { } { { "loc" "" { Generic "E:/FPGA/puart2/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X10_Y0 to location X20_Y12"} { { 12 { 0 ""} 10 0 11 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1765447230052 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1765447230052 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1765447230330 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1765447230330 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1765447230333 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.15 " "Total time spent on timing analysis during the Fitter is 0.15 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1765447230488 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1765447230493 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1765447230679 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1765447230680 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1765447230967 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1765447231409 ""}
{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "4 MAX 10 " "4 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing MAX 10 Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "test_flag 3.3-V LVCMOS J12 " "Pin test_flag uses I/O standard 3.3-V LVCMOS at J12" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { test_flag } } } { "e:/quartuslite/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/quartuslite/quartus/bin64/Assignment Editor.qase" 1 { { 0 "test_flag" } } } } { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 4 0 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 11 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1765447231526 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "rst_n 3.3-V LVCMOS J14 " "Pin rst_n uses I/O standard 3.3-V LVCMOS at J14" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { rst_n } } } { "e:/quartuslite/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/quartuslite/quartus/bin64/Assignment Editor.qase" 1 { { 0 "rst_n" } } } } { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 3 0 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 10 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1765447231526 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "sys_clk 3.3-V LVCMOS J5 " "Pin sys_clk uses I/O standard 3.3-V LVCMOS at J5" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { sys_clk } } } { "e:/quartuslite/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/quartuslite/quartus/bin64/Assignment Editor.qase" 1 { { 0 "sys_clk" } } } } { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 2 0 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 9 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1765447231526 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "miso 3.3-V LVCMOS P4 " "Pin miso uses I/O standard 3.3-V LVCMOS at P4" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { miso } } } { "e:/quartuslite/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/quartuslite/quartus/bin64/Assignment Editor.qase" 1 { { 0 "miso" } } } } { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 7 0 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 12 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1765447231526 ""} } { } 0 169177 "%1!d! pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1765447231526 ""}
{ "Warning" "WFIOMGR_INCONSISTENT_VCCIO_ACROSS_MULTIPLE_BANKS_OF_CONFIGURAION_PINS" "2 Internal Configuration 2 " "Inconsistent VCCIO across multiple banks of configuration pins. The configuration pins are contained in 2 banks in 'Internal Configuration' configuration scheme and there are 2 different VCCIOs." { } { } 0 169202 "Inconsistent VCCIO across multiple banks of configuration pins. The configuration pins are contained in %1!d! banks in '%2!s!' configuration scheme and there are %3!d! different VCCIOs." 0 0 "Fitter" 0 -1 1765447231527 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/FPGA/puart2/output_files/intan_m10.fit.smsg " "Generated suppressed messages file E:/FPGA/puart2/output_files/intan_m10.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1765447231568 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5547 " "Peak virtual memory: 5547 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1765447231939 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 11 18:00:31 2025 " "Processing ended: Thu Dec 11 18:00:31 2025" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1765447231939 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1765447231939 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1765447231939 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1765447231939 ""}

460
puart2/db/intan_m10.hier_info Normal file
View File

@ -0,0 +1,460 @@
|ddr_ctrl
sys_clk => sys_clk.IN2
rst_n => rst_n.IN3
test_flag => Selector12.IN4
test_flag => test_flag_led.DATAIN
test_flag => convert_flag_led.DATAIN
test_flag => Selector8.IN2
test_flag => Selector9.IN2
test_flag => Selector10.IN2
test_flag => Selector11.IN2
test_flag => Selector7.IN2
miso => miso.IN1
mosi <= spi_master_2164:u_spi_master_2164.mosi
cs_n <= spi_master_2164:u_spi_master_2164.cs_n
sclk <= spi_master_2164:u_spi_master_2164.sclk
MOSI_ESP32 <= spi_master_esp32:tranfer.mosi
cs_ESP32 <= spi_master_esp32:tranfer.cs
sclk_ESP32 <= spi_master_esp32:tranfer.sclk
tx <= uart_tx:u_uart_pc.tx
test_flag_led <= test_flag.DB_MAX_OUTPUT_PORT_TYPE
convert_flag_led <= test_flag.DB_MAX_OUTPUT_PORT_TYPE
|ddr_ctrl|clk_gen:clk_gen_inst
inclk0 => sub_wire1[0].IN1
c0 <= altpll:altpll_component.clk
c1 <= altpll:altpll_component.clk
|ddr_ctrl|clk_gen:clk_gen_inst|altpll:altpll_component
inclk[0] => clk_gen_altpll:auto_generated.inclk[0]
inclk[1] => clk_gen_altpll:auto_generated.inclk[1]
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanclkena => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
phasecounterselect[0] => ~NO_FANOUT~
phasecounterselect[1] => ~NO_FANOUT~
phasecounterselect[2] => ~NO_FANOUT~
phasecounterselect[3] => ~NO_FANOUT~
phaseupdown => ~NO_FANOUT~
phasestep => ~NO_FANOUT~
configupdate => ~NO_FANOUT~
fbmimicbidir <> <GND>
clk[0] <= clk[0].DB_MAX_OUTPUT_PORT_TYPE
clk[1] <= clk[1].DB_MAX_OUTPUT_PORT_TYPE
clk[2] <= clk[2].DB_MAX_OUTPUT_PORT_TYPE
clk[3] <= clk[3].DB_MAX_OUTPUT_PORT_TYPE
clk[4] <= clk[4].DB_MAX_OUTPUT_PORT_TYPE
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= <GND>
phasedone <= <GND>
vcooverrange <= <GND>
vcounderrange <= <GND>
fbout <= <GND>
fref <= <GND>
icdrclk <= <GND>
|ddr_ctrl|clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated
clk[0] <= pll1.CLK
clk[1] <= pll1.CLK1
clk[2] <= pll1.CLK2
clk[3] <= pll1.CLK3
clk[4] <= pll1.CLK4
inclk[0] => pll1.CLK
inclk[1] => pll1.CLK1
|ddr_ctrl|spi_master_2164:u_spi_master_2164
sys_clk => dout[0]~reg0.CLK
sys_clk => dout[1]~reg0.CLK
sys_clk => dout[2]~reg0.CLK
sys_clk => dout[3]~reg0.CLK
sys_clk => dout[4]~reg0.CLK
sys_clk => dout[5]~reg0.CLK
sys_clk => dout[6]~reg0.CLK
sys_clk => dout[7]~reg0.CLK
sys_clk => dout[8]~reg0.CLK
sys_clk => dout[9]~reg0.CLK
sys_clk => dout[10]~reg0.CLK
sys_clk => dout[11]~reg0.CLK
sys_clk => dout[12]~reg0.CLK
sys_clk => dout[13]~reg0.CLK
sys_clk => dout[14]~reg0.CLK
sys_clk => dout[15]~reg0.CLK
sys_clk => done~reg0.CLK
sys_clk => dout_r[0].CLK
sys_clk => dout_r[1].CLK
sys_clk => dout_r[2].CLK
sys_clk => dout_r[3].CLK
sys_clk => dout_r[4].CLK
sys_clk => dout_r[5].CLK
sys_clk => dout_r[6].CLK
sys_clk => dout_r[7].CLK
sys_clk => dout_r[8].CLK
sys_clk => dout_r[9].CLK
sys_clk => dout_r[10].CLK
sys_clk => dout_r[11].CLK
sys_clk => dout_r[12].CLK
sys_clk => dout_r[13].CLK
sys_clk => dout_r[14].CLK
sys_clk => dout_r[15].CLK
sys_clk => mosi~reg0.CLK
sys_clk => cs_n~reg0.CLK
sys_clk => sclk~reg0.CLK
sys_clk => cnt[0]~reg0.CLK
sys_clk => cnt[1]~reg0.CLK
sys_clk => cnt[2]~reg0.CLK
sys_clk => cnt[3]~reg0.CLK
sys_clk => cnt[4]~reg0.CLK
sys_clk => cnt[5]~reg0.CLK
sys_clk => cnt[6]~reg0.CLK
rst_n => mosi~reg0.ACLR
rst_n => cs_n~reg0.PRESET
rst_n => sclk~reg0.ACLR
rst_n => dout[0]~reg0.ACLR
rst_n => dout[1]~reg0.ACLR
rst_n => dout[2]~reg0.ACLR
rst_n => dout[3]~reg0.ACLR
rst_n => dout[4]~reg0.ACLR
rst_n => dout[5]~reg0.ACLR
rst_n => dout[6]~reg0.ACLR
rst_n => dout[7]~reg0.ACLR
rst_n => dout[8]~reg0.ACLR
rst_n => dout[9]~reg0.ACLR
rst_n => dout[10]~reg0.ACLR
rst_n => dout[11]~reg0.ACLR
rst_n => dout[12]~reg0.ACLR
rst_n => dout[13]~reg0.ACLR
rst_n => dout[14]~reg0.ACLR
rst_n => dout[15]~reg0.ACLR
rst_n => done~reg0.ACLR
rst_n => cnt[0]~reg0.ACLR
rst_n => cnt[1]~reg0.ACLR
rst_n => cnt[2]~reg0.ACLR
rst_n => cnt[3]~reg0.ACLR
rst_n => cnt[4]~reg0.ACLR
rst_n => cnt[5]~reg0.ACLR
rst_n => cnt[6]~reg0.ACLR
rst_n => dout_r[15].ENA
rst_n => dout_r[14].ENA
rst_n => dout_r[13].ENA
rst_n => dout_r[12].ENA
rst_n => dout_r[11].ENA
rst_n => dout_r[10].ENA
rst_n => dout_r[9].ENA
rst_n => dout_r[8].ENA
rst_n => dout_r[7].ENA
rst_n => dout_r[6].ENA
rst_n => dout_r[5].ENA
rst_n => dout_r[4].ENA
rst_n => dout_r[3].ENA
rst_n => dout_r[2].ENA
rst_n => dout_r[1].ENA
rst_n => dout_r[0].ENA
din[0] => Selector0.IN33
din[1] => Selector0.IN32
din[2] => Selector0.IN31
din[3] => Selector0.IN30
din[4] => Selector0.IN29
din[5] => Selector0.IN28
din[6] => Selector0.IN27
din[7] => Selector0.IN26
din[8] => Selector0.IN25
din[9] => Selector0.IN24
din[10] => Selector0.IN23
din[11] => Selector0.IN22
din[12] => Selector0.IN21
din[13] => Selector0.IN20
din[14] => Selector0.IN19
din[15] => Selector0.IN18
start => cnt.OUTPUTSELECT
start => cnt.OUTPUTSELECT
start => cnt.OUTPUTSELECT
start => cnt.OUTPUTSELECT
start => cnt.OUTPUTSELECT
start => cnt.OUTPUTSELECT
start => cnt.OUTPUTSELECT
dout[0] <= dout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= dout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= dout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= dout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= dout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= dout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= dout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= dout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[8] <= dout[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[9] <= dout[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[10] <= dout[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[11] <= dout[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[12] <= dout[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[13] <= dout[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[14] <= dout[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[15] <= dout[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
done <= done~reg0.DB_MAX_OUTPUT_PORT_TYPE
sclk <= sclk~reg0.DB_MAX_OUTPUT_PORT_TYPE
cs_n <= cs_n~reg0.DB_MAX_OUTPUT_PORT_TYPE
mosi <= mosi~reg0.DB_MAX_OUTPUT_PORT_TYPE
miso => dout_r.DATAB
cnt[0] <= cnt[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[1] <= cnt[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[2] <= cnt[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[3] <= cnt[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[4] <= cnt[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[5] <= cnt[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[6] <= cnt[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|ddr_ctrl|spi_master_esp32:tranfer
clk => done~reg0.CLK
clk => shift_reg[0].CLK
clk => shift_reg[1].CLK
clk => shift_reg[2].CLK
clk => shift_reg[3].CLK
clk => shift_reg[4].CLK
clk => shift_reg[5].CLK
clk => shift_reg[6].CLK
clk => shift_reg[7].CLK
clk => shift_reg[8].CLK
clk => shift_reg[9].CLK
clk => shift_reg[10].CLK
clk => shift_reg[11].CLK
clk => shift_reg[12].CLK
clk => shift_reg[13].CLK
clk => shift_reg[14].CLK
clk => shift_reg[15].CLK
clk => bit_cnt[0].CLK
clk => bit_cnt[1].CLK
clk => bit_cnt[2].CLK
clk => bit_cnt[3].CLK
clk => sclk_reg.CLK
clk => cs~reg0.CLK
clk => state~4.DATAIN
rst_n => done~reg0.ACLR
rst_n => shift_reg[0].ACLR
rst_n => shift_reg[1].ACLR
rst_n => shift_reg[2].ACLR
rst_n => shift_reg[3].ACLR
rst_n => shift_reg[4].ACLR
rst_n => shift_reg[5].ACLR
rst_n => shift_reg[6].ACLR
rst_n => shift_reg[7].ACLR
rst_n => shift_reg[8].ACLR
rst_n => shift_reg[9].ACLR
rst_n => shift_reg[10].ACLR
rst_n => shift_reg[11].ACLR
rst_n => shift_reg[12].ACLR
rst_n => shift_reg[13].ACLR
rst_n => shift_reg[14].ACLR
rst_n => shift_reg[15].ACLR
rst_n => bit_cnt[0].ACLR
rst_n => bit_cnt[1].ACLR
rst_n => bit_cnt[2].ACLR
rst_n => bit_cnt[3].ACLR
rst_n => sclk_reg.ACLR
rst_n => cs~reg0.PRESET
rst_n => state~6.DATAIN
start => state.OUTPUTSELECT
start => state.OUTPUTSELECT
start => state.OUTPUTSELECT
start => done~reg0.ENA
start => cs~reg0.ENA
start => sclk_reg.ENA
start => bit_cnt[3].ENA
start => bit_cnt[2].ENA
start => bit_cnt[1].ENA
start => bit_cnt[0].ENA
start => shift_reg[15].ENA
start => shift_reg[14].ENA
start => shift_reg[13].ENA
start => shift_reg[12].ENA
start => shift_reg[11].ENA
start => shift_reg[10].ENA
start => shift_reg[9].ENA
start => shift_reg[8].ENA
start => shift_reg[7].ENA
start => shift_reg[6].ENA
start => shift_reg[5].ENA
start => shift_reg[4].ENA
start => shift_reg[3].ENA
start => shift_reg[2].ENA
start => shift_reg[1].ENA
start => shift_reg[0].ENA
din[0] => Selector18.IN1
din[1] => Selector17.IN1
din[2] => Selector16.IN1
din[3] => Selector15.IN1
din[4] => Selector14.IN1
din[5] => Selector13.IN1
din[6] => Selector12.IN1
din[7] => Selector11.IN1
din[8] => Selector10.IN1
din[9] => Selector9.IN1
din[10] => Selector8.IN1
din[11] => Selector7.IN1
din[12] => Selector6.IN1
din[13] => Selector5.IN1
din[14] => Selector4.IN1
din[15] => Selector3.IN1
done <= done~reg0.DB_MAX_OUTPUT_PORT_TYPE
sclk <= sclk_reg.DB_MAX_OUTPUT_PORT_TYPE
mosi <= shift_reg[15].DB_MAX_OUTPUT_PORT_TYPE
cs <= cs~reg0.DB_MAX_OUTPUT_PORT_TYPE
|ddr_ctrl|uart_tx:u_uart_pc
clk => tx_bit_counter[0].CLK
clk => tx_bit_counter[1].CLK
clk => tx_bit_counter[2].CLK
clk => tx_bit_counter[3].CLK
clk => data_to_send[0].CLK
clk => data_to_send[1].CLK
clk => data_to_send[2].CLK
clk => data_to_send[3].CLK
clk => data_to_send[4].CLK
clk => data_to_send[5].CLK
clk => data_to_send[6].CLK
clk => data_to_send[7].CLK
clk => tx_shift_reg[0].CLK
clk => tx_shift_reg[1].CLK
clk => tx_shift_reg[2].CLK
clk => tx_shift_reg[3].CLK
clk => tx_shift_reg[4].CLK
clk => tx_shift_reg[5].CLK
clk => tx_shift_reg[6].CLK
clk => tx_shift_reg[7].CLK
clk => tx_shift_reg[8].CLK
clk => tx_shift_reg[9].CLK
clk => tx_done~reg0.CLK
clk => baud_counter[0].CLK
clk => baud_counter[1].CLK
clk => baud_counter[2].CLK
clk => baud_counter[3].CLK
clk => baud_counter[4].CLK
clk => baud_counter[5].CLK
clk => baud_counter[6].CLK
clk => baud_counter[7].CLK
clk => baud_counter[8].CLK
clk => baud_counter[9].CLK
clk => baud_counter[10].CLK
clk => baud_counter[11].CLK
clk => baud_counter[12].CLK
clk => baud_counter[13].CLK
clk => baud_counter[14].CLK
clk => baud_counter[15].CLK
clk => byte_select~2.DATAIN
clk => tx_state~3.DATAIN
rst => tx_shift_reg[0].PRESET
rst => tx_shift_reg[1].PRESET
rst => tx_shift_reg[2].PRESET
rst => tx_shift_reg[3].PRESET
rst => tx_shift_reg[4].PRESET
rst => tx_shift_reg[5].PRESET
rst => tx_shift_reg[6].PRESET
rst => tx_shift_reg[7].PRESET
rst => tx_shift_reg[8].PRESET
rst => tx_shift_reg[9].PRESET
rst => tx_done~reg0.ACLR
rst => baud_counter[0].ACLR
rst => baud_counter[1].ACLR
rst => baud_counter[2].ACLR
rst => baud_counter[3].ACLR
rst => baud_counter[4].ACLR
rst => baud_counter[5].ACLR
rst => baud_counter[6].ACLR
rst => baud_counter[7].ACLR
rst => baud_counter[8].ACLR
rst => baud_counter[9].ACLR
rst => baud_counter[10].ACLR
rst => baud_counter[11].ACLR
rst => baud_counter[12].ACLR
rst => baud_counter[13].ACLR
rst => baud_counter[14].ACLR
rst => baud_counter[15].ACLR
rst => byte_select~4.DATAIN
rst => tx_state~5.DATAIN
rst => tx_bit_counter[0].ENA
rst => data_to_send[7].ENA
rst => data_to_send[6].ENA
rst => data_to_send[5].ENA
rst => data_to_send[4].ENA
rst => data_to_send[3].ENA
rst => data_to_send[2].ENA
rst => data_to_send[1].ENA
rst => data_to_send[0].ENA
rst => tx_bit_counter[3].ENA
rst => tx_bit_counter[2].ENA
rst => tx_bit_counter[1].ENA
tx_start => data_to_send.OUTPUTSELECT
tx_start => data_to_send.OUTPUTSELECT
tx_start => data_to_send.OUTPUTSELECT
tx_start => data_to_send.OUTPUTSELECT
tx_start => data_to_send.OUTPUTSELECT
tx_start => data_to_send.OUTPUTSELECT
tx_start => data_to_send.OUTPUTSELECT
tx_start => data_to_send.OUTPUTSELECT
tx_start => tx_shift_reg.OUTPUTSELECT
tx_start => tx_shift_reg.OUTPUTSELECT
tx_start => tx_shift_reg.OUTPUTSELECT
tx_start => tx_shift_reg.OUTPUTSELECT
tx_start => tx_shift_reg.OUTPUTSELECT
tx_start => tx_shift_reg.OUTPUTSELECT
tx_start => tx_shift_reg.OUTPUTSELECT
tx_start => tx_shift_reg.OUTPUTSELECT
tx_start => tx_shift_reg.OUTPUTSELECT
tx_start => tx_shift_reg.OUTPUTSELECT
tx_start => tx_state.OUTPUTSELECT
tx_start => tx_state.OUTPUTSELECT
tx_start => tx_done.OUTPUTSELECT
tx_data[0] => data_to_send.DATAA
tx_data[1] => data_to_send.DATAA
tx_data[2] => data_to_send.DATAA
tx_data[3] => data_to_send.DATAA
tx_data[4] => data_to_send.DATAA
tx_data[5] => data_to_send.DATAA
tx_data[6] => data_to_send.DATAA
tx_data[7] => data_to_send.DATAA
tx_data[8] => data_to_send.DATAB
tx_data[9] => data_to_send.DATAB
tx_data[10] => data_to_send.DATAB
tx_data[11] => data_to_send.DATAB
tx_data[12] => data_to_send.DATAB
tx_data[13] => data_to_send.DATAB
tx_data[14] => data_to_send.DATAB
tx_data[15] => data_to_send.DATAB
tx <= tx_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE
tx_done <= tx_done~reg0.DB_MAX_OUTPUT_PORT_TYPE

BIN
puart2/db/intan_m10.hif Normal file
View File

Binary file not shown.

98
puart2/db/intan_m10.lpc.html Normal file
View File

@ -0,0 +1,98 @@
<TABLE>
<TR bgcolor="#C0C0C0">
<TH>Hierarchy</TH>
<TH>Input</TH>
<TH>Constant Input</TH>
<TH>Unused Input</TH>
<TH>Floating Input</TH>
<TH>Output</TH>
<TH>Constant Output</TH>
<TH>Unused Output</TH>
<TH>Floating Output</TH>
<TH>Bidir</TH>
<TH>Constant Bidir</TH>
<TH>Unused Bidir</TH>
<TH>Input only Bidir</TH>
<TH>Output only Bidir</TH>
</TR>
<TR >
<TD >u_uart_pc</TD>
<TD >19</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >tranfer</TD>
<TD >19</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >4</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_spi_master_2164</TD>
<TD >20</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >20</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >clk_gen_inst|altpll_component|auto_generated</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >5</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >clk_gen_inst</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
</TABLE>

BIN
puart2/db/intan_m10.lpc.rdb Normal file
View File

Binary file not shown.

11
puart2/db/intan_m10.lpc.txt Normal file
View File

@ -0,0 +1,11 @@
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+----------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+----------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; u_uart_pc ; 19 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; tranfer ; 19 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; u_spi_master_2164 ; 20 ; 0 ; 0 ; 0 ; 20 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; clk_gen_inst|altpll_component|auto_generated ; 2 ; 0 ; 0 ; 0 ; 5 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; clk_gen_inst ; 1 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+----------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

BIN
puart2/db/intan_m10.map.ammdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.map.bpm Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.map.cdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.map.hdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.map.kpt Normal file
View File

Binary file not shown.

1
puart2/db/intan_m10.map.logdb Normal file
View File

@ -0,0 +1 @@
v1

38
puart2/db/intan_m10.map.qmsg Normal file
View File

File diff suppressed because one or more lines are too long

BIN
puart2/db/intan_m10.map.rdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.map_bb.cdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.map_bb.hdb Normal file
View File

Binary file not shown.

1
puart2/db/intan_m10.map_bb.logdb Normal file
View File

@ -0,0 +1 @@
v1

4
puart2/db/intan_m10.npp.qmsg Normal file
View File

@ -0,0 +1,4 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1714359168898 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus Prime " "Running Quartus Prime Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1714359168903 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 29 10:52:48 2024 " "Processing started: Mon Apr 29 10:52:48 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1714359168903 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1714359168903 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_npp intan_m10 -c intan_m10 --netlist_type=sgate " "Command: quartus_npp intan_m10 -c intan_m10 --netlist_type=sgate" { } { } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1714359168904 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 0 s Quartus Prime " "Quartus Prime Netlist Viewers Preprocess was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4538 " "Peak virtual memory: 4538 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1714359169080 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 29 10:52:49 2024 " "Processing ended: Mon Apr 29 10:52:49 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1714359169080 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1714359169080 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1714359169080 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1714359169080 ""}

19
puart2/db/intan_m10.pow.qmsg Normal file
View File

@ -0,0 +1,19 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1765447235218 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Power Analyzer Quartus Prime " "Running Quartus Prime Power Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1765447235229 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 11 18:00:35 2025 " "Processing started: Thu Dec 11 18:00:35 2025" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1765447235229 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Power Analyzer" 0 -1 1765447235229 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_pow --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10 " "Command: quartus_pow --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10" { } { } 0 0 "Command: %1!s!" 0 0 "Power Analyzer" 0 -1 1765447235229 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Power Analyzer" 0 -1 1765447235534 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Power Analyzer" 0 -1 1765447235534 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "intan_m10.sdc " "Synopsys Design Constraints File file not found: 'intan_m10.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Power Analyzer" 0 -1 1765447235796 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "sys_clk " "Node: sys_clk was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi_master_2164:u_spi_master_2164\|cnt\[1\] sys_clk " "Register spi_master_2164:u_spi_master_2164\|cnt\[1\] is being clocked by sys_clk" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1765447235797 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Power Analyzer" 0 -1 1765447235797 "|ddr_ctrl|sys_clk"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi_master_2164:u_spi_master_2164\|cs_n " "Node: spi_master_2164:u_spi_master_2164\|cs_n was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register state\[2\] spi_master_2164:u_spi_master_2164\|cs_n " "Register state\[2\] is being clocked by spi_master_2164:u_spi_master_2164\|cs_n" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1765447235797 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Power Analyzer" 0 -1 1765447235797 "|ddr_ctrl|spi_master_2164:u_spi_master_2164|cs_n"}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Power Analyzer" 0 -1 1765447235798 ""}
{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Node: clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 83.333 " "Node: clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 83.333" { } { } 0 332056 "%1!s!" 0 0 "Design Software" 0 -1 1765447235799 ""} } { } 0 332056 "%1!s!" 0 0 "Power Analyzer" 0 -1 1765447235799 ""}
{ "Info" "IPVA_PVA_START_CALCULATION" "" "Starting Vectorless Power Activity Estimation" { } { } 0 223000 "Starting Vectorless Power Activity Estimation" 0 0 "Power Analyzer" 0 -1 1765447235803 ""}
{ "Warning" "WPUTIL_PUTIL_NO_CLK_DOMAINS_FOUND" "" "Relative toggle rates could not be calculated because no clock domain could be identified for some nodes" { } { } 0 222013 "Relative toggle rates could not be calculated because no clock domain could be identified for some nodes" 0 0 "Power Analyzer" 0 -1 1765447235804 ""}
{ "Info" "IPVA_PVA_END_CALCULATION" "" "Completed Vectorless Power Activity Estimation" { } { } 0 223001 "Completed Vectorless Power Activity Estimation" 0 0 "Power Analyzer" 0 -1 1765447235806 ""}
{ "Info" "IPATFAM_USING_ADVANCED_IO_POWER" "" "Using Advanced I/O Power to simulate I/O buffers with the specified board trace model" { } { } 0 218000 "Using Advanced I/O Power to simulate I/O buffers with the specified board trace model" 0 0 "Power Analyzer" 0 -1 1765447235961 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Power Analyzer" 0 -1 1765447235996 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Power Analyzer" 0 -1 1765447236365 ""}
{ "Info" "IPAN_AVG_TOGGLE_RATE_PER_DESIGN" "0.000 millions of transitions / sec " "Average toggle rate for this design is 0.000 millions of transitions / sec" { } { } 0 215049 "Average toggle rate for this design is %1!s!" 0 0 "Power Analyzer" 0 -1 1765447236695 ""}
{ "Info" "IPAN_PAN_TOTAL_POWER_ESTIMATION" "149.66 mW " "Total thermal power estimate for the design is 149.66 mW" { } { { "e:/quartuslite/quartus/bin64/Report_Window_01.qrpt" "" { Report "e:/quartuslite/quartus/bin64/Report_Window_01.qrpt" "Compiler" "" "" "" "" { } "PowerPlay Power Analyzer Summary" } } } 0 215031 "Total thermal power estimate for the design is %1!s!" 0 0 "Power Analyzer" 0 -1 1765447236811 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Power Analyzer 0 s 7 s Quartus Prime " "Quartus Prime Power Analyzer was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4812 " "Peak virtual memory: 4812 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1765447237015 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 11 18:00:37 2025 " "Processing ended: Thu Dec 11 18:00:37 2025" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1765447237015 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1765447237015 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1765447237015 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Power Analyzer" 0 -1 1765447237015 ""}

BIN
puart2/db/intan_m10.pplq.rdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.pre_map.cdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.pre_map.hdb Normal file
View File

Binary file not shown.

1
puart2/db/intan_m10.qns Normal file
View File

@ -0,0 +1 @@
intan_m10/done

30
puart2/db/intan_m10.qpf Normal file
View File

@ -0,0 +1,30 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
# Date created = 09:52:33 September 21, 2024
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "17.1"
DATE = "09:52:33 September 21, 2024"
# Revisions
PROJECT_REVISION = "intan_m10"

BIN
puart2/db/intan_m10.root_partition.map.reg_db.cdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.routing.rdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.rtlv.hdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.rtlv_sg.cdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.rtlv_sg_swap.cdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.sgate.nvd Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.sgate_sm.nvd Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.sgate_sm_bdd.nvd Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.sld_design_entry.sci Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.sld_design_entry_dsc.sci Normal file
View File

Binary file not shown.

1
puart2/db/intan_m10.smart_action.txt Normal file
View File

@ -0,0 +1 @@
DONE

23
puart2/db/intan_m10.smp_dump.txt Normal file
View File

@ -0,0 +1,23 @@
State Machine - |ddr_ctrl|state_top
Name state_top.SEND_uart state_top.SEND2 state_top.SEND1 state_top.IDLE
state_top.IDLE 0 0 0 0
state_top.SEND1 0 0 1 1
state_top.SEND2 0 1 0 1
state_top.SEND_uart 1 0 0 1
State Machine - |ddr_ctrl|uart_tx:u_uart_pc|byte_select
Name byte_select.01
byte_select.00 0
byte_select.01 1
State Machine - |ddr_ctrl|uart_tx:u_uart_pc|tx_state
Name tx_state.0001
tx_state.0000 0
tx_state.0001 1
State Machine - |ddr_ctrl|spi_master_esp32:tranfer|state
Name state.IDLE state.DONE state.TRANSFER
state.IDLE 0 0 0
state.TRANSFER 1 0 1
state.DONE 1 1 0

47
puart2/db/intan_m10.sta.qmsg Normal file
View File

@ -0,0 +1,47 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1765447238388 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1765447238402 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 11 18:00:37 2025 " "Processing started: Thu Dec 11 18:00:37 2025" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1765447238402 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447238402 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta intan_m10 -c intan_m10 " "Command: quartus_sta intan_m10 -c intan_m10" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447238403 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #3" { } { } 0 0 "qsta_default_script.tcl version: #3" 0 0 "TimeQuest Timing Analyzer" 0 0 1765447238569 ""}
{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "4 " "Parallel compilation is enabled and will use up to 4 processors" { } { } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447238960 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447238999 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447238999 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "intan_m10.sdc " "Synopsys Design Constraints File file not found: 'intan_m10.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447239163 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "generated clocks \"derive_pll_clocks -create_base_clocks\" " "No user constrained generated clocks found in the design. Calling \"derive_pll_clocks -create_base_clocks\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447239163 ""}
{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_clock -period 83.333 -waveform \{0.000 41.666\} -name sys_clk sys_clk " "create_clock -period 83.333 -waveform \{0.000 41.666\} -name sys_clk sys_clk" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1765447239165 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 625 -multiply_by 6 -duty_cycle 50.00 -name \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 625 -multiply_by 6 -duty_cycle 50.00 -name \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1765447239165 ""} } { } 0 332110 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447239165 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447239165 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name spi_master_2164:u_spi_master_2164\|cs_n spi_master_2164:u_spi_master_2164\|cs_n " "create_clock -period 1.000 -name spi_master_2164:u_spi_master_2164\|cs_n spi_master_2164:u_spi_master_2164\|cs_n" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1765447239165 ""} } { } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447239165 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447239168 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447239168 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1765447239169 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1765447239178 ""}
{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "TimeQuest Timing Analyzer" 0 0 1765447239184 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447239186 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -6.744 " "Worst-case setup slack is -6.744" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447239196 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447239196 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.744 -6.744 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -6.744 -6.744 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447239196 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.642 -7.912 spi_master_2164:u_spi_master_2164\|cs_n " " -0.642 -7.912 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447239196 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447239196 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.362 " "Worst-case hold slack is 0.362" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447239203 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447239203 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.362 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.362 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447239203 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.363 0.000 spi_master_2164:u_spi_master_2164\|cs_n " " 0.363 0.000 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447239203 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447239203 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447239216 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447239218 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.487 " "Worst-case minimum pulse width slack is -1.487" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447239265 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447239265 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.487 -46.097 spi_master_2164:u_spi_master_2164\|cs_n " " -1.487 -46.097 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447239265 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 41.554 0.000 sys_clk " " 41.554 0.000 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447239265 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4339.989 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4339.989 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447239265 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447239265 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 1 synchronizer chains. " "Report Metastability: Found 1 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447239274 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 1 " "Number of Synchronizer Chains Found: 1" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447239274 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447239274 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447239274 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 17358.585 ns " "Worst Case Available Settling Time: 17358.585 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447239274 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447239274 ""} } { } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447239274 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1765447239279 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447239308 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447239885 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447240002 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447240008 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -6.215 " "Worst-case setup slack is -6.215" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240020 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240020 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.215 -6.215 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -6.215 -6.215 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240020 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.556 -5.863 spi_master_2164:u_spi_master_2164\|cs_n " " -0.556 -5.863 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240020 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447240020 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.324 " "Worst-case hold slack is 0.324" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240025 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240025 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.324 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.324 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240025 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.325 0.000 spi_master_2164:u_spi_master_2164\|cs_n " " 0.325 0.000 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240025 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447240025 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447240038 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447240046 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.487 " "Worst-case minimum pulse width slack is -1.487" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240054 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240054 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.487 -46.097 spi_master_2164:u_spi_master_2164\|cs_n " " -1.487 -46.097 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240054 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 41.555 0.000 sys_clk " " 41.555 0.000 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240054 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4340.000 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4340.000 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240054 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447240054 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 1 synchronizer chains. " "Report Metastability: Found 1 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447240065 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 1 " "Number of Synchronizer Chains Found: 1" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447240065 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447240065 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447240065 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 17358.726 ns " "Worst Case Available Settling Time: 17358.726 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447240065 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447240065 ""} } { } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447240065 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1765447240069 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447240261 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447240262 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.312 " "Worst-case setup slack is -2.312" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240264 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240264 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.312 -2.312 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -2.312 -2.312 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240264 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.304 0.000 spi_master_2164:u_spi_master_2164\|cs_n " " 0.304 0.000 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240264 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447240264 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.151 " "Worst-case hold slack is 0.151" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240276 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240276 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.151 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.151 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240276 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.151 0.000 spi_master_2164:u_spi_master_2164\|cs_n " " 0.151 0.000 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240276 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447240276 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447240278 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447240297 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.000 " "Worst-case minimum pulse width slack is -1.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240299 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240299 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.000 -31.000 spi_master_2164:u_spi_master_2164\|cs_n " " -1.000 -31.000 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240299 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 41.180 0.000 sys_clk " " 41.180 0.000 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240299 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4340.041 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4340.041 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240299 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447240299 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 1 synchronizer chains. " "Report Metastability: Found 1 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447240306 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 1 " "Number of Synchronizer Chains Found: 1" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447240306 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447240306 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447240306 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 17359.966 ns " "Worst Case Available Settling Time: 17359.966 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447240306 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447240306 ""} } { } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447240306 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447241137 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447241138 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4784 " "Peak virtual memory: 4784 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1765447241203 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 11 18:00:41 2025 " "Processing ended: Thu Dec 11 18:00:41 2025" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1765447241203 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1765447241203 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1765447241203 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447241203 ""}

BIN
puart2/db/intan_m10.sta.rdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.sta_cmp.8_slow_1200mv_85c.tdb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.tis_db_list.ddb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.tiscmp.fast_1200mv_0c.ddb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.tiscmp.fastest_slow_1200mv_0c.ddb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.tiscmp.fastest_slow_1200mv_85c.ddb Normal file
View File

Binary file not shown.

BIN
puart2/db/intan_m10.tiscmp.slow_1200mv_0c.ddb Normal file
View File

Binary file not shown.

Some files were not shown because too many files have changed in this diff Show More