commit 58bb0da74bff26416d612acbef8cae2368178f9c Author: dsfsdf <2319834949@qq.com> Date: Thu Dec 11 18:35:48 2025 +0800 update diff --git a/puart2/.qsys_edit/filters.xml b/puart2/.qsys_edit/filters.xml new file mode 100644 index 0000000..21d8ce6 --- /dev/null +++ b/puart2/.qsys_edit/filters.xml @@ -0,0 +1,2 @@ + + diff --git a/puart2/.qsys_edit/preferences.xml b/puart2/.qsys_edit/preferences.xml new file mode 100644 index 0000000..c5b7680 --- /dev/null +++ b/puart2/.qsys_edit/preferences.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/puart2/__intan_m10.auto.qarlog b/puart2/__intan_m10.auto.qarlog new file mode 100644 index 0000000..732c22e --- /dev/null +++ b/puart2/__intan_m10.auto.qarlog @@ -0,0 +1,52 @@ +Quartus Prime Archive log -- E:/FPGA/SPItransfer/20240726/__intan_m10.auto.qarlog + +Archive: E:/FPGA/SPItransfer/20240726/__intan_m10.auto.qar +Date: Sat Sep 21 09:52:33 2024 +Quartus Prime 17.1.0 Build 590 10/25/2017 SJ Lite Edition + + =========== Files Selected: =========== +E:/FPGA/SPItransfer/20240726/clk_gen.qip +E:/FPGA/SPItransfer/20240726/clk_gen.v +E:/FPGA/SPItransfer/20240726/db/clk_gen_altpll.v +E:/FPGA/SPItransfer/20240726/db/intan_m10.cbx.xml +E:/FPGA/SPItransfer/20240726/db/intan_m10.qpf +E:/FPGA/SPItransfer/20240726/ddr_ctrl.v +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.asm.rpt +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.cdf +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.done +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.eda.rpt +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.fit.rpt +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.fit.smsg +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.fit.summary +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.flow.rpt +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.jdi +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.map.rpt +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.map.smsg +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.map.summary +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.pin +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.pof +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.pow.rpt +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.pow.summary +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.sld +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.sof +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.sta.rpt +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.sta.summary +E:/FPGA/SPItransfer/20240726/spi_master_2164.v +E:/FPGA/SPItransfer/20240726/spi_master_esp32.v +clk_gen.ppf +clk_gen_bb.v +clk_gen_inst.v +clkgen.ppf +clkgen.qip +clkgen.v +clkgen_bb.v +clkgen_inst.v +ddr_ctrl_tb.v +e:/quartuslite/quartus/bin64/assignment_defaults.qdf +intan_m10.qsf +intan_m10.v +intan_m10_assignment_defaults.qdf + ======= Total: 41 files to archive ======= + + ================ Status: =============== +All files archived successfully. diff --git a/puart2/clk_gen.ppf b/puart2/clk_gen.ppf new file mode 100644 index 0000000..36a1b80 --- /dev/null +++ b/puart2/clk_gen.ppf @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/puart2/clk_gen.qip b/puart2/clk_gen.qip new file mode 100644 index 0000000..733a641 --- /dev/null +++ b/puart2/clk_gen.qip @@ -0,0 +1,7 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "17.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "clk_gen.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clk_gen_inst.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clk_gen_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clk_gen.ppf"] diff --git a/puart2/clk_gen.v b/puart2/clk_gen.v new file mode 100644 index 0000000..77d5fe8 --- /dev/null +++ b/puart2/clk_gen.v @@ -0,0 +1,332 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: clk_gen.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 17.1.0 Build 590 10/25/2017 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2017 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module clk_gen ( + inclk0, + c0, + c1); + + input inclk0; + output c0; + output c1; + + wire [0:0] sub_wire2 = 1'h0; + wire [4:0] sub_wire3; + wire sub_wire0 = inclk0; + wire [1:0] sub_wire1 = {sub_wire2, sub_wire0}; + wire [1:1] sub_wire5 = sub_wire3[1:1]; + wire [0:0] sub_wire4 = sub_wire3[0:0]; + wire c0 = sub_wire4; + wire c1 = sub_wire5; + + altpll altpll_component ( + .inclk (sub_wire1), + .clk (sub_wire3), + .activeclock (), + .areset (1'b0), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .locked (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 625, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 6, + altpll_component.clk0_phase_shift = "0", + altpll_component.clk1_divide_by = 625, + altpll_component.clk1_duty_cycle = 50, + altpll_component.clk1_multiply_by = 12, + altpll_component.clk1_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 83333, + altpll_component.intended_device_family = "MAX 10", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=clk_gen", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_UNUSED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_UNUSED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_USED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "104" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "52" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.115200" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "0.230400" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "12.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.11520000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "0.23040000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clk_gen.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK2 STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK3 STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK4 STRING "0" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "625" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "6" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "625" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "12" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "83333" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/puart2/clk_gen_bb.v b/puart2/clk_gen_bb.v new file mode 100644 index 0000000..dc97bcd --- /dev/null +++ b/puart2/clk_gen_bb.v @@ -0,0 +1,219 @@ +// megafunction wizard: %ALTPLL%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: clk_gen.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 17.1.0 Build 590 10/25/2017 SJ Lite Edition +// ************************************************************ + +//Copyright (C) 2017 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + +module clk_gen ( + inclk0, + c0, + c1); + + input inclk0; + output c0; + output c1; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "104" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "52" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.115200" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "0.230400" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "12.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.11520000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "0.23040000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clk_gen.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK2 STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK3 STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK4 STRING "0" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "625" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "6" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "625" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "12" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "83333" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/puart2/clk_gen_inst.v b/puart2/clk_gen_inst.v new file mode 100644 index 0000000..29c749f --- /dev/null +++ b/puart2/clk_gen_inst.v @@ -0,0 +1,5 @@ +clk_gen clk_gen_inst ( + .inclk0 ( inclk0_sig ), + .c0 ( c0_sig ), + .c1 ( c1_sig ) + ); diff --git a/puart2/clkgen.ppf b/puart2/clkgen.ppf new file mode 100644 index 0000000..69051ed --- /dev/null +++ b/puart2/clkgen.ppf @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/puart2/clkgen.qip b/puart2/clkgen.qip new file mode 100644 index 0000000..15da83f --- /dev/null +++ b/puart2/clkgen.qip @@ -0,0 +1,7 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "17.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "clkgen.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clkgen_inst.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clkgen_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clkgen.ppf"] diff --git a/puart2/clkgen.v b/puart2/clkgen.v new file mode 100644 index 0000000..997fbeb --- /dev/null +++ b/puart2/clkgen.v @@ -0,0 +1,305 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: clkgen.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 17.1.0 Build 590 10/25/2017 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2017 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module clkgen ( + inclk0, + c0); + + input inclk0; + output c0; + + wire [0:0] sub_wire2 = 1'h0; + wire [4:0] sub_wire3; + wire sub_wire0 = inclk0; + wire [1:0] sub_wire1 = {sub_wire2, sub_wire0}; + wire [0:0] sub_wire4 = sub_wire3[0:0]; + wire c0 = sub_wire4; + + altpll altpll_component ( + .inclk (sub_wire1), + .clk (sub_wire3), + .activeclock (), + .areset (1'b0), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .locked (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 6, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 1, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 83333, + altpll_component.intended_device_family = "MAX 10", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=clkgen", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_UNUSED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_UNUSED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "6" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "2.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "12.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clkgen.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK2 STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK3 STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK4 STRING "0" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "6" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "83333" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/puart2/clkgen_bb.v b/puart2/clkgen_bb.v new file mode 100644 index 0000000..ceb2bf8 --- /dev/null +++ b/puart2/clkgen_bb.v @@ -0,0 +1,198 @@ +// megafunction wizard: %ALTPLL%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: clkgen.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 17.1.0 Build 590 10/25/2017 SJ Lite Edition +// ************************************************************ + +//Copyright (C) 2017 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + +module clkgen ( + inclk0, + c0); + + input inclk0; + output c0; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "6" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "2.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "12.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clkgen.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK2 STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK3 STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK4 STRING "0" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "6" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "83333" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/puart2/clkgen_inst.v b/puart2/clkgen_inst.v new file mode 100644 index 0000000..75f6166 --- /dev/null +++ b/puart2/clkgen_inst.v @@ -0,0 +1,4 @@ +clkgen clkgen_inst ( + .inclk0 ( inclk0_sig ), + .c0 ( c0_sig ) + ); diff --git a/puart2/db/.cmp.kpt b/puart2/db/.cmp.kpt new file mode 100644 index 0000000..587b886 Binary files /dev/null and b/puart2/db/.cmp.kpt differ diff --git a/puart2/db/clk_gen_altpll.v b/puart2/db/clk_gen_altpll.v new file mode 100644 index 0000000..f7c638d --- /dev/null +++ b/puart2/db/clk_gen_altpll.v @@ -0,0 +1,96 @@ +//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=625 clk0_duty_cycle=50 clk0_multiply_by=6 clk0_phase_shift="0" clk1_divide_by=625 clk1_duty_cycle=50 clk1_multiply_by=12 clk1_phase_shift="0" compensate_clock="CLK0" device_family="MAX 10" inclk0_input_frequency=83333 intended_device_family="MAX 10" lpm_hint="CBX_MODULE_PREFIX=clk_gen" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 clk inclk CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +//VERSION_BEGIN 17.1 cbx_altclkbuf 2017:10:25:18:06:52:SJ cbx_altiobuf_bidir 2017:10:25:18:06:52:SJ cbx_altiobuf_in 2017:10:25:18:06:52:SJ cbx_altiobuf_out 2017:10:25:18:06:52:SJ cbx_altpll 2017:10:25:18:06:53:SJ cbx_cycloneii 2017:10:25:18:06:53:SJ cbx_lpm_add_sub 2017:10:25:18:06:53:SJ cbx_lpm_compare 2017:10:25:18:06:53:SJ cbx_lpm_counter 2017:10:25:18:06:53:SJ cbx_lpm_decode 2017:10:25:18:06:53:SJ cbx_lpm_mux 2017:10:25:18:06:53:SJ cbx_mgl 2017:10:25:18:08:29:SJ cbx_nadder 2017:10:25:18:06:53:SJ cbx_stratix 2017:10:25:18:06:53:SJ cbx_stratixii 2017:10:25:18:06:53:SJ cbx_stratixiii 2017:10:25:18:06:53:SJ cbx_stratixv 2017:10:25:18:06:53:SJ cbx_util_mgl 2017:10:25:18:06:53:SJ VERSION_END +//CBXI_INSTANCE_NAME="ddr_ctrl_clk_gen_clk_gen_inst_altpll_altpll_component" +// synthesis VERILOG_INPUT_VERSION VERILOG_2001 +// altera message_off 10463 + + + +// Copyright (C) 2017 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details. + + + +//synthesis_resources = fiftyfivenm_pll 1 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module clk_gen_altpll + ( + clk, + inclk) /* synthesis synthesis_clearbox=1 */; + output [4:0] clk; + input [1:0] inclk; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 [1:0] inclk; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [4:0] wire_pll1_clk; + wire wire_pll1_fbout; + + fiftyfivenm_pll pll1 + ( + .activeclock(), + .clk(wire_pll1_clk), + .clkbad(), + .fbin(wire_pll1_fbout), + .fbout(wire_pll1_fbout), + .inclk(inclk), + .locked(), + .phasedone(), + .scandataout(), + .scandone(), + .vcooverrange(), + .vcounderrange() + `ifndef FORMAL_VERIFICATION + // synopsys translate_off + `endif + , + .areset(1'b0), + .clkswitch(1'b0), + .configupdate(1'b0), + .pfdena(1'b1), + .phasecounterselect({3{1'b0}}), + .phasestep(1'b0), + .phaseupdown(1'b0), + .scanclk(1'b0), + .scanclkena(1'b1), + .scandata(1'b0) + `ifndef FORMAL_VERIFICATION + // synopsys translate_on + `endif + ); + defparam + pll1.bandwidth_type = "auto", + pll1.clk0_divide_by = 625, + pll1.clk0_duty_cycle = 50, + pll1.clk0_multiply_by = 6, + pll1.clk0_phase_shift = "0", + pll1.clk1_divide_by = 625, + pll1.clk1_duty_cycle = 50, + pll1.clk1_multiply_by = 12, + pll1.clk1_phase_shift = "0", + pll1.compensate_clock = "clk0", + pll1.inclk0_input_frequency = 83333, + pll1.operation_mode = "normal", + pll1.pll_type = "auto", + pll1.lpm_type = "fiftyfivenm_pll"; + assign + clk = {wire_pll1_clk[4:0]}; +endmodule //clk_gen_altpll +//VALID FILE diff --git a/puart2/db/intan_m10.(0).cnf.cdb b/puart2/db/intan_m10.(0).cnf.cdb new file mode 100644 index 0000000..587fb58 Binary files /dev/null and b/puart2/db/intan_m10.(0).cnf.cdb differ diff --git a/puart2/db/intan_m10.(0).cnf.hdb b/puart2/db/intan_m10.(0).cnf.hdb new file mode 100644 index 0000000..c64f302 Binary files /dev/null and b/puart2/db/intan_m10.(0).cnf.hdb differ diff --git a/puart2/db/intan_m10.(1).cnf.cdb b/puart2/db/intan_m10.(1).cnf.cdb new file mode 100644 index 0000000..69fa70a Binary files /dev/null and b/puart2/db/intan_m10.(1).cnf.cdb differ diff --git a/puart2/db/intan_m10.(1).cnf.hdb b/puart2/db/intan_m10.(1).cnf.hdb new file mode 100644 index 0000000..64c5aac Binary files /dev/null and b/puart2/db/intan_m10.(1).cnf.hdb differ diff --git a/puart2/db/intan_m10.(10).cnf.cdb b/puart2/db/intan_m10.(10).cnf.cdb new file mode 100644 index 0000000..e27aa82 Binary files /dev/null and b/puart2/db/intan_m10.(10).cnf.cdb differ diff --git a/puart2/db/intan_m10.(10).cnf.hdb b/puart2/db/intan_m10.(10).cnf.hdb new file mode 100644 index 0000000..eaf5e2a Binary files /dev/null and b/puart2/db/intan_m10.(10).cnf.hdb differ diff --git a/puart2/db/intan_m10.(2).cnf.cdb b/puart2/db/intan_m10.(2).cnf.cdb new file mode 100644 index 0000000..5fd6674 Binary files /dev/null and b/puart2/db/intan_m10.(2).cnf.cdb differ diff --git a/puart2/db/intan_m10.(2).cnf.hdb b/puart2/db/intan_m10.(2).cnf.hdb new file mode 100644 index 0000000..a64cc2c Binary files /dev/null and b/puart2/db/intan_m10.(2).cnf.hdb differ diff --git a/puart2/db/intan_m10.(3).cnf.cdb b/puart2/db/intan_m10.(3).cnf.cdb new file mode 100644 index 0000000..d058530 Binary files /dev/null and b/puart2/db/intan_m10.(3).cnf.cdb differ diff --git a/puart2/db/intan_m10.(3).cnf.hdb b/puart2/db/intan_m10.(3).cnf.hdb new file mode 100644 index 0000000..2de4bdb Binary files /dev/null and b/puart2/db/intan_m10.(3).cnf.hdb differ diff --git a/puart2/db/intan_m10.(4).cnf.cdb b/puart2/db/intan_m10.(4).cnf.cdb new file mode 100644 index 0000000..47738bb Binary files /dev/null and b/puart2/db/intan_m10.(4).cnf.cdb differ diff --git a/puart2/db/intan_m10.(4).cnf.hdb b/puart2/db/intan_m10.(4).cnf.hdb new file mode 100644 index 0000000..167d036 Binary files /dev/null and b/puart2/db/intan_m10.(4).cnf.hdb differ diff --git a/puart2/db/intan_m10.(5).cnf.cdb b/puart2/db/intan_m10.(5).cnf.cdb new file mode 100644 index 0000000..964dae6 Binary files /dev/null and b/puart2/db/intan_m10.(5).cnf.cdb differ diff --git a/puart2/db/intan_m10.(5).cnf.hdb b/puart2/db/intan_m10.(5).cnf.hdb new file mode 100644 index 0000000..23a883e Binary files /dev/null and b/puart2/db/intan_m10.(5).cnf.hdb differ diff --git a/puart2/db/intan_m10.(6).cnf.cdb b/puart2/db/intan_m10.(6).cnf.cdb new file mode 100644 index 0000000..3c1b2c8 Binary files /dev/null and b/puart2/db/intan_m10.(6).cnf.cdb differ diff --git a/puart2/db/intan_m10.(6).cnf.hdb b/puart2/db/intan_m10.(6).cnf.hdb new file mode 100644 index 0000000..8c6d4a9 Binary files /dev/null and b/puart2/db/intan_m10.(6).cnf.hdb differ diff --git a/puart2/db/intan_m10.(7).cnf.cdb b/puart2/db/intan_m10.(7).cnf.cdb new file mode 100644 index 0000000..f1849ea Binary files /dev/null and b/puart2/db/intan_m10.(7).cnf.cdb differ diff --git a/puart2/db/intan_m10.(7).cnf.hdb b/puart2/db/intan_m10.(7).cnf.hdb new file mode 100644 index 0000000..257ddd1 Binary files /dev/null and b/puart2/db/intan_m10.(7).cnf.hdb differ diff --git a/puart2/db/intan_m10.(8).cnf.cdb b/puart2/db/intan_m10.(8).cnf.cdb new file mode 100644 index 0000000..ed7d8a0 Binary files /dev/null and b/puart2/db/intan_m10.(8).cnf.cdb differ diff --git a/puart2/db/intan_m10.(8).cnf.hdb b/puart2/db/intan_m10.(8).cnf.hdb new file mode 100644 index 0000000..33f0982 Binary files /dev/null and b/puart2/db/intan_m10.(8).cnf.hdb differ diff --git a/puart2/db/intan_m10.(9).cnf.cdb b/puart2/db/intan_m10.(9).cnf.cdb new file mode 100644 index 0000000..9eade72 Binary files /dev/null and b/puart2/db/intan_m10.(9).cnf.cdb differ diff --git a/puart2/db/intan_m10.(9).cnf.hdb b/puart2/db/intan_m10.(9).cnf.hdb new file mode 100644 index 0000000..590e66e Binary files /dev/null and b/puart2/db/intan_m10.(9).cnf.hdb differ diff --git a/puart2/db/intan_m10.ace_cmp.bpm b/puart2/db/intan_m10.ace_cmp.bpm new file mode 100644 index 0000000..c455d1c Binary files /dev/null and b/puart2/db/intan_m10.ace_cmp.bpm differ diff --git a/puart2/db/intan_m10.ace_cmp.cdb b/puart2/db/intan_m10.ace_cmp.cdb new file mode 100644 index 0000000..a97bee7 Binary files /dev/null and b/puart2/db/intan_m10.ace_cmp.cdb differ diff --git a/puart2/db/intan_m10.ace_cmp.hdb b/puart2/db/intan_m10.ace_cmp.hdb new file mode 100644 index 0000000..c3d50f7 Binary files /dev/null and b/puart2/db/intan_m10.ace_cmp.hdb differ diff --git a/puart2/db/intan_m10.ae.hdb b/puart2/db/intan_m10.ae.hdb new file mode 100644 index 0000000..bbed942 Binary files /dev/null and b/puart2/db/intan_m10.ae.hdb differ diff --git a/puart2/db/intan_m10.archive.qmsg b/puart2/db/intan_m10.archive.qmsg new file mode 100644 index 0000000..fa4a1ee --- /dev/null +++ b/puart2/db/intan_m10.archive.qmsg @@ -0,0 +1,21 @@ +{ "Info" "0" "" "File Set 'Source control' contains:" { { "Info" "0" "" "Project source and settings files" { } { } 0 0 "Project source and settings files" 0 0 "0" 0 0 1726883553136 ""} { "Info" "0" "" "Automatically detected source files" { } { } 0 0 "Automatically detected source files" 0 0 "0" 0 0 1726883553136 ""} } { } 0 0 "File Set 'Source control' contains:" 0 0 "Shell" 0 0 1726883553136 ""} +{ "Warning" "0" "" "Hierarchical Platform Designer systems and custom IP components(_hw.tcl and associated files) are not archived by the Quartus Archiver" { } { } 0 0 "Hierarchical Platform Designer systems and custom IP components(_hw.tcl and associated files) are not archived by the Quartus Archiver" 0 0 "Shell" 0 0 1726883553166 ""} +{ "Critical Warning" "0" "" "Analysis & Elaboration was not run successfully." { { "Critical Warning" "0" "" "The 'Automatically detected source files' file subset will attempt to guess which files are needed. The archive file will likely be larger than required and may still be incomplete." { } { } 1 0 "The 'Automatically detected source files' file subset will attempt to guess which files are needed. The archive file will likely be larger than required and may still be incomplete." 0 0 "0" 0 0 1726883553166 ""} } { } 1 0 "Analysis & Elaboration was not run successfully." 0 0 "Shell" 0 0 1726883553166 ""} +{ "Warning" "WPRJ_ARC_TCL_HDB_REQUIRE_FILES_NOT_EXIST" "20240625.v " "Can't find required hierarchy file 20240625.v" { } { } 0 225003 "Can't find required hierarchy file %1!s!" 0 0 "Shell" 0 -1 1726883553176 ""} +{ "Info" "0" "" "Parsing: spi_master_2164.v" { } { } 0 0 "Parsing: spi_master_2164.v" 0 0 "Shell" 0 0 1726883553306 ""} +{ "Info" "0" "" "Parsing: ddr_ctrl.v" { } { } 0 0 "Parsing: ddr_ctrl.v" 0 0 "Shell" 0 0 1726883553306 ""} +{ "Info" "0" "" "Parsing: clk_gen.v" { } { } 0 0 "Parsing: clk_gen.v" 0 0 "Shell" 0 0 1726883553306 ""} +{ "Info" "0" "" "Parsing: clk_gen_inst.v" { } { } 0 0 "Parsing: clk_gen_inst.v" 0 0 "Shell" 0 0 1726883553306 ""} +{ "Info" "0" "" "Parsing: clk_gen_bb.v" { } { } 0 0 "Parsing: clk_gen_bb.v" 0 0 "Shell" 0 0 1726883553316 ""} +{ "Info" "0" "" "Parsing: spi_master_esp32.v" { } { } 0 0 "Parsing: spi_master_esp32.v" 0 0 "Shell" 0 0 1726883553316 ""} +{ "Info" "0" "" "Parsing: intan_m10.v" { } { } 0 0 "Parsing: intan_m10.v" 0 0 "Shell" 0 0 1726883553316 ""} +{ "Info" "0" "" "Archive will store files relative to the closest common parent directory" { } { } 0 0 "Archive will store files relative to the closest common parent directory" 0 0 "Shell" 0 0 1726883553316 ""} +{ "Info" "IPRJ_ARC_TCL_TCL_USING_COMMON_DIR" "E:/FPGA/SPItransfer/20240726/ " "Using common directory E:/FPGA/SPItransfer/20240726/" { } { } 0 13213 "Using common directory %1!s!" 0 0 "Shell" 0 -1 1726883553336 ""} +{ "Info" "0" "" "----------------------------------------------------------" { } { } 0 0 "----------------------------------------------------------" 0 0 "Shell" 0 0 1726883553366 ""} +{ "Info" "0" "" "----------------------------------------------------------" { } { } 0 0 "----------------------------------------------------------" 0 0 "Shell" 0 0 1726883553366 ""} +{ "Info" "0" "" "Generated archive 'E:/FPGA/SPItransfer/20240726/uart_tx.qar'" { } { } 0 0 "Generated archive 'E:/FPGA/SPItransfer/20240726/uart_tx.qar'" 0 0 "Shell" 0 0 1726883553366 ""} +{ "Info" "0" "" "----------------------------------------------------------" { } { } 0 0 "----------------------------------------------------------" 0 0 "Shell" 0 0 1726883553366 ""} +{ "Info" "0" "" "----------------------------------------------------------" { } { } 0 0 "----------------------------------------------------------" 0 0 "Shell" 0 0 1726883553366 ""} +{ "Info" "0" "" "Generated report 'intan_m10.archive.rpt'" { } { } 0 0 "Generated report 'intan_m10.archive.rpt'" 0 0 "Shell" 0 0 1726883553376 ""} +{ "Error" "EQEXE_TCL_SCRIPT_STATUS" "e:/quartuslite/quartus/common/tcl/apps/qpm/qar.tcl " "Evaluation of Tcl script e:/quartuslite/quartus/common/tcl/apps/qpm/qar.tcl unsuccessful" { } { } 0 23031 "Evaluation of Tcl script %1!s! unsuccessful" 0 0 "Shell" 0 -1 1726883553376 ""} +{ "Error" "EQEXE_ERROR_COUNT" "Shell 6 s 17 s Quartus Prime " "Quartus Prime Shell was unsuccessful. 6 errors, 17 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "4826 " "Peak virtual memory: 4826 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1726883553376 ""} { "Error" "EQEXE_END_BANNER_TIME" "Sat Sep 21 09:52:33 2024 " "Processing ended: Sat Sep 21 09:52:33 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1726883553376 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1726883553376 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:20 " "Total CPU time (on all processors): 00:00:20" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1726883553376 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Shell" 0 -1 1726883553376 ""} diff --git a/puart2/db/intan_m10.archiver.cache b/puart2/db/intan_m10.archiver.cache new file mode 100644 index 0000000..5fc592e --- /dev/null +++ b/puart2/db/intan_m10.archiver.cache @@ -0,0 +1,21 @@ +file:E:/FPGA/SPItransfer/20240726/intan_m10.v +ts:1726883210 +init: +file:E:/FPGA/SPItransfer/20240726/spi_master_esp32.v +ts:1726153605 +init: +file:E:/FPGA/SPItransfer/20240726/clk_gen.v +ts:1726279939 +init: +file:E:/FPGA/SPItransfer/20240726/spi_master_2164.v +ts:1726034143 +init: +file:E:/FPGA/SPItransfer/20240726/clk_gen_inst.v +ts:1726279939 +init: +file:E:/FPGA/SPItransfer/20240726/clk_gen_bb.v +ts:1726279939 +init: +file:E:/FPGA/SPItransfer/20240726/ddr_ctrl.v +ts:1726883080 +init: diff --git a/puart2/db/intan_m10.asm.qmsg b/puart2/db/intan_m10.asm.qmsg new file mode 100644 index 0000000..a73df98 --- /dev/null +++ b/puart2/db/intan_m10.asm.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1765447233049 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1765447233062 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 11 18:00:32 2025 " "Processing started: Thu Dec 11 18:00:32 2025" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1765447233062 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1765447233062 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1765447233063 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1765447233787 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1765447233821 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4672 " "Peak virtual memory: 4672 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1765447234216 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 11 18:00:34 2025 " "Processing ended: Thu Dec 11 18:00:34 2025" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1765447234216 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1765447234216 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1765447234216 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1765447234216 ""} diff --git a/puart2/db/intan_m10.asm.rdb b/puart2/db/intan_m10.asm.rdb new file mode 100644 index 0000000..aa1b813 Binary files /dev/null and b/puart2/db/intan_m10.asm.rdb differ diff --git a/puart2/db/intan_m10.asm_labs.ddb b/puart2/db/intan_m10.asm_labs.ddb new file mode 100644 index 0000000..c95957d Binary files /dev/null and b/puart2/db/intan_m10.asm_labs.ddb differ diff --git a/puart2/db/intan_m10.cbx.xml b/puart2/db/intan_m10.cbx.xml new file mode 100644 index 0000000..e7f0b57 --- /dev/null +++ b/puart2/db/intan_m10.cbx.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/puart2/db/intan_m10.cmp.bpm b/puart2/db/intan_m10.cmp.bpm new file mode 100644 index 0000000..d29e1bd Binary files /dev/null and b/puart2/db/intan_m10.cmp.bpm differ diff --git a/puart2/db/intan_m10.cmp.cdb b/puart2/db/intan_m10.cmp.cdb new file mode 100644 index 0000000..b5012e2 Binary files /dev/null and b/puart2/db/intan_m10.cmp.cdb differ diff --git a/puart2/db/intan_m10.cmp.hdb b/puart2/db/intan_m10.cmp.hdb new file mode 100644 index 0000000..746feae Binary files /dev/null and b/puart2/db/intan_m10.cmp.hdb differ diff --git a/puart2/db/intan_m10.cmp.idb b/puart2/db/intan_m10.cmp.idb new file mode 100644 index 0000000..1823b44 Binary files /dev/null and b/puart2/db/intan_m10.cmp.idb differ diff --git a/puart2/db/intan_m10.cmp.logdb b/puart2/db/intan_m10.cmp.logdb new file mode 100644 index 0000000..b1531ae --- /dev/null +++ b/puart2/db/intan_m10.cmp.logdb @@ -0,0 +1,54 @@ +v1 +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, +IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,, +IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,, +IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os.,Critical,0 such failures found.,,I/O,, +IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, +IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042, +IO_RULES_MATRIX,Total Pass,13;0;13;0;0;13;13;0;13;13;0;0;0;0;4;0;0;4;0;0;0;0;0;0;0;0;0;13;0;0, +IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Total Inapplicable,0;13;0;13;13;0;0;13;0;0;13;13;13;13;9;13;13;9;13;13;13;13;13;13;13;13;13;0;13;13, +IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,mosi,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,cs_n,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,sclk,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,MOSI_ESP32,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,cs_ESP32,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,sclk_ESP32,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tx,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,test_flag_led,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,convert_flag_led,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,test_flag,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,rst_n,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,sys_clk,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,miso,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_SUMMARY,Total I/O Rules,30, +IO_RULES_SUMMARY,Number of I/O Rules Passed,9, +IO_RULES_SUMMARY,Number of I/O Rules Failed,0, +IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,21, diff --git a/puart2/db/intan_m10.cmp.rdb b/puart2/db/intan_m10.cmp.rdb new file mode 100644 index 0000000..3317f09 Binary files /dev/null and b/puart2/db/intan_m10.cmp.rdb differ diff --git a/puart2/db/intan_m10.cmp_merge.kpt b/puart2/db/intan_m10.cmp_merge.kpt new file mode 100644 index 0000000..89c56d3 Binary files /dev/null and b/puart2/db/intan_m10.cmp_merge.kpt differ diff --git a/puart2/db/intan_m10.db_info b/puart2/db/intan_m10.db_info new file mode 100644 index 0000000..f3660bf --- /dev/null +++ b/puart2/db/intan_m10.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition +Version_Index = 453135872 +Creation_Time = Thu Dec 11 17:21:09 2025 diff --git a/puart2/db/intan_m10.eco.cdb b/puart2/db/intan_m10.eco.cdb new file mode 100644 index 0000000..68218e4 Binary files /dev/null and b/puart2/db/intan_m10.eco.cdb differ diff --git a/puart2/db/intan_m10.fit.qmsg b/puart2/db/intan_m10.fit.qmsg new file mode 100644 index 0000000..3a4f047 --- /dev/null +++ b/puart2/db/intan_m10.fit.qmsg @@ -0,0 +1,54 @@ +{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "4 " "Parallel compilation is enabled and will use up to 4 processors" { } { } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Fitter" 0 -1 1765447227432 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "intan_m10 10M08SAM153C8G " "Selected device 10M08SAM153C8G for design \"intan_m10\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1765447227440 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1765447227474 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1765447227474 ""} +{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|pll1 MAX 10 PLL " "Implemented PLL \"clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|pll1\" as MAX 10 PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] 6 625 0 0 " "Implementing clock multiplication of 6, clock division of 625, and phase shift of 0 degrees (0 ps) for clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/clk_gen_altpll.v" "" { Text "E:/FPGA/puart2/db/clk_gen_altpll.v" 43 -1 0 } } { "" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 124 14177 15141 0 0 "" 0 "" "" } } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Design Software" 0 -1 1765447227517 ""} } { { "db/clk_gen_altpll.v" "" { Text "E:/FPGA/puart2/db/clk_gen_altpll.v" 43 -1 0 } } { "" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 124 14177 15141 0 0 "" 0 "" "" } } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1765447227517 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1765447227564 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1765447227572 ""} +{ "Critical Warning" "WFCUDA_FCUDA_SPS_DEVICE_POWER_LIMITATION" "" "Review the Power Analyzer report file (.pow.rpt) to ensure your design is within the maximum power utilization limit of the single power-supply target device and to avoid functional failures." { } { } 1 16562 "Review the Power Analyzer report file (.pow.rpt) to ensure your design is within the maximum power utilization limit of the single power-supply target device and to avoid functional failures." 0 0 "Fitter" 0 -1 1765447227690 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M08SAM153C8GES " "Device 10M08SAM153C8GES is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1765447227701 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M04SAM153C8G " "Device 10M04SAM153C8G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1765447227701 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1765447227701 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "8 " "Fitter converted 8 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TMS~ G1 " "Pin ~ALTERA_TMS~ is reserved at location G1" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { ~ALTERA_TMS~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 395 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765447227702 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TCK~ J1 " "Pin ~ALTERA_TCK~ is reserved at location J1" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { ~ALTERA_TCK~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 397 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765447227702 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDI~ H5 " "Pin ~ALTERA_TDI~ is reserved at location H5" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDI~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 399 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765447227702 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDO~ H4 " "Pin ~ALTERA_TDO~ is reserved at location H4" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDO~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 401 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765447227702 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONFIG_SEL~ D8 " "Pin ~ALTERA_CONFIG_SEL~ is reserved at location D8" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONFIG_SEL~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 403 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765447227702 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCONFIG~ E8 " "Pin ~ALTERA_nCONFIG~ is reserved at location E8" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCONFIG~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 405 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765447227702 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nSTATUS~ D6 " "Pin ~ALTERA_nSTATUS~ is reserved at location D6" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { ~ALTERA_nSTATUS~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 407 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765447227702 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONF_DONE~ E6 " "Pin ~ALTERA_CONF_DONE~ is reserved at location E6" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONF_DONE~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 409 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765447227702 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1765447227702 ""} +{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" { } { } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1765447227703 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1765447227703 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1765447227703 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1765447227703 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1765447227703 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "intan_m10.sdc " "Synopsys Design Constraints File file not found: 'intan_m10.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1765447228110 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "generated clocks " "No user constrained generated clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1765447228110 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1765447228111 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1765447228114 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1765447228114 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1765447228114 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C1 of PLL_1) " "Automatically promoted node clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C1 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1765447228130 ""} } { { "db/clk_gen_altpll.v" "" { Text "E:/FPGA/puart2/db/clk_gen_altpll.v" 77 -1 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 124 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1765447228130 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "spi_master_2164:u_spi_master_2164\|cs_n " "Automatically promoted node spi_master_2164:u_spi_master_2164\|cs_n " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1765447228130 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "cs_n~output " "Destination node cs_n~output" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 9 0 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 376 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1765447228130 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1765447228130 ""} } { { "spi_master_2164.v" "" { Text "E:/FPGA/puart2/spi_master_2164.v" 11 -1 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 119 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1765447228130 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1765447228429 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1765447228430 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1765447228430 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1765447228431 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1765447228431 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1765447228432 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1765447228432 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1765447228432 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1765447228442 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1765447228443 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1765447228443 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1765447228463 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1765447228466 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1765447228928 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1765447228977 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1765447228986 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1765447229349 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1765447229349 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1765447229707 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X10_Y0 X20_Y12 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X10_Y0 to location X20_Y12" { } { { "loc" "" { Generic "E:/FPGA/puart2/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X10_Y0 to location X20_Y12"} { { 12 { 0 ""} 10 0 11 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1765447230052 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1765447230052 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1765447230330 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1765447230330 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1765447230333 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.15 " "Total time spent on timing analysis during the Fitter is 0.15 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1765447230488 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1765447230493 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1765447230679 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1765447230680 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1765447230967 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1765447231409 ""} +{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "4 MAX 10 " "4 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing MAX 10 Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "test_flag 3.3-V LVCMOS J12 " "Pin test_flag uses I/O standard 3.3-V LVCMOS at J12" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { test_flag } } } { "e:/quartuslite/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/quartuslite/quartus/bin64/Assignment Editor.qase" 1 { { 0 "test_flag" } } } } { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 4 0 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 11 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1765447231526 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "rst_n 3.3-V LVCMOS J14 " "Pin rst_n uses I/O standard 3.3-V LVCMOS at J14" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { rst_n } } } { "e:/quartuslite/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/quartuslite/quartus/bin64/Assignment Editor.qase" 1 { { 0 "rst_n" } } } } { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 3 0 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 10 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1765447231526 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "sys_clk 3.3-V LVCMOS J5 " "Pin sys_clk uses I/O standard 3.3-V LVCMOS at J5" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { sys_clk } } } { "e:/quartuslite/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/quartuslite/quartus/bin64/Assignment Editor.qase" 1 { { 0 "sys_clk" } } } } { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 2 0 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 9 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1765447231526 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "miso 3.3-V LVCMOS P4 " "Pin miso uses I/O standard 3.3-V LVCMOS at P4" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { miso } } } { "e:/quartuslite/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/quartuslite/quartus/bin64/Assignment Editor.qase" 1 { { 0 "miso" } } } } { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 7 0 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 12 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1765447231526 ""} } { } 0 169177 "%1!d! pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1765447231526 ""} +{ "Warning" "WFIOMGR_INCONSISTENT_VCCIO_ACROSS_MULTIPLE_BANKS_OF_CONFIGURAION_PINS" "2 Internal Configuration 2 " "Inconsistent VCCIO across multiple banks of configuration pins. The configuration pins are contained in 2 banks in 'Internal Configuration' configuration scheme and there are 2 different VCCIOs." { } { } 0 169202 "Inconsistent VCCIO across multiple banks of configuration pins. The configuration pins are contained in %1!d! banks in '%2!s!' configuration scheme and there are %3!d! different VCCIOs." 0 0 "Fitter" 0 -1 1765447231527 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/FPGA/puart2/output_files/intan_m10.fit.smsg " "Generated suppressed messages file E:/FPGA/puart2/output_files/intan_m10.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1765447231568 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5547 " "Peak virtual memory: 5547 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1765447231939 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 11 18:00:31 2025 " "Processing ended: Thu Dec 11 18:00:31 2025" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1765447231939 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1765447231939 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1765447231939 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1765447231939 ""} diff --git a/puart2/db/intan_m10.hier_info b/puart2/db/intan_m10.hier_info new file mode 100644 index 0000000..6a86d2f --- /dev/null +++ b/puart2/db/intan_m10.hier_info @@ -0,0 +1,460 @@ +|ddr_ctrl +sys_clk => sys_clk.IN2 +rst_n => rst_n.IN3 +test_flag => Selector12.IN4 +test_flag => test_flag_led.DATAIN +test_flag => convert_flag_led.DATAIN +test_flag => Selector8.IN2 +test_flag => Selector9.IN2 +test_flag => Selector10.IN2 +test_flag => Selector11.IN2 +test_flag => Selector7.IN2 +miso => miso.IN1 +mosi <= spi_master_2164:u_spi_master_2164.mosi +cs_n <= spi_master_2164:u_spi_master_2164.cs_n +sclk <= spi_master_2164:u_spi_master_2164.sclk +MOSI_ESP32 <= spi_master_esp32:tranfer.mosi +cs_ESP32 <= spi_master_esp32:tranfer.cs +sclk_ESP32 <= spi_master_esp32:tranfer.sclk +tx <= uart_tx:u_uart_pc.tx +test_flag_led <= test_flag.DB_MAX_OUTPUT_PORT_TYPE +convert_flag_led <= test_flag.DB_MAX_OUTPUT_PORT_TYPE + + +|ddr_ctrl|clk_gen:clk_gen_inst +inclk0 => sub_wire1[0].IN1 +c0 <= altpll:altpll_component.clk +c1 <= altpll:altpll_component.clk + + +|ddr_ctrl|clk_gen:clk_gen_inst|altpll:altpll_component +inclk[0] => clk_gen_altpll:auto_generated.inclk[0] +inclk[1] => clk_gen_altpll:auto_generated.inclk[1] +fbin => ~NO_FANOUT~ +pllena => ~NO_FANOUT~ +clkswitch => ~NO_FANOUT~ +areset => ~NO_FANOUT~ +pfdena => ~NO_FANOUT~ +clkena[0] => ~NO_FANOUT~ +clkena[1] => ~NO_FANOUT~ +clkena[2] => ~NO_FANOUT~ +clkena[3] => ~NO_FANOUT~ +clkena[4] => ~NO_FANOUT~ +clkena[5] => ~NO_FANOUT~ +extclkena[0] => ~NO_FANOUT~ +extclkena[1] => ~NO_FANOUT~ +extclkena[2] => ~NO_FANOUT~ +extclkena[3] => ~NO_FANOUT~ +scanclk => ~NO_FANOUT~ +scanclkena => ~NO_FANOUT~ +scanaclr => ~NO_FANOUT~ +scanread => ~NO_FANOUT~ +scanwrite => ~NO_FANOUT~ +scandata => ~NO_FANOUT~ +phasecounterselect[0] => ~NO_FANOUT~ +phasecounterselect[1] => ~NO_FANOUT~ +phasecounterselect[2] => ~NO_FANOUT~ +phasecounterselect[3] => ~NO_FANOUT~ +phaseupdown => ~NO_FANOUT~ +phasestep => ~NO_FANOUT~ +configupdate => ~NO_FANOUT~ +fbmimicbidir <> +clk[0] <= clk[0].DB_MAX_OUTPUT_PORT_TYPE +clk[1] <= clk[1].DB_MAX_OUTPUT_PORT_TYPE +clk[2] <= clk[2].DB_MAX_OUTPUT_PORT_TYPE +clk[3] <= clk[3].DB_MAX_OUTPUT_PORT_TYPE +clk[4] <= clk[4].DB_MAX_OUTPUT_PORT_TYPE +extclk[0] <= +extclk[1] <= +extclk[2] <= +extclk[3] <= +clkbad[0] <= +clkbad[1] <= +enable1 <= +enable0 <= +activeclock <= +clkloss <= +locked <= +scandataout <= +scandone <= +sclkout0 <= +sclkout1 <= +phasedone <= +vcooverrange <= +vcounderrange <= +fbout <= +fref <= +icdrclk <= + + +|ddr_ctrl|clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated +clk[0] <= pll1.CLK +clk[1] <= pll1.CLK1 +clk[2] <= pll1.CLK2 +clk[3] <= pll1.CLK3 +clk[4] <= pll1.CLK4 +inclk[0] => pll1.CLK +inclk[1] => pll1.CLK1 + + +|ddr_ctrl|spi_master_2164:u_spi_master_2164 +sys_clk => dout[0]~reg0.CLK +sys_clk => dout[1]~reg0.CLK +sys_clk => dout[2]~reg0.CLK +sys_clk => dout[3]~reg0.CLK +sys_clk => dout[4]~reg0.CLK +sys_clk => dout[5]~reg0.CLK +sys_clk => dout[6]~reg0.CLK +sys_clk => dout[7]~reg0.CLK +sys_clk => dout[8]~reg0.CLK +sys_clk => dout[9]~reg0.CLK +sys_clk => dout[10]~reg0.CLK +sys_clk => dout[11]~reg0.CLK +sys_clk => dout[12]~reg0.CLK +sys_clk => dout[13]~reg0.CLK +sys_clk => dout[14]~reg0.CLK +sys_clk => dout[15]~reg0.CLK +sys_clk => done~reg0.CLK +sys_clk => dout_r[0].CLK +sys_clk => dout_r[1].CLK +sys_clk => dout_r[2].CLK +sys_clk => dout_r[3].CLK +sys_clk => dout_r[4].CLK +sys_clk => dout_r[5].CLK +sys_clk => dout_r[6].CLK +sys_clk => dout_r[7].CLK +sys_clk => dout_r[8].CLK +sys_clk => dout_r[9].CLK +sys_clk => dout_r[10].CLK +sys_clk => dout_r[11].CLK +sys_clk => dout_r[12].CLK +sys_clk => dout_r[13].CLK +sys_clk => dout_r[14].CLK +sys_clk => dout_r[15].CLK +sys_clk => mosi~reg0.CLK +sys_clk => cs_n~reg0.CLK +sys_clk => sclk~reg0.CLK +sys_clk => cnt[0]~reg0.CLK +sys_clk => cnt[1]~reg0.CLK +sys_clk => cnt[2]~reg0.CLK +sys_clk => cnt[3]~reg0.CLK +sys_clk => cnt[4]~reg0.CLK +sys_clk => cnt[5]~reg0.CLK +sys_clk => cnt[6]~reg0.CLK +rst_n => mosi~reg0.ACLR +rst_n => cs_n~reg0.PRESET +rst_n => sclk~reg0.ACLR +rst_n => dout[0]~reg0.ACLR +rst_n => dout[1]~reg0.ACLR +rst_n => dout[2]~reg0.ACLR +rst_n => dout[3]~reg0.ACLR +rst_n => dout[4]~reg0.ACLR +rst_n => dout[5]~reg0.ACLR +rst_n => dout[6]~reg0.ACLR +rst_n => dout[7]~reg0.ACLR +rst_n => dout[8]~reg0.ACLR +rst_n => dout[9]~reg0.ACLR +rst_n => dout[10]~reg0.ACLR +rst_n => dout[11]~reg0.ACLR +rst_n => dout[12]~reg0.ACLR +rst_n => dout[13]~reg0.ACLR +rst_n => dout[14]~reg0.ACLR +rst_n => dout[15]~reg0.ACLR +rst_n => done~reg0.ACLR +rst_n => cnt[0]~reg0.ACLR +rst_n => cnt[1]~reg0.ACLR +rst_n => cnt[2]~reg0.ACLR +rst_n => cnt[3]~reg0.ACLR +rst_n => cnt[4]~reg0.ACLR +rst_n => cnt[5]~reg0.ACLR +rst_n => cnt[6]~reg0.ACLR +rst_n => dout_r[15].ENA +rst_n => dout_r[14].ENA +rst_n => dout_r[13].ENA +rst_n => dout_r[12].ENA +rst_n => dout_r[11].ENA +rst_n => dout_r[10].ENA +rst_n => dout_r[9].ENA +rst_n => dout_r[8].ENA +rst_n => dout_r[7].ENA +rst_n => dout_r[6].ENA +rst_n => dout_r[5].ENA +rst_n => dout_r[4].ENA +rst_n => dout_r[3].ENA +rst_n => dout_r[2].ENA +rst_n => dout_r[1].ENA +rst_n => dout_r[0].ENA +din[0] => Selector0.IN33 +din[1] => Selector0.IN32 +din[2] => Selector0.IN31 +din[3] => Selector0.IN30 +din[4] => Selector0.IN29 +din[5] => Selector0.IN28 +din[6] => Selector0.IN27 +din[7] => Selector0.IN26 +din[8] => Selector0.IN25 +din[9] => Selector0.IN24 +din[10] => Selector0.IN23 +din[11] => Selector0.IN22 +din[12] => Selector0.IN21 +din[13] => Selector0.IN20 +din[14] => Selector0.IN19 +din[15] => Selector0.IN18 +start => cnt.OUTPUTSELECT +start => cnt.OUTPUTSELECT +start => cnt.OUTPUTSELECT +start => cnt.OUTPUTSELECT +start => cnt.OUTPUTSELECT +start => cnt.OUTPUTSELECT +start => cnt.OUTPUTSELECT +dout[0] <= dout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dout[1] <= dout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dout[2] <= dout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dout[3] <= dout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dout[4] <= dout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dout[5] <= dout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dout[6] <= dout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dout[7] <= dout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dout[8] <= dout[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dout[9] <= dout[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dout[10] <= dout[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dout[11] <= dout[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dout[12] <= dout[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dout[13] <= dout[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dout[14] <= dout[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dout[15] <= dout[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +done <= done~reg0.DB_MAX_OUTPUT_PORT_TYPE +sclk <= sclk~reg0.DB_MAX_OUTPUT_PORT_TYPE +cs_n <= cs_n~reg0.DB_MAX_OUTPUT_PORT_TYPE +mosi <= mosi~reg0.DB_MAX_OUTPUT_PORT_TYPE +miso => dout_r.DATAB +cnt[0] <= cnt[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +cnt[1] <= cnt[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +cnt[2] <= cnt[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +cnt[3] <= cnt[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +cnt[4] <= cnt[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +cnt[5] <= cnt[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +cnt[6] <= cnt[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|ddr_ctrl|spi_master_esp32:tranfer +clk => done~reg0.CLK +clk => shift_reg[0].CLK +clk => shift_reg[1].CLK +clk => shift_reg[2].CLK +clk => shift_reg[3].CLK +clk => shift_reg[4].CLK +clk => shift_reg[5].CLK +clk => shift_reg[6].CLK +clk => shift_reg[7].CLK +clk => shift_reg[8].CLK +clk => shift_reg[9].CLK +clk => shift_reg[10].CLK +clk => shift_reg[11].CLK +clk => shift_reg[12].CLK +clk => shift_reg[13].CLK +clk => shift_reg[14].CLK +clk => shift_reg[15].CLK +clk => bit_cnt[0].CLK +clk => bit_cnt[1].CLK +clk => bit_cnt[2].CLK +clk => bit_cnt[3].CLK +clk => sclk_reg.CLK +clk => cs~reg0.CLK +clk => state~4.DATAIN +rst_n => done~reg0.ACLR +rst_n => shift_reg[0].ACLR +rst_n => shift_reg[1].ACLR +rst_n => shift_reg[2].ACLR +rst_n => shift_reg[3].ACLR +rst_n => shift_reg[4].ACLR +rst_n => shift_reg[5].ACLR +rst_n => shift_reg[6].ACLR +rst_n => shift_reg[7].ACLR +rst_n => shift_reg[8].ACLR +rst_n => shift_reg[9].ACLR +rst_n => shift_reg[10].ACLR +rst_n => shift_reg[11].ACLR +rst_n => shift_reg[12].ACLR +rst_n => shift_reg[13].ACLR +rst_n => shift_reg[14].ACLR +rst_n => shift_reg[15].ACLR +rst_n => bit_cnt[0].ACLR +rst_n => bit_cnt[1].ACLR +rst_n => bit_cnt[2].ACLR +rst_n => bit_cnt[3].ACLR +rst_n => sclk_reg.ACLR +rst_n => cs~reg0.PRESET +rst_n => state~6.DATAIN +start => state.OUTPUTSELECT +start => state.OUTPUTSELECT +start => state.OUTPUTSELECT +start => done~reg0.ENA +start => cs~reg0.ENA +start => sclk_reg.ENA +start => bit_cnt[3].ENA +start => bit_cnt[2].ENA +start => bit_cnt[1].ENA +start => bit_cnt[0].ENA +start => shift_reg[15].ENA +start => shift_reg[14].ENA +start => shift_reg[13].ENA +start => shift_reg[12].ENA +start => shift_reg[11].ENA +start => shift_reg[10].ENA +start => shift_reg[9].ENA +start => shift_reg[8].ENA +start => shift_reg[7].ENA +start => shift_reg[6].ENA +start => shift_reg[5].ENA +start => shift_reg[4].ENA +start => shift_reg[3].ENA +start => shift_reg[2].ENA +start => shift_reg[1].ENA +start => shift_reg[0].ENA +din[0] => Selector18.IN1 +din[1] => Selector17.IN1 +din[2] => Selector16.IN1 +din[3] => Selector15.IN1 +din[4] => Selector14.IN1 +din[5] => Selector13.IN1 +din[6] => Selector12.IN1 +din[7] => Selector11.IN1 +din[8] => Selector10.IN1 +din[9] => Selector9.IN1 +din[10] => Selector8.IN1 +din[11] => Selector7.IN1 +din[12] => Selector6.IN1 +din[13] => Selector5.IN1 +din[14] => Selector4.IN1 +din[15] => Selector3.IN1 +done <= done~reg0.DB_MAX_OUTPUT_PORT_TYPE +sclk <= sclk_reg.DB_MAX_OUTPUT_PORT_TYPE +mosi <= shift_reg[15].DB_MAX_OUTPUT_PORT_TYPE +cs <= cs~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|ddr_ctrl|uart_tx:u_uart_pc +clk => tx_bit_counter[0].CLK +clk => tx_bit_counter[1].CLK +clk => tx_bit_counter[2].CLK +clk => tx_bit_counter[3].CLK +clk => data_to_send[0].CLK +clk => data_to_send[1].CLK +clk => data_to_send[2].CLK +clk => data_to_send[3].CLK +clk => data_to_send[4].CLK +clk => data_to_send[5].CLK +clk => data_to_send[6].CLK +clk => data_to_send[7].CLK +clk => tx_shift_reg[0].CLK +clk => tx_shift_reg[1].CLK +clk => tx_shift_reg[2].CLK +clk => tx_shift_reg[3].CLK +clk => tx_shift_reg[4].CLK +clk => tx_shift_reg[5].CLK +clk => tx_shift_reg[6].CLK +clk => tx_shift_reg[7].CLK +clk => tx_shift_reg[8].CLK +clk => tx_shift_reg[9].CLK +clk => tx_done~reg0.CLK +clk => baud_counter[0].CLK +clk => baud_counter[1].CLK +clk => baud_counter[2].CLK +clk => baud_counter[3].CLK +clk => baud_counter[4].CLK +clk => baud_counter[5].CLK +clk => baud_counter[6].CLK +clk => baud_counter[7].CLK +clk => baud_counter[8].CLK +clk => baud_counter[9].CLK +clk => baud_counter[10].CLK +clk => baud_counter[11].CLK +clk => baud_counter[12].CLK +clk => baud_counter[13].CLK +clk => baud_counter[14].CLK +clk => baud_counter[15].CLK +clk => byte_select~2.DATAIN +clk => tx_state~3.DATAIN +rst => tx_shift_reg[0].PRESET +rst => tx_shift_reg[1].PRESET +rst => tx_shift_reg[2].PRESET +rst => tx_shift_reg[3].PRESET +rst => tx_shift_reg[4].PRESET +rst => tx_shift_reg[5].PRESET +rst => tx_shift_reg[6].PRESET +rst => tx_shift_reg[7].PRESET +rst => tx_shift_reg[8].PRESET +rst => tx_shift_reg[9].PRESET +rst => tx_done~reg0.ACLR +rst => baud_counter[0].ACLR +rst => baud_counter[1].ACLR +rst => baud_counter[2].ACLR +rst => baud_counter[3].ACLR +rst => baud_counter[4].ACLR +rst => baud_counter[5].ACLR +rst => baud_counter[6].ACLR +rst => baud_counter[7].ACLR +rst => baud_counter[8].ACLR +rst => baud_counter[9].ACLR +rst => baud_counter[10].ACLR +rst => baud_counter[11].ACLR +rst => baud_counter[12].ACLR +rst => baud_counter[13].ACLR +rst => baud_counter[14].ACLR +rst => baud_counter[15].ACLR +rst => byte_select~4.DATAIN +rst => tx_state~5.DATAIN +rst => tx_bit_counter[0].ENA +rst => data_to_send[7].ENA +rst => data_to_send[6].ENA +rst => data_to_send[5].ENA +rst => data_to_send[4].ENA +rst => data_to_send[3].ENA +rst => data_to_send[2].ENA +rst => data_to_send[1].ENA +rst => data_to_send[0].ENA +rst => tx_bit_counter[3].ENA +rst => tx_bit_counter[2].ENA +rst => tx_bit_counter[1].ENA +tx_start => data_to_send.OUTPUTSELECT +tx_start => data_to_send.OUTPUTSELECT +tx_start => data_to_send.OUTPUTSELECT +tx_start => data_to_send.OUTPUTSELECT +tx_start => data_to_send.OUTPUTSELECT +tx_start => data_to_send.OUTPUTSELECT +tx_start => data_to_send.OUTPUTSELECT +tx_start => data_to_send.OUTPUTSELECT +tx_start => tx_shift_reg.OUTPUTSELECT +tx_start => tx_shift_reg.OUTPUTSELECT +tx_start => tx_shift_reg.OUTPUTSELECT +tx_start => tx_shift_reg.OUTPUTSELECT +tx_start => tx_shift_reg.OUTPUTSELECT +tx_start => tx_shift_reg.OUTPUTSELECT +tx_start => tx_shift_reg.OUTPUTSELECT +tx_start => tx_shift_reg.OUTPUTSELECT +tx_start => tx_shift_reg.OUTPUTSELECT +tx_start => tx_shift_reg.OUTPUTSELECT +tx_start => tx_state.OUTPUTSELECT +tx_start => tx_state.OUTPUTSELECT +tx_start => tx_done.OUTPUTSELECT +tx_data[0] => data_to_send.DATAA +tx_data[1] => data_to_send.DATAA +tx_data[2] => data_to_send.DATAA +tx_data[3] => data_to_send.DATAA +tx_data[4] => data_to_send.DATAA +tx_data[5] => data_to_send.DATAA +tx_data[6] => data_to_send.DATAA +tx_data[7] => data_to_send.DATAA +tx_data[8] => data_to_send.DATAB +tx_data[9] => data_to_send.DATAB +tx_data[10] => data_to_send.DATAB +tx_data[11] => data_to_send.DATAB +tx_data[12] => data_to_send.DATAB +tx_data[13] => data_to_send.DATAB +tx_data[14] => data_to_send.DATAB +tx_data[15] => data_to_send.DATAB +tx <= tx_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE +tx_done <= tx_done~reg0.DB_MAX_OUTPUT_PORT_TYPE + + diff --git a/puart2/db/intan_m10.hif b/puart2/db/intan_m10.hif new file mode 100644 index 0000000..ef15384 Binary files /dev/null and b/puart2/db/intan_m10.hif differ diff --git a/puart2/db/intan_m10.lpc.html b/puart2/db/intan_m10.lpc.html new file mode 100644 index 0000000..f00e4e0 --- /dev/null +++ b/puart2/db/intan_m10.lpc.html @@ -0,0 +1,98 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
u_uart_pc19000200000000
tranfer19000400000000
u_spi_master_2164200002000000000
clk_gen_inst|altpll_component|auto_generated2000500000000
clk_gen_inst1000200000000
diff --git a/puart2/db/intan_m10.lpc.rdb b/puart2/db/intan_m10.lpc.rdb new file mode 100644 index 0000000..32bb4ee Binary files /dev/null and b/puart2/db/intan_m10.lpc.rdb differ diff --git a/puart2/db/intan_m10.lpc.txt b/puart2/db/intan_m10.lpc.txt new file mode 100644 index 0000000..f4822c3 --- /dev/null +++ b/puart2/db/intan_m10.lpc.txt @@ -0,0 +1,11 @@ ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++----------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++----------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; u_uart_pc ; 19 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; tranfer ; 19 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; u_spi_master_2164 ; 20 ; 0 ; 0 ; 0 ; 20 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; clk_gen_inst|altpll_component|auto_generated ; 2 ; 0 ; 0 ; 0 ; 5 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; clk_gen_inst ; 1 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ++----------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/puart2/db/intan_m10.map.ammdb b/puart2/db/intan_m10.map.ammdb new file mode 100644 index 0000000..e8d19e2 Binary files /dev/null and b/puart2/db/intan_m10.map.ammdb differ diff --git a/puart2/db/intan_m10.map.bpm b/puart2/db/intan_m10.map.bpm new file mode 100644 index 0000000..3f349d6 Binary files /dev/null and b/puart2/db/intan_m10.map.bpm differ diff --git a/puart2/db/intan_m10.map.cdb b/puart2/db/intan_m10.map.cdb new file mode 100644 index 0000000..b94082e Binary files /dev/null and b/puart2/db/intan_m10.map.cdb differ diff --git a/puart2/db/intan_m10.map.hdb b/puart2/db/intan_m10.map.hdb new file mode 100644 index 0000000..aa658ff Binary files /dev/null and b/puart2/db/intan_m10.map.hdb differ diff --git a/puart2/db/intan_m10.map.kpt b/puart2/db/intan_m10.map.kpt new file mode 100644 index 0000000..8021afe Binary files /dev/null and b/puart2/db/intan_m10.map.kpt differ diff --git a/puart2/db/intan_m10.map.logdb b/puart2/db/intan_m10.map.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/puart2/db/intan_m10.map.logdb @@ -0,0 +1 @@ +v1 diff --git a/puart2/db/intan_m10.map.qmsg b/puart2/db/intan_m10.map.qmsg new file mode 100644 index 0000000..930da0f --- /dev/null +++ b/puart2/db/intan_m10.map.qmsg @@ -0,0 +1,38 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1765447215980 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1765447215990 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 11 18:00:15 2025 " "Processing started: Thu Dec 11 18:00:15 2025" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1765447215990 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765447215990 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off intan_m10 -c intan_m10 " "Command: quartus_map --read_settings_files=on --write_settings_files=off intan_m10 -c intan_m10" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765447215990 ""} +{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "4 " "Parallel compilation is enabled and will use up to 4 processors" { } { } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Analysis & Synthesis" 0 -1 1765447216375 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spi_master_2164.v 1 1 " "Found 1 design units, including 1 entities, in source file spi_master_2164.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi_master_2164 " "Found entity 1: spi_master_2164" { } { { "spi_master_2164.v" "" { Text "E:/FPGA/puart2/spi_master_2164.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1765447224728 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765447224728 ""} +{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "ddr_ctrl.v(151) " "Verilog HDL information at ddr_ctrl.v(151): always construct contains both blocking and non-blocking assignments" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 151 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1765447224731 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr_ctrl.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr_ctrl.v" { { "Info" "ISGN_ENTITY_NAME" "1 ddr_ctrl " "Found entity 1: ddr_ctrl" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1765447224732 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765447224732 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clk_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file clk_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_gen " "Found entity 1: clk_gen" { } { { "clk_gen.v" "" { Text "E:/FPGA/puart2/clk_gen.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1765447224734 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765447224734 ""} +{ "Warning" "WSGN_FILE_IS_MISSING" "../../20240625.v " "Can't analyze file -- file ../../20240625.v is missing" { } { } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Analysis & Synthesis" 0 -1 1765447224737 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "done DONE spi_master_esp32.v(6) " "Verilog HDL Declaration information at spi_master_esp32.v(6): object \"done\" differs only in case from object \"DONE\" in the same scope" { } { { "spi_master_esp32.v" "" { Text "E:/FPGA/puart2/spi_master_esp32.v" 6 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1765447224740 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spi_master_esp32.v 1 1 " "Found 1 design units, including 1 entities, in source file spi_master_esp32.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi_master_esp32 " "Found entity 1: spi_master_esp32" { } { { "spi_master_esp32.v" "" { Text "E:/FPGA/puart2/spi_master_esp32.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1765447224740 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765447224740 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_tx.v 1 1 " "Found 1 design units, including 1 entities, in source file uart_tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart_tx " "Found entity 1: uart_tx" { } { { "uart_tx.v" "" { Text "E:/FPGA/puart2/uart_tx.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1765447224743 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765447224743 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "ddr_ctrl " "Elaborating entity \"ddr_ctrl\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1765447224790 ""} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "received_data ddr_ctrl.v(71) " "Verilog HDL or VHDL warning at ddr_ctrl.v(71): object \"received_data\" assigned a value but never read" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 71 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1765447224791 "|ddr_ctrl"} +{ "Warning" "WVRFX_L2_VERI_ASSUMED_INCOMPLETE_CASE" "ddr_ctrl.v(153) " "Verilog HDL warning at ddr_ctrl.v(153): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 153 0 0 } } } 0 10763 "Verilog HDL warning at %1!s!: case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness" 0 0 "Analysis & Synthesis" 0 -1 1765447224793 "|ddr_ctrl"} +{ "Warning" "WVRFX_L2_VERI_FULL_CASE_DIRECTIVE_EFFECTIVE" "ddr_ctrl.v(153) " "Verilog HDL Case Statement warning at ddr_ctrl.v(153): honored full_case synthesis attribute - differences between design synthesis and simulation may occur" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 153 0 0 } } } 0 10208 "Verilog HDL Case Statement warning at %1!s!: honored full_case synthesis attribute - differences between design synthesis and simulation may occur" 0 0 "Analysis & Synthesis" 0 -1 1765447224793 "|ddr_ctrl"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_gen clk_gen:clk_gen_inst " "Elaborating entity \"clk_gen\" for hierarchy \"clk_gen:clk_gen_inst\"" { } { { "ddr_ctrl.v" "clk_gen_inst" { Text "E:/FPGA/puart2/ddr_ctrl.v" 204 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765447224811 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll clk_gen:clk_gen_inst\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"clk_gen:clk_gen_inst\|altpll:altpll_component\"" { } { { "clk_gen.v" "altpll_component" { Text "E:/FPGA/puart2/clk_gen.v" 94 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765447224854 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "clk_gen:clk_gen_inst\|altpll:altpll_component " "Elaborated megafunction instantiation \"clk_gen:clk_gen_inst\|altpll:altpll_component\"" { } { { "clk_gen.v" "" { Text "E:/FPGA/puart2/clk_gen.v" 94 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765447224855 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "clk_gen:clk_gen_inst\|altpll:altpll_component " "Instantiated megafunction \"clk_gen:clk_gen_inst\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 625 " "Parameter \"clk0_divide_by\" = \"625\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 6 " "Parameter \"clk0_multiply_by\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 625 " "Parameter \"clk1_divide_by\" = \"625\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 12 " "Parameter \"clk1_multiply_by\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 0 " "Parameter \"clk1_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 83333 " "Parameter \"inclk0_input_frequency\" = \"83333\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family MAX 10 " "Parameter \"intended_device_family\" = \"MAX 10\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=clk_gen " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=clk_gen\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_UNUSED " "Parameter \"port_locked\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Parameter \"port_clk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} } { { "clk_gen.v" "" { Text "E:/FPGA/puart2/clk_gen.v" 94 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1765447224856 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/clk_gen_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/clk_gen_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_gen_altpll " "Found entity 1: clk_gen_altpll" { } { { "db/clk_gen_altpll.v" "" { Text "E:/FPGA/puart2/db/clk_gen_altpll.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1765447224906 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765447224906 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_gen_altpll clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated " "Elaborating entity \"clk_gen_altpll\" for hierarchy \"clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "e:/quartuslite/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765447224906 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi_master_2164 spi_master_2164:u_spi_master_2164 " "Elaborating entity \"spi_master_2164\" for hierarchy \"spi_master_2164:u_spi_master_2164\"" { } { { "ddr_ctrl.v" "u_spi_master_2164" { Text "E:/FPGA/puart2/ddr_ctrl.v" 221 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765447224910 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi_master_esp32 spi_master_esp32:tranfer " "Elaborating entity \"spi_master_esp32\" for hierarchy \"spi_master_esp32:tranfer\"" { } { { "ddr_ctrl.v" "tranfer" { Text "E:/FPGA/puart2/ddr_ctrl.v" 234 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765447224911 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 spi_master_esp32.v(50) " "Verilog HDL assignment warning at spi_master_esp32.v(50): truncated value with size 32 to match size of target (4)" { } { { "spi_master_esp32.v" "" { Text "E:/FPGA/puart2/spi_master_esp32.v" 50 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1765447224912 "|ddr_ctrl|spi_master_esp32:tranfer"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_tx uart_tx:u_uart_pc " "Elaborating entity \"uart_tx\" for hierarchy \"uart_tx:u_uart_pc\"" { } { { "ddr_ctrl.v" "u_uart_pc" { Text "E:/FPGA/puart2/ddr_ctrl.v" 243 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765447224913 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 uart_tx.v(32) " "Verilog HDL assignment warning at uart_tx.v(32): truncated value with size 32 to match size of target (16)" { } { { "uart_tx.v" "" { Text "E:/FPGA/puart2/uart_tx.v" 32 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1765447224914 "|ddr_ctrl|uart_tx:u_uart_pc"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 uart_tx.v(74) " "Verilog HDL assignment warning at uart_tx.v(74): truncated value with size 32 to match size of target (4)" { } { { "uart_tx.v" "" { Text "E:/FPGA/puart2/uart_tx.v" 74 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1765447224914 "|ddr_ctrl|uart_tx:u_uart_pc"} +{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "spi_master_2164.v" "" { Text "E:/FPGA/puart2/spi_master_2164.v" 11 -1 0 } } { "uart_tx.v" "" { Text "E:/FPGA/puart2/uart_tx.v" 43 -1 0 } } { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 146 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 -1 1765447225299 ""} +{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Analysis & Synthesis" 0 -1 1765447225299 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "MOSI_ESP32 GND " "Pin \"MOSI_ESP32\" is stuck at GND" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 12 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1765447225343 "|ddr_ctrl|MOSI_ESP32"} { "Warning" "WMLS_MLS_STUCK_PIN" "cs_ESP32 VCC " "Pin \"cs_ESP32\" is stuck at VCC" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 13 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1765447225343 "|ddr_ctrl|cs_ESP32"} { "Warning" "WMLS_MLS_STUCK_PIN" "sclk_ESP32 GND " "Pin \"sclk_ESP32\" is stuck at GND" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 14 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1765447225343 "|ddr_ctrl|sclk_ESP32"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1765447225343 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1765447225397 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "6 " "6 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1765447225805 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/FPGA/puart2/output_files/intan_m10.map.smsg " "Generated suppressed messages file E:/FPGA/puart2/output_files/intan_m10.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765447225846 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "1 0 1 0 0 " "Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1765447225934 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765447225934 ""} +{ "Warning" "WCUT_PLL_MULT_DIV_SPECIFIED_CLOCK_NOT_CONNECTED" "clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|pll1 CLK\[1\] clk1_multiply_by clk1_divide_by " "PLL \"clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|pll1\" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK\[1\] is not connected" { } { { "db/clk_gen_altpll.v" "" { Text "E:/FPGA/puart2/db/clk_gen_altpll.v" 43 -1 0 } } { "altpll.tdf" "" { Text "e:/quartuslite/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "clk_gen.v" "" { Text "E:/FPGA/puart2/clk_gen.v" 94 0 0 } } { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 204 0 0 } } } 0 15899 "PLL \"%1!s!\" has parameters %3!s! and %4!s! specified but port %2!s! is not connected" 0 0 "Analysis & Synthesis" 0 -1 1765447225956 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "213 " "Implemented 213 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Implemented 4 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1765447225973 ""} { "Info" "ICUT_CUT_TM_OPINS" "9 " "Implemented 9 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1765447225973 ""} { "Info" "ICUT_CUT_TM_LCELLS" "199 " "Implemented 199 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1765447225973 ""} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Implemented 1 PLLs" { } { } 0 21065 "Implemented %1!d! PLLs" 0 0 "Design Software" 0 -1 1765447225973 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1765447225973 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4766 " "Peak virtual memory: 4766 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1765447225990 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 11 18:00:25 2025 " "Processing ended: Thu Dec 11 18:00:25 2025" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1765447225990 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1765447225990 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1765447225990 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1765447225990 ""} diff --git a/puart2/db/intan_m10.map.rdb b/puart2/db/intan_m10.map.rdb new file mode 100644 index 0000000..a2d9b7f Binary files /dev/null and b/puart2/db/intan_m10.map.rdb differ diff --git a/puart2/db/intan_m10.map_bb.cdb b/puart2/db/intan_m10.map_bb.cdb new file mode 100644 index 0000000..5f665fe Binary files /dev/null and b/puart2/db/intan_m10.map_bb.cdb differ diff --git a/puart2/db/intan_m10.map_bb.hdb b/puart2/db/intan_m10.map_bb.hdb new file mode 100644 index 0000000..cb28809 Binary files /dev/null and b/puart2/db/intan_m10.map_bb.hdb differ diff --git a/puart2/db/intan_m10.map_bb.logdb b/puart2/db/intan_m10.map_bb.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/puart2/db/intan_m10.map_bb.logdb @@ -0,0 +1 @@ +v1 diff --git a/puart2/db/intan_m10.npp.qmsg b/puart2/db/intan_m10.npp.qmsg new file mode 100644 index 0000000..aaaf526 --- /dev/null +++ b/puart2/db/intan_m10.npp.qmsg @@ -0,0 +1,4 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1714359168898 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus Prime " "Running Quartus Prime Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1714359168903 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 29 10:52:48 2024 " "Processing started: Mon Apr 29 10:52:48 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1714359168903 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1714359168903 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_npp intan_m10 -c intan_m10 --netlist_type=sgate " "Command: quartus_npp intan_m10 -c intan_m10 --netlist_type=sgate" { } { } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1714359168904 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 0 s Quartus Prime " "Quartus Prime Netlist Viewers Preprocess was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4538 " "Peak virtual memory: 4538 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1714359169080 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 29 10:52:49 2024 " "Processing ended: Mon Apr 29 10:52:49 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1714359169080 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1714359169080 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1714359169080 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1714359169080 ""} diff --git a/puart2/db/intan_m10.pow.qmsg b/puart2/db/intan_m10.pow.qmsg new file mode 100644 index 0000000..945f8bf --- /dev/null +++ b/puart2/db/intan_m10.pow.qmsg @@ -0,0 +1,19 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1765447235218 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Power Analyzer Quartus Prime " "Running Quartus Prime Power Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1765447235229 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 11 18:00:35 2025 " "Processing started: Thu Dec 11 18:00:35 2025" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1765447235229 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Power Analyzer" 0 -1 1765447235229 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_pow --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10 " "Command: quartus_pow --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10" { } { } 0 0 "Command: %1!s!" 0 0 "Power Analyzer" 0 -1 1765447235229 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Power Analyzer" 0 -1 1765447235534 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Power Analyzer" 0 -1 1765447235534 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "intan_m10.sdc " "Synopsys Design Constraints File file not found: 'intan_m10.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Power Analyzer" 0 -1 1765447235796 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "sys_clk " "Node: sys_clk was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi_master_2164:u_spi_master_2164\|cnt\[1\] sys_clk " "Register spi_master_2164:u_spi_master_2164\|cnt\[1\] is being clocked by sys_clk" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1765447235797 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Power Analyzer" 0 -1 1765447235797 "|ddr_ctrl|sys_clk"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi_master_2164:u_spi_master_2164\|cs_n " "Node: spi_master_2164:u_spi_master_2164\|cs_n was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register state\[2\] spi_master_2164:u_spi_master_2164\|cs_n " "Register state\[2\] is being clocked by spi_master_2164:u_spi_master_2164\|cs_n" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1765447235797 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Power Analyzer" 0 -1 1765447235797 "|ddr_ctrl|spi_master_2164:u_spi_master_2164|cs_n"} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Power Analyzer" 0 -1 1765447235798 ""} +{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Node: clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 83.333 " "Node: clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 83.333" { } { } 0 332056 "%1!s!" 0 0 "Design Software" 0 -1 1765447235799 ""} } { } 0 332056 "%1!s!" 0 0 "Power Analyzer" 0 -1 1765447235799 ""} +{ "Info" "IPVA_PVA_START_CALCULATION" "" "Starting Vectorless Power Activity Estimation" { } { } 0 223000 "Starting Vectorless Power Activity Estimation" 0 0 "Power Analyzer" 0 -1 1765447235803 ""} +{ "Warning" "WPUTIL_PUTIL_NO_CLK_DOMAINS_FOUND" "" "Relative toggle rates could not be calculated because no clock domain could be identified for some nodes" { } { } 0 222013 "Relative toggle rates could not be calculated because no clock domain could be identified for some nodes" 0 0 "Power Analyzer" 0 -1 1765447235804 ""} +{ "Info" "IPVA_PVA_END_CALCULATION" "" "Completed Vectorless Power Activity Estimation" { } { } 0 223001 "Completed Vectorless Power Activity Estimation" 0 0 "Power Analyzer" 0 -1 1765447235806 ""} +{ "Info" "IPATFAM_USING_ADVANCED_IO_POWER" "" "Using Advanced I/O Power to simulate I/O buffers with the specified board trace model" { } { } 0 218000 "Using Advanced I/O Power to simulate I/O buffers with the specified board trace model" 0 0 "Power Analyzer" 0 -1 1765447235961 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Power Analyzer" 0 -1 1765447235996 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Power Analyzer" 0 -1 1765447236365 ""} +{ "Info" "IPAN_AVG_TOGGLE_RATE_PER_DESIGN" "0.000 millions of transitions / sec " "Average toggle rate for this design is 0.000 millions of transitions / sec" { } { } 0 215049 "Average toggle rate for this design is %1!s!" 0 0 "Power Analyzer" 0 -1 1765447236695 ""} +{ "Info" "IPAN_PAN_TOTAL_POWER_ESTIMATION" "149.66 mW " "Total thermal power estimate for the design is 149.66 mW" { } { { "e:/quartuslite/quartus/bin64/Report_Window_01.qrpt" "" { Report "e:/quartuslite/quartus/bin64/Report_Window_01.qrpt" "Compiler" "" "" "" "" { } "PowerPlay Power Analyzer Summary" } } } 0 215031 "Total thermal power estimate for the design is %1!s!" 0 0 "Power Analyzer" 0 -1 1765447236811 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Power Analyzer 0 s 7 s Quartus Prime " "Quartus Prime Power Analyzer was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4812 " "Peak virtual memory: 4812 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1765447237015 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 11 18:00:37 2025 " "Processing ended: Thu Dec 11 18:00:37 2025" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1765447237015 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1765447237015 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1765447237015 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Power Analyzer" 0 -1 1765447237015 ""} diff --git a/puart2/db/intan_m10.pplq.rdb b/puart2/db/intan_m10.pplq.rdb new file mode 100644 index 0000000..45b9f94 Binary files /dev/null and b/puart2/db/intan_m10.pplq.rdb differ diff --git a/puart2/db/intan_m10.pre_map.cdb b/puart2/db/intan_m10.pre_map.cdb new file mode 100644 index 0000000..8b56fb6 Binary files /dev/null and b/puart2/db/intan_m10.pre_map.cdb differ diff --git a/puart2/db/intan_m10.pre_map.hdb b/puart2/db/intan_m10.pre_map.hdb new file mode 100644 index 0000000..3c0eeb0 Binary files /dev/null and b/puart2/db/intan_m10.pre_map.hdb differ diff --git a/puart2/db/intan_m10.qns b/puart2/db/intan_m10.qns new file mode 100644 index 0000000..c61216f --- /dev/null +++ b/puart2/db/intan_m10.qns @@ -0,0 +1 @@ +intan_m10/done diff --git a/puart2/db/intan_m10.qpf b/puart2/db/intan_m10.qpf new file mode 100644 index 0000000..6fb6d0f --- /dev/null +++ b/puart2/db/intan_m10.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition +# Date created = 09:52:33 September 21, 2024 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.1" +DATE = "09:52:33 September 21, 2024" + +# Revisions + +PROJECT_REVISION = "intan_m10" diff --git a/puart2/db/intan_m10.root_partition.map.reg_db.cdb b/puart2/db/intan_m10.root_partition.map.reg_db.cdb new file mode 100644 index 0000000..49af47c Binary files /dev/null and b/puart2/db/intan_m10.root_partition.map.reg_db.cdb differ diff --git a/puart2/db/intan_m10.routing.rdb b/puart2/db/intan_m10.routing.rdb new file mode 100644 index 0000000..05e7f82 Binary files /dev/null and b/puart2/db/intan_m10.routing.rdb differ diff --git a/puart2/db/intan_m10.rtlv.hdb b/puart2/db/intan_m10.rtlv.hdb new file mode 100644 index 0000000..3e9662a Binary files /dev/null and b/puart2/db/intan_m10.rtlv.hdb differ diff --git a/puart2/db/intan_m10.rtlv_sg.cdb b/puart2/db/intan_m10.rtlv_sg.cdb new file mode 100644 index 0000000..9ac3b91 Binary files /dev/null and b/puart2/db/intan_m10.rtlv_sg.cdb differ diff --git a/puart2/db/intan_m10.rtlv_sg_swap.cdb b/puart2/db/intan_m10.rtlv_sg_swap.cdb new file mode 100644 index 0000000..931b49f Binary files /dev/null and b/puart2/db/intan_m10.rtlv_sg_swap.cdb differ diff --git a/puart2/db/intan_m10.sgate.nvd b/puart2/db/intan_m10.sgate.nvd new file mode 100644 index 0000000..13408f0 Binary files /dev/null and b/puart2/db/intan_m10.sgate.nvd differ diff --git a/puart2/db/intan_m10.sgate_sm.nvd b/puart2/db/intan_m10.sgate_sm.nvd new file mode 100644 index 0000000..56144bf Binary files /dev/null and b/puart2/db/intan_m10.sgate_sm.nvd differ diff --git a/puart2/db/intan_m10.sgate_sm_bdd.nvd b/puart2/db/intan_m10.sgate_sm_bdd.nvd new file mode 100644 index 0000000..56144bf Binary files /dev/null and b/puart2/db/intan_m10.sgate_sm_bdd.nvd differ diff --git a/puart2/db/intan_m10.sld_design_entry.sci b/puart2/db/intan_m10.sld_design_entry.sci new file mode 100644 index 0000000..e2964ba Binary files /dev/null and b/puart2/db/intan_m10.sld_design_entry.sci differ diff --git a/puart2/db/intan_m10.sld_design_entry_dsc.sci b/puart2/db/intan_m10.sld_design_entry_dsc.sci new file mode 100644 index 0000000..e2964ba Binary files /dev/null and b/puart2/db/intan_m10.sld_design_entry_dsc.sci differ diff --git a/puart2/db/intan_m10.smart_action.txt b/puart2/db/intan_m10.smart_action.txt new file mode 100644 index 0000000..c8e8a13 --- /dev/null +++ b/puart2/db/intan_m10.smart_action.txt @@ -0,0 +1 @@ +DONE diff --git a/puart2/db/intan_m10.smp_dump.txt b/puart2/db/intan_m10.smp_dump.txt new file mode 100644 index 0000000..1d237d2 --- /dev/null +++ b/puart2/db/intan_m10.smp_dump.txt @@ -0,0 +1,23 @@ + +State Machine - |ddr_ctrl|state_top +Name state_top.SEND_uart state_top.SEND2 state_top.SEND1 state_top.IDLE +state_top.IDLE 0 0 0 0 +state_top.SEND1 0 0 1 1 +state_top.SEND2 0 1 0 1 +state_top.SEND_uart 1 0 0 1 + +State Machine - |ddr_ctrl|uart_tx:u_uart_pc|byte_select +Name byte_select.01 +byte_select.00 0 +byte_select.01 1 + +State Machine - |ddr_ctrl|uart_tx:u_uart_pc|tx_state +Name tx_state.0001 +tx_state.0000 0 +tx_state.0001 1 + +State Machine - |ddr_ctrl|spi_master_esp32:tranfer|state +Name state.IDLE state.DONE state.TRANSFER +state.IDLE 0 0 0 +state.TRANSFER 1 0 1 +state.DONE 1 1 0 diff --git a/puart2/db/intan_m10.sta.qmsg b/puart2/db/intan_m10.sta.qmsg new file mode 100644 index 0000000..ac2cb21 --- /dev/null +++ b/puart2/db/intan_m10.sta.qmsg @@ -0,0 +1,47 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1765447238388 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1765447238402 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 11 18:00:37 2025 " "Processing started: Thu Dec 11 18:00:37 2025" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1765447238402 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447238402 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta intan_m10 -c intan_m10 " "Command: quartus_sta intan_m10 -c intan_m10" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447238403 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #3" { } { } 0 0 "qsta_default_script.tcl version: #3" 0 0 "TimeQuest Timing Analyzer" 0 0 1765447238569 ""} +{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "4 " "Parallel compilation is enabled and will use up to 4 processors" { } { } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447238960 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447238999 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447238999 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "intan_m10.sdc " "Synopsys Design Constraints File file not found: 'intan_m10.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447239163 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "generated clocks \"derive_pll_clocks -create_base_clocks\" " "No user constrained generated clocks found in the design. Calling \"derive_pll_clocks -create_base_clocks\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447239163 ""} +{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_clock -period 83.333 -waveform \{0.000 41.666\} -name sys_clk sys_clk " "create_clock -period 83.333 -waveform \{0.000 41.666\} -name sys_clk sys_clk" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1765447239165 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 625 -multiply_by 6 -duty_cycle 50.00 -name \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 625 -multiply_by 6 -duty_cycle 50.00 -name \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1765447239165 ""} } { } 0 332110 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447239165 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447239165 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name spi_master_2164:u_spi_master_2164\|cs_n spi_master_2164:u_spi_master_2164\|cs_n " "create_clock -period 1.000 -name spi_master_2164:u_spi_master_2164\|cs_n spi_master_2164:u_spi_master_2164\|cs_n" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1765447239165 ""} } { } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447239165 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447239168 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447239168 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1765447239169 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1765447239178 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "TimeQuest Timing Analyzer" 0 0 1765447239184 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447239186 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -6.744 " "Worst-case setup slack is -6.744" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447239196 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447239196 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.744 -6.744 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -6.744 -6.744 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447239196 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.642 -7.912 spi_master_2164:u_spi_master_2164\|cs_n " " -0.642 -7.912 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447239196 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447239196 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.362 " "Worst-case hold slack is 0.362" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447239203 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447239203 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.362 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.362 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447239203 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.363 0.000 spi_master_2164:u_spi_master_2164\|cs_n " " 0.363 0.000 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447239203 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447239203 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447239216 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447239218 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.487 " "Worst-case minimum pulse width slack is -1.487" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447239265 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447239265 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.487 -46.097 spi_master_2164:u_spi_master_2164\|cs_n " " -1.487 -46.097 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447239265 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 41.554 0.000 sys_clk " " 41.554 0.000 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447239265 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4339.989 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4339.989 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447239265 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447239265 ""} +{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 1 synchronizer chains. " "Report Metastability: Found 1 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447239274 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 1 " "Number of Synchronizer Chains Found: 1" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447239274 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447239274 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447239274 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 17358.585 ns " "Worst Case Available Settling Time: 17358.585 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447239274 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447239274 ""} } { } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447239274 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1765447239279 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447239308 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447239885 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447240002 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447240008 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -6.215 " "Worst-case setup slack is -6.215" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240020 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240020 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.215 -6.215 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -6.215 -6.215 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240020 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.556 -5.863 spi_master_2164:u_spi_master_2164\|cs_n " " -0.556 -5.863 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240020 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447240020 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.324 " "Worst-case hold slack is 0.324" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240025 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240025 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.324 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.324 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240025 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.325 0.000 spi_master_2164:u_spi_master_2164\|cs_n " " 0.325 0.000 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240025 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447240025 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447240038 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447240046 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.487 " "Worst-case minimum pulse width slack is -1.487" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240054 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240054 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.487 -46.097 spi_master_2164:u_spi_master_2164\|cs_n " " -1.487 -46.097 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240054 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 41.555 0.000 sys_clk " " 41.555 0.000 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240054 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4340.000 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4340.000 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240054 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447240054 ""} +{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 1 synchronizer chains. " "Report Metastability: Found 1 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447240065 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 1 " "Number of Synchronizer Chains Found: 1" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447240065 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447240065 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447240065 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 17358.726 ns " "Worst Case Available Settling Time: 17358.726 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447240065 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447240065 ""} } { } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447240065 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1765447240069 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447240261 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447240262 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.312 " "Worst-case setup slack is -2.312" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240264 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240264 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.312 -2.312 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -2.312 -2.312 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240264 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.304 0.000 spi_master_2164:u_spi_master_2164\|cs_n " " 0.304 0.000 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240264 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447240264 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.151 " "Worst-case hold slack is 0.151" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240276 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240276 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.151 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.151 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240276 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.151 0.000 spi_master_2164:u_spi_master_2164\|cs_n " " 0.151 0.000 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240276 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447240276 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447240278 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447240297 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.000 " "Worst-case minimum pulse width slack is -1.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240299 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240299 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.000 -31.000 spi_master_2164:u_spi_master_2164\|cs_n " " -1.000 -31.000 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240299 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 41.180 0.000 sys_clk " " 41.180 0.000 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240299 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4340.041 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4340.041 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765447240299 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447240299 ""} +{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 1 synchronizer chains. " "Report Metastability: Found 1 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447240306 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 1 " "Number of Synchronizer Chains Found: 1" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447240306 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447240306 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447240306 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 17359.966 ns " "Worst Case Available Settling Time: 17359.966 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447240306 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765447240306 ""} } { } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447240306 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447241137 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447241138 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4784 " "Peak virtual memory: 4784 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1765447241203 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 11 18:00:41 2025 " "Processing ended: Thu Dec 11 18:00:41 2025" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1765447241203 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1765447241203 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1765447241203 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765447241203 ""} diff --git a/puart2/db/intan_m10.sta.rdb b/puart2/db/intan_m10.sta.rdb new file mode 100644 index 0000000..296f94a Binary files /dev/null and b/puart2/db/intan_m10.sta.rdb differ diff --git a/puart2/db/intan_m10.sta_cmp.8_slow_1200mv_85c.tdb b/puart2/db/intan_m10.sta_cmp.8_slow_1200mv_85c.tdb new file mode 100644 index 0000000..e0127c2 Binary files /dev/null and b/puart2/db/intan_m10.sta_cmp.8_slow_1200mv_85c.tdb differ diff --git a/puart2/db/intan_m10.tis_db_list.ddb b/puart2/db/intan_m10.tis_db_list.ddb new file mode 100644 index 0000000..0e78876 Binary files /dev/null and b/puart2/db/intan_m10.tis_db_list.ddb differ diff --git a/puart2/db/intan_m10.tiscmp.fast_1200mv_0c.ddb b/puart2/db/intan_m10.tiscmp.fast_1200mv_0c.ddb new file mode 100644 index 0000000..b7de860 Binary files /dev/null and b/puart2/db/intan_m10.tiscmp.fast_1200mv_0c.ddb differ diff --git a/puart2/db/intan_m10.tiscmp.fastest_slow_1200mv_0c.ddb b/puart2/db/intan_m10.tiscmp.fastest_slow_1200mv_0c.ddb new file mode 100644 index 0000000..5847c70 Binary files /dev/null and b/puart2/db/intan_m10.tiscmp.fastest_slow_1200mv_0c.ddb differ diff --git a/puart2/db/intan_m10.tiscmp.fastest_slow_1200mv_85c.ddb b/puart2/db/intan_m10.tiscmp.fastest_slow_1200mv_85c.ddb new file mode 100644 index 0000000..bdc7b83 Binary files /dev/null and b/puart2/db/intan_m10.tiscmp.fastest_slow_1200mv_85c.ddb differ diff --git a/puart2/db/intan_m10.tiscmp.slow_1200mv_0c.ddb b/puart2/db/intan_m10.tiscmp.slow_1200mv_0c.ddb new file mode 100644 index 0000000..e3b0a3c Binary files /dev/null and b/puart2/db/intan_m10.tiscmp.slow_1200mv_0c.ddb differ diff --git a/puart2/db/intan_m10.tiscmp.slow_1200mv_85c.ddb b/puart2/db/intan_m10.tiscmp.slow_1200mv_85c.ddb new file mode 100644 index 0000000..db2f7a2 Binary files /dev/null and b/puart2/db/intan_m10.tiscmp.slow_1200mv_85c.ddb differ diff --git a/puart2/db/intan_m10.tmw_info b/puart2/db/intan_m10.tmw_info new file mode 100644 index 0000000..e08c75b --- /dev/null +++ b/puart2/db/intan_m10.tmw_info @@ -0,0 +1,6 @@ +start_full_compilation:s:00:00:26 +start_analysis_synthesis:s:00:00:11-start_full_compilation +start_analysis_elaboration:s-start_full_compilation +start_fitter:s:00:00:06-start_full_compilation +start_assembler:s:00:00:02-start_full_compilation +start_timing_analyzer:s:00:00:04-start_full_compilation diff --git a/puart2/db/intan_m10.vpr.ammdb b/puart2/db/intan_m10.vpr.ammdb new file mode 100644 index 0000000..d937fc8 Binary files /dev/null and b/puart2/db/intan_m10.vpr.ammdb differ diff --git a/puart2/db/intan_m10.zippleback_io_sim_cache.ff_0c_fast.hsd b/puart2/db/intan_m10.zippleback_io_sim_cache.ff_0c_fast.hsd new file mode 100644 index 0000000..e2e79d0 Binary files /dev/null and b/puart2/db/intan_m10.zippleback_io_sim_cache.ff_0c_fast.hsd differ diff --git a/puart2/db/intan_m10.zippleback_io_sim_cache.ss_0c_slow.hsd b/puart2/db/intan_m10.zippleback_io_sim_cache.ss_0c_slow.hsd new file mode 100644 index 0000000..9062db0 Binary files /dev/null and b/puart2/db/intan_m10.zippleback_io_sim_cache.ss_0c_slow.hsd differ diff --git a/puart2/db/intan_m10.zippleback_io_sim_cache.ss_85c_slow.hsd b/puart2/db/intan_m10.zippleback_io_sim_cache.ss_85c_slow.hsd new file mode 100644 index 0000000..a531000 Binary files /dev/null and b/puart2/db/intan_m10.zippleback_io_sim_cache.ss_85c_slow.hsd differ diff --git a/puart2/db/intan_m10.zippleback_io_sim_cache.tt_85c_nom.hsd b/puart2/db/intan_m10.zippleback_io_sim_cache.tt_85c_nom.hsd new file mode 100644 index 0000000..5973c08 Binary files /dev/null and b/puart2/db/intan_m10.zippleback_io_sim_cache.tt_85c_nom.hsd differ diff --git a/puart2/db/intan_m10_partition_pins.json b/puart2/db/intan_m10_partition_pins.json new file mode 100644 index 0000000..19eeb35 --- /dev/null +++ b/puart2/db/intan_m10_partition_pins.json @@ -0,0 +1,45 @@ +{ + "partitions" : [ + { + "name" : "Top", + "pins" : [ + { + "name" : "mosi", + "strict" : false + }, + { + "name" : "cs_n", + "strict" : false + }, + { + "name" : "sclk", + "strict" : false + }, + { + "name" : "tx", + "strict" : false + }, + { + "name" : "test_flag_led", + "strict" : false + }, + { + "name" : "convert_flag_led", + "strict" : false + }, + { + "name" : "test_flag", + "strict" : false + }, + { + "name" : "rst_n", + "strict" : false + }, + { + "name" : "miso", + "strict" : false + } + ] + } + ] +} \ No newline at end of file diff --git a/puart2/db/prev_cmp_intan_m10.qmsg b/puart2/db/prev_cmp_intan_m10.qmsg new file mode 100644 index 0000000..a1e7712 --- /dev/null +++ b/puart2/db/prev_cmp_intan_m10.qmsg @@ -0,0 +1,171 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1765446240614 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1765446240623 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 11 17:44:00 2025 " "Processing started: Thu Dec 11 17:44:00 2025" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1765446240623 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765446240623 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off intan_m10 -c intan_m10 " "Command: quartus_map --read_settings_files=on --write_settings_files=off intan_m10 -c intan_m10" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765446240623 ""} +{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "4 " "Parallel compilation is enabled and will use up to 4 processors" { } { } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Analysis & Synthesis" 0 -1 1765446241010 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spi_master_2164.v 1 1 " "Found 1 design units, including 1 entities, in source file spi_master_2164.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi_master_2164 " "Found entity 1: spi_master_2164" { } { { "spi_master_2164.v" "" { Text "E:/FPGA/puart2/spi_master_2164.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1765446249927 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765446249927 ""} +{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "ddr_ctrl.v(151) " "Verilog HDL information at ddr_ctrl.v(151): always construct contains both blocking and non-blocking assignments" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 151 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1765446249930 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr_ctrl.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr_ctrl.v" { { "Info" "ISGN_ENTITY_NAME" "1 ddr_ctrl " "Found entity 1: ddr_ctrl" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1765446249930 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765446249930 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clk_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file clk_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_gen " "Found entity 1: clk_gen" { } { { "clk_gen.v" "" { Text "E:/FPGA/puart2/clk_gen.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1765446249933 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765446249933 ""} +{ "Warning" "WSGN_FILE_IS_MISSING" "../../20240625.v " "Can't analyze file -- file ../../20240625.v is missing" { } { } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Analysis & Synthesis" 0 -1 1765446249936 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "done DONE spi_master_esp32.v(6) " "Verilog HDL Declaration information at spi_master_esp32.v(6): object \"done\" differs only in case from object \"DONE\" in the same scope" { } { { "spi_master_esp32.v" "" { Text "E:/FPGA/puart2/spi_master_esp32.v" 6 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1765446249939 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spi_master_esp32.v 1 1 " "Found 1 design units, including 1 entities, in source file spi_master_esp32.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi_master_esp32 " "Found entity 1: spi_master_esp32" { } { { "spi_master_esp32.v" "" { Text "E:/FPGA/puart2/spi_master_esp32.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1765446249939 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765446249939 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_tx.v 1 1 " "Found 1 design units, including 1 entities, in source file uart_tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart_tx " "Found entity 1: uart_tx" { } { { "uart_tx.v" "" { Text "E:/FPGA/puart2/uart_tx.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1765446249941 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765446249941 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "ddr_ctrl " "Elaborating entity \"ddr_ctrl\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1765446249988 ""} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "received_data ddr_ctrl.v(71) " "Verilog HDL or VHDL warning at ddr_ctrl.v(71): object \"received_data\" assigned a value but never read" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 71 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1765446249989 "|ddr_ctrl"} +{ "Warning" "WVRFX_L2_VERI_ASSUMED_INCOMPLETE_CASE" "ddr_ctrl.v(153) " "Verilog HDL warning at ddr_ctrl.v(153): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 153 0 0 } } } 0 10763 "Verilog HDL warning at %1!s!: case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness" 0 0 "Analysis & Synthesis" 0 -1 1765446249990 "|ddr_ctrl"} +{ "Warning" "WVRFX_L2_VERI_FULL_CASE_DIRECTIVE_EFFECTIVE" "ddr_ctrl.v(153) " "Verilog HDL Case Statement warning at ddr_ctrl.v(153): honored full_case synthesis attribute - differences between design synthesis and simulation may occur" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 153 0 0 } } } 0 10208 "Verilog HDL Case Statement warning at %1!s!: honored full_case synthesis attribute - differences between design synthesis and simulation may occur" 0 0 "Analysis & Synthesis" 0 -1 1765446249990 "|ddr_ctrl"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_gen clk_gen:clk_gen_inst " "Elaborating entity \"clk_gen\" for hierarchy \"clk_gen:clk_gen_inst\"" { } { { "ddr_ctrl.v" "clk_gen_inst" { Text "E:/FPGA/puart2/ddr_ctrl.v" 204 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765446250014 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll clk_gen:clk_gen_inst\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"clk_gen:clk_gen_inst\|altpll:altpll_component\"" { } { { "clk_gen.v" "altpll_component" { Text "E:/FPGA/puart2/clk_gen.v" 94 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765446250066 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "clk_gen:clk_gen_inst\|altpll:altpll_component " "Elaborated megafunction instantiation \"clk_gen:clk_gen_inst\|altpll:altpll_component\"" { } { { "clk_gen.v" "" { Text "E:/FPGA/puart2/clk_gen.v" 94 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765446250068 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "clk_gen:clk_gen_inst\|altpll:altpll_component " "Instantiated megafunction \"clk_gen:clk_gen_inst\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 625 " "Parameter \"clk0_divide_by\" = \"625\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 6 " "Parameter \"clk0_multiply_by\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 625 " "Parameter \"clk1_divide_by\" = \"625\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 12 " "Parameter \"clk1_multiply_by\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 0 " "Parameter \"clk1_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 83333 " "Parameter \"inclk0_input_frequency\" = \"83333\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family MAX 10 " "Parameter \"intended_device_family\" = \"MAX 10\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=clk_gen " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=clk_gen\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_UNUSED " "Parameter \"port_locked\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Parameter \"port_clk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765446250068 ""} } { { "clk_gen.v" "" { Text "E:/FPGA/puart2/clk_gen.v" 94 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1765446250068 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/clk_gen_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/clk_gen_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_gen_altpll " "Found entity 1: clk_gen_altpll" { } { { "db/clk_gen_altpll.v" "" { Text "E:/FPGA/puart2/db/clk_gen_altpll.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1765446250125 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765446250125 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_gen_altpll clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated " "Elaborating entity \"clk_gen_altpll\" for hierarchy \"clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "e:/quartuslite/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765446250126 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi_master_2164 spi_master_2164:u_spi_master_2164 " "Elaborating entity \"spi_master_2164\" for hierarchy \"spi_master_2164:u_spi_master_2164\"" { } { { "ddr_ctrl.v" "u_spi_master_2164" { Text "E:/FPGA/puart2/ddr_ctrl.v" 221 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765446250131 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi_master_esp32 spi_master_esp32:tranfer " "Elaborating entity \"spi_master_esp32\" for hierarchy \"spi_master_esp32:tranfer\"" { } { { "ddr_ctrl.v" "tranfer" { Text "E:/FPGA/puart2/ddr_ctrl.v" 234 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765446250145 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 spi_master_esp32.v(50) " "Verilog HDL assignment warning at spi_master_esp32.v(50): truncated value with size 32 to match size of target (4)" { } { { "spi_master_esp32.v" "" { Text "E:/FPGA/puart2/spi_master_esp32.v" 50 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1765446250146 "|ddr_ctrl|spi_master_esp32:tranfer"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_tx uart_tx:u_uart_pc " "Elaborating entity \"uart_tx\" for hierarchy \"uart_tx:u_uart_pc\"" { } { { "ddr_ctrl.v" "u_uart_pc" { Text "E:/FPGA/puart2/ddr_ctrl.v" 243 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765446250148 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 uart_tx.v(32) " "Verilog HDL assignment warning at uart_tx.v(32): truncated value with size 32 to match size of target (16)" { } { { "uart_tx.v" "" { Text "E:/FPGA/puart2/uart_tx.v" 32 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1765446250149 "|ddr_ctrl|uart_tx:u_uart_pc"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 uart_tx.v(74) " "Verilog HDL assignment warning at uart_tx.v(74): truncated value with size 32 to match size of target (4)" { } { { "uart_tx.v" "" { Text "E:/FPGA/puart2/uart_tx.v" 74 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1765446250149 "|ddr_ctrl|uart_tx:u_uart_pc"} +{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "spi_master_2164.v" "" { Text "E:/FPGA/puart2/spi_master_2164.v" 11 -1 0 } } { "uart_tx.v" "" { Text "E:/FPGA/puart2/uart_tx.v" 43 -1 0 } } { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 146 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 -1 1765446250579 ""} +{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Analysis & Synthesis" 0 -1 1765446250579 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "MOSI_ESP32 GND " "Pin \"MOSI_ESP32\" is stuck at GND" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 12 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1765446250623 "|ddr_ctrl|MOSI_ESP32"} { "Warning" "WMLS_MLS_STUCK_PIN" "cs_ESP32 VCC " "Pin \"cs_ESP32\" is stuck at VCC" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 13 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1765446250623 "|ddr_ctrl|cs_ESP32"} { "Warning" "WMLS_MLS_STUCK_PIN" "sclk_ESP32 GND " "Pin \"sclk_ESP32\" is stuck at GND" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 14 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1765446250623 "|ddr_ctrl|sclk_ESP32"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1765446250623 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1765446250676 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "6 " "6 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1765446251141 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/FPGA/puart2/output_files/intan_m10.map.smsg " "Generated suppressed messages file E:/FPGA/puart2/output_files/intan_m10.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765446251182 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "1 0 1 0 0 " "Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1765446251268 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765446251268 ""} +{ "Warning" "WCUT_PLL_MULT_DIV_SPECIFIED_CLOCK_NOT_CONNECTED" "clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|pll1 CLK\[1\] clk1_multiply_by clk1_divide_by " "PLL \"clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|pll1\" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK\[1\] is not connected" { } { { "db/clk_gen_altpll.v" "" { Text "E:/FPGA/puart2/db/clk_gen_altpll.v" 43 -1 0 } } { "altpll.tdf" "" { Text "e:/quartuslite/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "clk_gen.v" "" { Text "E:/FPGA/puart2/clk_gen.v" 94 0 0 } } { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 204 0 0 } } } 0 15899 "PLL \"%1!s!\" has parameters %3!s! and %4!s! specified but port %2!s! is not connected" 0 0 "Analysis & Synthesis" 0 -1 1765446251300 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "214 " "Implemented 214 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Implemented 4 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1765446251316 ""} { "Info" "ICUT_CUT_TM_OPINS" "9 " "Implemented 9 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1765446251316 ""} { "Info" "ICUT_CUT_TM_LCELLS" "200 " "Implemented 200 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1765446251316 ""} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Implemented 1 PLLs" { } { } 0 21065 "Implemented %1!d! PLLs" 0 0 "Design Software" 0 -1 1765446251316 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1765446251316 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4766 " "Peak virtual memory: 4766 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1765446251330 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 11 17:44:11 2025 " "Processing ended: Thu Dec 11 17:44:11 2025" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1765446251330 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1765446251330 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1765446251330 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1765446251330 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1765446252624 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1765446252634 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 11 17:44:12 2025 " "Processing started: Thu Dec 11 17:44:12 2025" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1765446252634 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1765446252634 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1765446252634 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #3" { } { } 0 0 "qfit2_default_script.tcl version: #3" 0 0 "Fitter" 0 0 1765446252760 ""} +{ "Info" "0" "" "Project = intan_m10" { } { } 0 0 "Project = intan_m10" 0 0 "Fitter" 0 0 1765446252760 ""} +{ "Info" "0" "" "Revision = intan_m10" { } { } 0 0 "Revision = intan_m10" 0 0 "Fitter" 0 0 1765446252760 ""} +{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "4 " "Parallel compilation is enabled and will use up to 4 processors" { } { } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Fitter" 0 -1 1765446252850 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "intan_m10 10M08SAM153C8G " "Selected device 10M08SAM153C8G for design \"intan_m10\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1765446252857 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1765446252891 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1765446252891 ""} +{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|pll1 MAX 10 PLL " "Implemented PLL \"clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|pll1\" as MAX 10 PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] 6 625 0 0 " "Implementing clock multiplication of 6, clock division of 625, and phase shift of 0 degrees (0 ps) for clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/clk_gen_altpll.v" "" { Text "E:/FPGA/puart2/db/clk_gen_altpll.v" 43 -1 0 } } { "" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 124 14177 15141 0 0 "" 0 "" "" } } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Design Software" 0 -1 1765446252935 ""} } { { "db/clk_gen_altpll.v" "" { Text "E:/FPGA/puart2/db/clk_gen_altpll.v" 43 -1 0 } } { "" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 124 14177 15141 0 0 "" 0 "" "" } } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1765446252935 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1765446252980 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1765446252989 ""} +{ "Critical Warning" "WFCUDA_FCUDA_SPS_DEVICE_POWER_LIMITATION" "" "Review the Power Analyzer report file (.pow.rpt) to ensure your design is within the maximum power utilization limit of the single power-supply target device and to avoid functional failures." { } { } 1 16562 "Review the Power Analyzer report file (.pow.rpt) to ensure your design is within the maximum power utilization limit of the single power-supply target device and to avoid functional failures." 0 0 "Fitter" 0 -1 1765446253124 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M08SAM153C8GES " "Device 10M08SAM153C8GES is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1765446253135 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M04SAM153C8G " "Device 10M04SAM153C8G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1765446253135 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1765446253135 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "8 " "Fitter converted 8 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TMS~ G1 " "Pin ~ALTERA_TMS~ is reserved at location G1" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { ~ALTERA_TMS~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 395 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765446253137 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TCK~ J1 " "Pin ~ALTERA_TCK~ is reserved at location J1" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { ~ALTERA_TCK~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 397 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765446253137 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDI~ H5 " "Pin ~ALTERA_TDI~ is reserved at location H5" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDI~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 399 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765446253137 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDO~ H4 " "Pin ~ALTERA_TDO~ is reserved at location H4" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDO~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 401 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765446253137 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONFIG_SEL~ D8 " "Pin ~ALTERA_CONFIG_SEL~ is reserved at location D8" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONFIG_SEL~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 403 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765446253137 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCONFIG~ E8 " "Pin ~ALTERA_nCONFIG~ is reserved at location E8" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCONFIG~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 405 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765446253137 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nSTATUS~ D6 " "Pin ~ALTERA_nSTATUS~ is reserved at location D6" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { ~ALTERA_nSTATUS~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 407 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765446253137 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONF_DONE~ E6 " "Pin ~ALTERA_CONF_DONE~ is reserved at location E6" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONF_DONE~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 409 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765446253137 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1765446253137 ""} +{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" { } { } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1765446253137 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1765446253137 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1765446253137 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1765446253137 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1765446253138 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "intan_m10.sdc " "Synopsys Design Constraints File file not found: 'intan_m10.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1765446253556 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "generated clocks " "No user constrained generated clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1765446253557 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1765446253559 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1765446253564 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1765446253565 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1765446253566 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C1 of PLL_1) " "Automatically promoted node clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C1 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1765446253584 ""} } { { "db/clk_gen_altpll.v" "" { Text "E:/FPGA/puart2/db/clk_gen_altpll.v" 77 -1 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 124 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1765446253584 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "spi_master_2164:u_spi_master_2164\|cs_n " "Automatically promoted node spi_master_2164:u_spi_master_2164\|cs_n " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1765446253584 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "cs_n~output " "Destination node cs_n~output" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 9 0 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 376 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1765446253584 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1765446253584 ""} } { { "spi_master_2164.v" "" { Text "E:/FPGA/puart2/spi_master_2164.v" 11 -1 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 119 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1765446253584 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1765446253889 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1765446253889 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1765446253889 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1765446253890 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1765446253891 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1765446253891 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1765446253891 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1765446253891 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1765446253903 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1765446253904 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1765446253904 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1765446253924 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1765446253927 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1765446254347 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1765446254389 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1765446254398 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1765446254811 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1765446254811 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1765446255161 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X21_Y0 X31_Y12 " "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X21_Y0 to location X31_Y12" { } { { "loc" "" { Generic "E:/FPGA/puart2/" { { 1 { 0 "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X21_Y0 to location X31_Y12"} { { 12 { 0 ""} 21 0 11 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1765446255483 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1765446255483 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1765446255772 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1765446255772 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1765446255774 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.15 " "Total time spent on timing analysis during the Fitter is 0.15 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1765446255931 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1765446255937 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1765446256126 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1765446256126 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1765446256415 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1765446256839 ""} +{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "4 MAX 10 " "4 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing MAX 10 Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "test_flag 3.3-V LVCMOS J12 " "Pin test_flag uses I/O standard 3.3-V LVCMOS at J12" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { test_flag } } } { "e:/quartuslite/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/quartuslite/quartus/bin64/Assignment Editor.qase" 1 { { 0 "test_flag" } } } } { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 4 0 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 11 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1765446256961 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "rst_n 3.3-V LVCMOS J14 " "Pin rst_n uses I/O standard 3.3-V LVCMOS at J14" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { rst_n } } } { "e:/quartuslite/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/quartuslite/quartus/bin64/Assignment Editor.qase" 1 { { 0 "rst_n" } } } } { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 3 0 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 10 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1765446256961 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "sys_clk 3.3-V LVCMOS J5 " "Pin sys_clk uses I/O standard 3.3-V LVCMOS at J5" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { sys_clk } } } { "e:/quartuslite/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/quartuslite/quartus/bin64/Assignment Editor.qase" 1 { { 0 "sys_clk" } } } } { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 2 0 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 9 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1765446256961 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "miso 3.3-V LVCMOS P4 " "Pin miso uses I/O standard 3.3-V LVCMOS at P4" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { miso } } } { "e:/quartuslite/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/quartuslite/quartus/bin64/Assignment Editor.qase" 1 { { 0 "miso" } } } } { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 7 0 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 12 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1765446256961 ""} } { } 0 169177 "%1!d! pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1765446256961 ""} +{ "Warning" "WFIOMGR_INCONSISTENT_VCCIO_ACROSS_MULTIPLE_BANKS_OF_CONFIGURAION_PINS" "2 Internal Configuration 2 " "Inconsistent VCCIO across multiple banks of configuration pins. The configuration pins are contained in 2 banks in 'Internal Configuration' configuration scheme and there are 2 different VCCIOs." { } { } 0 169202 "Inconsistent VCCIO across multiple banks of configuration pins. The configuration pins are contained in %1!d! banks in '%2!s!' configuration scheme and there are %3!d! different VCCIOs." 0 0 "Fitter" 0 -1 1765446256962 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/FPGA/puart2/output_files/intan_m10.fit.smsg " "Generated suppressed messages file E:/FPGA/puart2/output_files/intan_m10.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1765446257001 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5550 " "Peak virtual memory: 5550 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1765446257348 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 11 17:44:17 2025 " "Processing ended: Thu Dec 11 17:44:17 2025" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1765446257348 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1765446257348 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1765446257348 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1765446257348 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1765446258410 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1765446258420 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 11 17:44:18 2025 " "Processing started: Thu Dec 11 17:44:18 2025" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1765446258420 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1765446258420 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1765446258420 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1765446259036 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1765446259063 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4669 " "Peak virtual memory: 4669 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1765446259316 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 11 17:44:19 2025 " "Processing ended: Thu Dec 11 17:44:19 2025" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1765446259316 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1765446259316 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1765446259316 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1765446259316 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1765446260258 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Power Analyzer Quartus Prime " "Running Quartus Prime Power Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1765446260267 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 11 17:44:20 2025 " "Processing started: Thu Dec 11 17:44:20 2025" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1765446260267 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Power Analyzer" 0 -1 1765446260267 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_pow --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10 " "Command: quartus_pow --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10" { } { } 0 0 "Command: %1!s!" 0 0 "Power Analyzer" 0 -1 1765446260267 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Power Analyzer" 0 -1 1765446260555 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Power Analyzer" 0 -1 1765446260555 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "intan_m10.sdc " "Synopsys Design Constraints File file not found: 'intan_m10.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Power Analyzer" 0 -1 1765446260801 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "sys_clk " "Node: sys_clk was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi_master_2164:u_spi_master_2164\|cnt\[1\] sys_clk " "Register spi_master_2164:u_spi_master_2164\|cnt\[1\] is being clocked by sys_clk" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1765446260802 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Power Analyzer" 0 -1 1765446260802 "|ddr_ctrl|sys_clk"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi_master_2164:u_spi_master_2164\|cs_n " "Node: spi_master_2164:u_spi_master_2164\|cs_n was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register state\[25\] spi_master_2164:u_spi_master_2164\|cs_n " "Register state\[25\] is being clocked by spi_master_2164:u_spi_master_2164\|cs_n" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1765446260802 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Power Analyzer" 0 -1 1765446260802 "|ddr_ctrl|spi_master_2164:u_spi_master_2164|cs_n"} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Power Analyzer" 0 -1 1765446260802 ""} +{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Node: clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 83.333 " "Node: clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 83.333" { } { } 0 332056 "%1!s!" 0 0 "Design Software" 0 -1 1765446260804 ""} } { } 0 332056 "%1!s!" 0 0 "Power Analyzer" 0 -1 1765446260804 ""} +{ "Info" "IPVA_PVA_START_CALCULATION" "" "Starting Vectorless Power Activity Estimation" { } { } 0 223000 "Starting Vectorless Power Activity Estimation" 0 0 "Power Analyzer" 0 -1 1765446260807 ""} +{ "Warning" "WPUTIL_PUTIL_NO_CLK_DOMAINS_FOUND" "" "Relative toggle rates could not be calculated because no clock domain could be identified for some nodes" { } { } 0 222013 "Relative toggle rates could not be calculated because no clock domain could be identified for some nodes" 0 0 "Power Analyzer" 0 -1 1765446260808 ""} +{ "Info" "IPVA_PVA_END_CALCULATION" "" "Completed Vectorless Power Activity Estimation" { } { } 0 223001 "Completed Vectorless Power Activity Estimation" 0 0 "Power Analyzer" 0 -1 1765446260810 ""} +{ "Info" "IPATFAM_USING_ADVANCED_IO_POWER" "" "Using Advanced I/O Power to simulate I/O buffers with the specified board trace model" { } { } 0 218000 "Using Advanced I/O Power to simulate I/O buffers with the specified board trace model" 0 0 "Power Analyzer" 0 -1 1765446260962 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Power Analyzer" 0 -1 1765446260995 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Power Analyzer" 0 -1 1765446261317 ""} +{ "Info" "IPAN_AVG_TOGGLE_RATE_PER_DESIGN" "0.000 millions of transitions / sec " "Average toggle rate for this design is 0.000 millions of transitions / sec" { } { } 0 215049 "Average toggle rate for this design is %1!s!" 0 0 "Power Analyzer" 0 -1 1765446261536 ""} +{ "Info" "IPAN_PAN_TOTAL_POWER_ESTIMATION" "149.66 mW " "Total thermal power estimate for the design is 149.66 mW" { } { { "e:/quartuslite/quartus/bin64/Report_Window_01.qrpt" "" { Report "e:/quartuslite/quartus/bin64/Report_Window_01.qrpt" "Compiler" "" "" "" "" { } "PowerPlay Power Analyzer Summary" } } } 0 215031 "Total thermal power estimate for the design is %1!s!" 0 0 "Power Analyzer" 0 -1 1765446261639 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Power Analyzer 0 s 7 s Quartus Prime " "Quartus Prime Power Analyzer was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4810 " "Peak virtual memory: 4810 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1765446261812 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 11 17:44:21 2025 " "Processing ended: Thu Dec 11 17:44:21 2025" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1765446261812 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1765446261812 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1765446261812 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Power Analyzer" 0 -1 1765446261812 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Power Analyzer" 0 -1 1765446262993 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1765446263006 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 11 17:44:22 2025 " "Processing started: Thu Dec 11 17:44:22 2025" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1765446263006 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446263006 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta intan_m10 -c intan_m10 " "Command: quartus_sta intan_m10 -c intan_m10" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446263006 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #3" { } { } 0 0 "qsta_default_script.tcl version: #3" 0 0 "TimeQuest Timing Analyzer" 0 0 1765446263149 ""} +{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "4 " "Parallel compilation is enabled and will use up to 4 processors" { } { } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446263318 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446263349 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446263349 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "intan_m10.sdc " "Synopsys Design Constraints File file not found: 'intan_m10.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446263463 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "generated clocks \"derive_pll_clocks -create_base_clocks\" " "No user constrained generated clocks found in the design. Calling \"derive_pll_clocks -create_base_clocks\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446263463 ""} +{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_clock -period 83.333 -waveform \{0.000 41.666\} -name sys_clk sys_clk " "create_clock -period 83.333 -waveform \{0.000 41.666\} -name sys_clk sys_clk" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1765446263464 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 625 -multiply_by 6 -duty_cycle 50.00 -name \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 625 -multiply_by 6 -duty_cycle 50.00 -name \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1765446263464 ""} } { } 0 332110 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446263464 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446263464 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name spi_master_2164:u_spi_master_2164\|cs_n spi_master_2164:u_spi_master_2164\|cs_n " "create_clock -period 1.000 -name spi_master_2164:u_spi_master_2164\|cs_n spi_master_2164:u_spi_master_2164\|cs_n" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1765446263464 ""} } { } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446263464 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446263466 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446263466 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1765446263466 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1765446263472 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "TimeQuest Timing Analyzer" 0 0 1765446263476 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446263478 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -7.344 " "Worst-case setup slack is -7.344" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446263484 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446263484 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -7.344 -7.344 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -7.344 -7.344 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446263484 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.651 -6.553 spi_master_2164:u_spi_master_2164\|cs_n " " -0.651 -6.553 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446263484 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446263484 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.344 " "Worst-case hold slack is 0.344" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446263489 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446263489 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.344 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.344 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446263489 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.363 0.000 spi_master_2164:u_spi_master_2164\|cs_n " " 0.363 0.000 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446263489 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446263489 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446263497 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446263502 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.487 " "Worst-case minimum pulse width slack is -1.487" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446263508 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446263508 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.487 -46.097 spi_master_2164:u_spi_master_2164\|cs_n " " -1.487 -46.097 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446263508 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 41.554 0.000 sys_clk " " 41.554 0.000 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446263508 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4339.971 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4339.971 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446263508 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446263508 ""} +{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 1 synchronizer chains. " "Report Metastability: Found 1 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765446263515 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 1 " "Number of Synchronizer Chains Found: 1" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765446263515 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765446263515 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765446263515 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 17358.987 ns " "Worst Case Available Settling Time: 17358.987 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765446263515 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765446263515 ""} } { } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446263515 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1765446263518 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446263535 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446263863 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446263915 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446263921 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -6.784 " "Worst-case setup slack is -6.784" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446263928 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446263928 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.784 -6.784 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -6.784 -6.784 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446263928 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.559 -4.266 spi_master_2164:u_spi_master_2164\|cs_n " " -0.559 -4.266 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446263928 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446263928 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.307 " "Worst-case hold slack is 0.307" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446263931 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446263931 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.307 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.307 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446263931 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.324 0.000 spi_master_2164:u_spi_master_2164\|cs_n " " 0.324 0.000 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446263931 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446263931 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446263941 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446263943 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.487 " "Worst-case minimum pulse width slack is -1.487" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446263982 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446263982 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.487 -46.097 spi_master_2164:u_spi_master_2164\|cs_n " " -1.487 -46.097 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446263982 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 41.555 0.000 sys_clk " " 41.555 0.000 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446263982 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4339.959 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4339.959 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446263982 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446263982 ""} +{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 1 synchronizer chains. " "Report Metastability: Found 1 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765446263988 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 1 " "Number of Synchronizer Chains Found: 1" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765446263988 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765446263988 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765446263988 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 17359.116 ns " "Worst Case Available Settling Time: 17359.116 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765446263988 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765446263988 ""} } { } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446263988 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1765446263990 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446264124 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446264125 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.505 " "Worst-case setup slack is -2.505" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446264126 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446264126 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.505 -2.505 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " -2.505 -2.505 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446264126 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.294 0.000 spi_master_2164:u_spi_master_2164\|cs_n " " 0.294 0.000 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446264126 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446264126 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.144 " "Worst-case hold slack is 0.144" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446264135 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446264135 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.144 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.144 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446264135 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.151 0.000 spi_master_2164:u_spi_master_2164\|cs_n " " 0.151 0.000 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446264135 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446264135 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446264137 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446264144 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.000 " "Worst-case minimum pulse width slack is -1.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446264147 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446264147 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.000 -31.000 spi_master_2164:u_spi_master_2164\|cs_n " " -1.000 -31.000 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446264147 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 41.180 0.000 sys_clk " " 41.180 0.000 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446264147 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4340.030 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4340.030 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765446264147 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446264147 ""} +{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 1 synchronizer chains. " "Report Metastability: Found 1 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765446264153 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 1 " "Number of Synchronizer Chains Found: 1" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765446264153 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765446264153 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765446264153 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 17360.144 ns " "Worst Case Available Settling Time: 17360.144 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765446264153 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1765446264153 ""} } { } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446264153 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446264769 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446264769 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4773 " "Peak virtual memory: 4773 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1765446264817 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 11 17:44:24 2025 " "Processing ended: Thu Dec 11 17:44:24 2025" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1765446264817 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1765446264817 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1765446264817 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446264817 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 29 s " "Quartus Prime Full Compilation was successful. 0 errors, 29 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1765446265433 ""} diff --git a/puart2/ddr_ctrl.v b/puart2/ddr_ctrl.v new file mode 100644 index 0000000..99452ae --- /dev/null +++ b/puart2/ddr_ctrl.v @@ -0,0 +1,247 @@ +module ddr_ctrl( + input sys_clk, // 12M on-board oscillator + input rst_n, + input test_flag, // 1: read register, 0: start convert data + + // 2132 + input miso, + output mosi, + output cs_n, + output sclk, + //esp32 + output MOSI_ESP32, + output cs_ESP32, + output sclk_ESP32, + //uart + output wire tx, // 串行输出信号 + + + + output test_flag_led, + output convert_flag_led + + // for simulation +// output reg [25:0] state, +// output reg [25:0] next, + + //output [15:0] dout +); + + reg start1, start2,start_uart; + wire done1,done2,done_uart; + + localparam [4:0] s0 = 0, + s1 = 1, + s2 = 2, + s3 = 3, + s4 = 4, + s5 = 5, + s6 = 6, + s7 = 7, + s8 = 8, + s9 = 9, + s10 = 10, + s11 = 11, + s12 = 12, + s13 = 13, + s14 = 14, + s15 = 15, + s16 = 16, + s17 = 17, + s18 = 18, + s19 = 19, + s20 = 20, + s21 = 21, + s22 = 22, + s23 = 23, + s24 = 24, + s25 = 25, + s26 = 26, + s27 = 27, + s28 = 28, + s29 = 29, + s30 = 30; + + + reg [30:0] state, next; + + reg [15:0] din_r; + wire [15:0] din; + + reg [15:0] received_data; // 存储从从机1接收到的数据 + reg [15:0] sent_data; // 要发送到从机2的数据 + + + + assign din = din_r; + + + assign test_flag_led = test_flag; + assign convert_flag_led = ~test_flag; + + // 定义状态编码 +parameter IDLE = 2'b00, + SEND1 = 2'b01, + SEND2 = 2'b10, + SEND_uart =2'b11; + +// 定义状态变量 +reg [1:0] state_top; + + //状态机，用于控制两个SPI模块的启动 + always @(posedge clk_115200 or negedge rst_n) begin + if (!rst_n) begin + start1 <= 0; + start2 <= 0; + state_top <= IDLE; + end + else begin + case (state_top) + IDLE: begin + start1 <= 1; // 启动SPI主机1 + start2 <= 0; + state_top <= SEND1; + end + + SEND1: begin + if (done1) begin // SPI主机1完成接收 + start1 <= 0; + received_data <= dout1; // 存储接收到的数据 + sent_data <= dout1; // 将接收到的数据准备好发送 + start_uart <= 1; // 启动SPI主机2，发送数据给从机2 + state_top <= SEND_uart; + end + end + + SEND_uart: begin + if (done_uart) begin // uart完成发送 + start_uart <= 0; + //start2 <= 1; + state_top <= IDLE; + end + end + + SEND2: begin + if (done2) begin // SPI主机2完成发送 + start2 <= 0; + state_top <= IDLE; // 回到初始状态，等待下一轮传输 + end + end + + default: state_top <= IDLE; + endcase + end + end + + + + + //时序逻辑加组合逻辑完成din命令的有序发送 + + always @ (posedge cs_n or negedge rst_n) begin + if(!rst_n) begin + state <= 31'd0; + state[s0] <= 1'b1; + end + else state <= next; + end + + + always @ (*) begin + next = 31'd0; + din_r = {2'b11,6'd63,8'h00}; + case(1'b1) // synthesis parallel_case full_case + state[s0]: begin din_r<={2'b11,6'd63,8'h00}; next[s1] = 1'b1; end + state[s1]: begin din_r<={2'b11,6'd63,8'h00}; next[s2] = 1'b1; end + state[s2]: begin din_r<={2'b10,6'd0,8'hDE}; next[s3] = 1'b1; end + state[s3]: begin din_r<={2'b10,6'd1,8'h20}; next[s4] = 1'b1; end //8'h20 + state[s4]: begin din_r<={2'b10,6'd2,8'h28}; next[s5] = 1'b1; end //8'h28 + state[s5]: begin din_r<={2'b10,6'd3,8'h00}; next[s6] = 1'b1; end + state[s6]: begin din_r<={2'b10,6'd4,8'hD6}; next[s7] = 1'b1; end + state[s7]: begin din_r<={2'b10,6'd5,8'h00}; next[s8] = 1'b1; end + state[s8]: begin din_r<={2'b10,6'd6,8'h80}; next[s9] = 1'b1; end + state[s9]: begin din_r<={2'b10,6'd7,8'h00}; next[s10] = 1'b1; end + state[s10]: begin din_r<={2'b10,6'd8,8'h16}; next[s11] = 1'b1; end + state[s11]: begin din_r<={2'b10,6'd9,8'h80}; next[s12] = 1'b1; end + state[s12]: begin din_r<={2'b10,6'd10,8'h17}; next[s13] = 1'b1; end + state[s13]: begin din_r<={2'b10,6'd11,8'h80}; next[s14] = 1'b1; end + state[s14]: begin din_r<={2'b10,6'd12,8'h2C}; next[s15] = 1'b1; end + state[s15]: begin din_r<={2'b10,6'd13,8'h86}; next[s16] = 1'b1; end + state[s16]: begin din_r<={2'b10,6'd14,8'hFF}; next[s17] = 1'b1; end + state[s17]: begin din_r<={2'b10,6'd15,8'hFF}; next[s18] = 1'b1; end + state[s18]: begin din_r<={2'b10,6'd16,8'hFF}; next[s19] = 1'b1; end + state[s19]: begin din_r<={2'b10,6'd17,8'hFF}; next[s20] = 1'b1; end + state[s20]: begin din_r<={2'b01,6'd21,8'h00}; next[s21] = 1'b1; end // CALIBRATE, {01,010101,8h00} + state[s21]: begin din_r<={2'b11,6'd63,8'h00}; next[s22] = 1'b1; end // dummy 1 + state[s22]: begin din_r<={2'b11,6'd63,8'h00}; next[s23] = 1'b1; end // dummy 2 + state[s23]: begin din_r<={2'b11,6'd63,8'h00}; next[s24] = 1'b1; end // dummy 3 + state[s24]: begin din_r<={2'b11,6'd63,8'h00}; next[s25] = 1'b1; end // dummy 4 + state[s25]: begin din_r<={2'b11,6'd63,8'h00}; next[s26] = 1'b1; end // dummy 5 + state[s26]: begin din_r<={2'b11,6'd63,8'h00}; next[s27] = 1'b1; end // dummy 6 + state[s27]: begin din_r<={2'b11,6'd63,8'h00}; next[s28] = 1'b1; end // dummy 7 + state[s28]: begin din_r<={2'b11,6'd63,8'h00}; next[s29] = 1'b1; end // dummy 8 + state[s29]: begin din_r<={2'b11,6'd62,8'h00}; next[s30] = 1'b1; end // dummy 9 + state[s30]: begin + if (test_flag) begin din_r<={2'b00,6'd21,8'h00}; end // convert(3) + else begin din_r<={2'b11,6'd62,8'h00}; end // read(63) + next[s30] = 1'b1; + end + endcase + end + + + + + + + wire clk_115200; + wire clk_230400; + + clk_gen clk_gen_inst ( + .inclk0 ( sys_clk ), + .c0 ( clk_115200 ), + .c1 ( clk_230400 ) + ); + + + wire [15:0] dout1; + + spi_master_2164 u_spi_master_2164( + .sys_clk(clk_115200 ), + .rst_n(rst_n), + .din(din), + .start(start1), + .dout(dout1), + .done(done1), + .sclk(sclk), + .cs_n(cs_n), + .mosi(mosi), + .miso(miso), + .cnt() + ); + + spi_master_esp32 tranfer( + + .clk(sys_clk), + .rst_n(rst_n), + .start(start2), + .din(sent_data), + .done(done2), + .sclk(sclk_ESP32), + .mosi(MOSI_ESP32), + .cs(cs_ESP32) + + ); + + uart_tx u_uart_pc( + .clk(clk_115200), // 时钟信号 + .rst(rst_n), // 复位信号 + .tx_start(start_uart), // 开始发送信号 + .tx_data(sent_data), // 顶层输入的16位待发送数据 + .tx(tx), // 串行输出信号 + .tx_done(done_uart) // 发送完成信号 + ); + + + +endmodule diff --git a/puart2/ddr_ctrl.v.bak b/puart2/ddr_ctrl.v.bak new file mode 100644 index 0000000..e9505e9 --- /dev/null +++ b/puart2/ddr_ctrl.v.bak @@ -0,0 +1,162 @@ +module ddr_ctrl( + input sys_clk, // 12M on-board oscillator + input rst_n, + + // 2164 + input miso, + output mosi, + output cs_n, + output sclk, + + // for simulation + output reg [24:0] state, + output reg [24:0] next, + + output [31:0] dout +); + + localparam [4:0] s0 = 0, + s1 = 1, + s2 = 2, + s3 = 3, + s4 = 4, + s5 = 5, + s6 = 6, + s7 = 7, + s8 = 8, + s9 = 9, + s10 = 10, + s11 = 11, + s12 = 12, + s13 = 13, + s14 = 14, + s15 = 15, + s16 = 16, + s17 = 17, + s18 = 18, + s19 = 19, + s20 = 20, + s21 = 21, + s22 = 22, + s23 = 23, + s24 = 24; // read reg 63 + +// reg [24:0] state, next; + + reg [15:0] din_r; + wire [15:0] din; +// wire [31:0] dout; + wire done; +// reg state; +// reg [5:0] sel; +// reg [4:0] din_t; + + + assign din = din_r; + + + always @ (posedge cs_n or negedge rst_n) begin + if(!rst_n) begin + state <= 25'd0; + state[s0] <= 1'b1; + end + else state <= next; + end + + + always @ (*) begin + next = 24'd0; + din_r = {2'b11,6'd63,8'h00}; + case(1'b1) // reverse case + state[s0]: begin din_r<={2'b11,6'd63,8'h00}; next[s1] = 1'b1; end + state[s1]: begin din_r<={2'b11,6'd63,8'h00}; next[s2] = 1'b1; end + state[s2]: begin din_r<={2'b10,6'd0,8'hDE}; next[s3] = 1'b1; end + state[s3]: begin din_r<={2'b10,6'd1,8'h42}; next[s4] = 1'b1; end + state[s4]: begin din_r<={2'b10,6'd2,8'h04}; next[s5] = 1'b1; end + state[s5]: begin din_r<={2'b10,6'd3,8'h00}; next[s6] = 1'b1; end + state[s6]: begin din_r<={2'b10,6'd4,8'h80}; next[s7] = 1'b1; end + state[s7]: begin din_r<={2'b10,6'd5,8'h00}; next[s8] = 1'b1; end + state[s8]: begin din_r<={2'b10,6'd6,8'h80}; next[s9] = 1'b1; end + state[s9]: begin din_r<={2'b10,6'd7,8'h00}; next[s10] = 1'b1; end + state[s10]: begin din_r<={2'b10,6'd8,8'h16}; next[s11] = 1'b1; end + state[s11]: begin din_r<={2'b10,6'd9,8'h80}; next[s12] = 1'b1; end + state[s12]: begin din_r<={2'b10,6'd10,8'h17}; next[s13] = 1'b1; end + state[s13]: begin din_r<={2'b10,6'd11,8'h80}; next[s14] = 1'b1; end + state[s14]: begin din_r<={2'b10,6'd12,8'h2C}; next[s15] = 1'b1; end + state[s15]: begin din_r<={2'b10,6'd13,8'h86}; next[s16] = 1'b1; end + state[s16]: begin din_r<={2'b10,6'd14,8'hFF}; next[s17] = 1'b1; end + state[s17]: begin din_r<={2'b10,6'd15,8'hFF}; next[s18] = 1'b1; end + state[s18]: begin din_r<={2'b10,6'd16,8'hFF}; next[s19] = 1'b1; end + state[s19]: begin din_r<={2'b10,6'd17,8'hFF}; next[s20] = 1'b1; end + state[s20]: begin din_r<={2'b10,6'd18,8'h00}; next[s21] = 1'b1; end + state[s21]: begin din_r<={2'b10,6'd19,8'h00}; next[s22] = 1'b1; end + state[s22]: begin din_r<={2'b10,6'd20,8'h00}; next[s23] = 1'b1; end + state[s23]: begin din_r<={2'b10,6'd21,8'h00}; next[s24] = 1'b1; end + state[s24]: begin din_r<={2'b11,6'd63,8'h00}; next[s24] = 1'b1; end + endcase + end + + + spi_master_2164 u_spi_master_2164( + .sys_clk(sys_clk), + .rst_n(rst_n), + .din(din), + .dout(dout), + .done(done), + .sclk(sclk), + .cs_n(cs_n), + .mosi(mosi), + .miso(miso), + .cnt() + ); + + + +// assign din = (state)? {3'b000, din_t, 8'b00000001}:din_r; +// +// always @ (posedge cs_n or negedge rst_n) begin +// if (!rst_n) begin state <= 1'b0; sel <= 'd0; din_r <= 'd0; end +// else begin +// case(sel) +// 6'd0: din_r<={2'b11,6'd62,8'h00}; +// 6'd1: din_r<={2'b11,6'd63,8'h00}; +// 6'd2: din_r<={2'b10,6'd0,8'hDE}; +// 6'd3: din_r<={2'b10,6'd1,8'h42}; +// 6'd4: din_r<={2'b10,6'd2,8'h04}; +// 6'd5: din_r<={2'b10,6'd3,8'h00}; +// 6'd6: din_r<={2'b10,6'd4,8'h80}; +// 6'd7: din_r<={2'b10,6'd5,8'h00}; +// 6'd8: din_r<={2'b10,6'd6,8'h80}; +// 6'd9: din_r<={2'b10,6'd7,8'h00}; +// 6'd10: din_r<={2'b10,6'd8,8'h16}; +// 6'd11: din_r<={2'b10,6'd9,8'h80}; +// 6'd12: din_r<={2'b10,6'd10,8'h17}; +// 6'd13: din_r<={2'b10,6'd11,8'h80}; +// 6'd14: din_r<={2'b10,6'd12,8'h2C}; +// 6'd15: din_r<={2'b10,6'd13,8'h86}; +// 6'd16: din_r<={2'b10,6'd14,8'hFF}; +// 6'd17: din_r<={2'b10,6'd15,8'hFF}; +// 6'd18: din_r<={2'b10,6'd16,8'hFF}; +// 6'd19: din_r<={2'b10,6'd17,8'hFF}; +// 6'd20: din_r<={2'b10,6'd18,8'h00}; +// 6'd21: din_r<={2'b10,6'd19,8'h00}; +// 6'd22: din_r<={2'b10,6'd20,8'h00}; +// 6'd23: din_r<={2'b10,6'd21,8'h00}; +// default: din_r<={2'b11,6'd63,8'h00}; +// endcase +// if (sel<24) sel <= sel + 1'b1; +// else state <= 1; // no need to reset sel since we only initialize once +// end +// end +// +// +// +// always @ (posedge cs_n or negedge rst_n) begin +// if (!rst_n) din_t <= 0; +// else if (state) din_t <= din_t + 1'b1; +// else din_t <= 0; +// end + + + +endmodule diff --git a/puart2/ddr_ctrl_tb.v b/puart2/ddr_ctrl_tb.v new file mode 100644 index 0000000..e91277c --- /dev/null +++ b/puart2/ddr_ctrl_tb.v @@ -0,0 +1,66 @@ +module ddr_ctrl_tb(); + +reg sys_clk; +reg rst_n; +reg miso; + +wire mosi; +wire cs_n; +wire sclk; + +wire [24:0] state; +wire [24:0] next; +wire [31:0] dout; + + + +ddr_ctrl uut( + .sys_clk(sys_clk), + .rst_n(rst_n), + .miso(miso), + .mosi(mosi), + .cs_n(cs_n), + .sclk(sclk), + .state(state), + .next(next), + .dout(dout) +); + + + +initial +begin + rst_n = 0; + miso = 0; + #50 rst_n = 1; + #12000 $finish; +end + + + +initial begin + forever begin + #5 sys_clk = 0; + #5 sys_clk = 1; + end +end + + + +initial begin + forever begin + #50 miso = 0; + #50 miso = 1; + end +end + + +initial begin + $fsdbDumpfile("ddr_ctrl.fsdb"); + $fsdbDumpvars(); +end + + + + +endmodule diff --git a/puart2/filelist.f b/puart2/filelist.f new file mode 100644 index 0000000..95a795d --- /dev/null +++ b/puart2/filelist.f @@ -0,0 +1,3 @@ +./ddr_ctrl_tb.v +./ddr_ctrl.v +./spi_master_2164.v \ No newline at end of file diff --git a/puart2/greybox_tmp/cbx_args.txt b/puart2/greybox_tmp/cbx_args.txt new file mode 100644 index 0000000..ba166fc --- /dev/null +++ b/puart2/greybox_tmp/cbx_args.txt @@ -0,0 +1,63 @@ +BANDWIDTH_TYPE=AUTO +CLK0_DIVIDE_BY=625 +CLK0_DUTY_CYCLE=50 +CLK0_MULTIPLY_BY=6 +CLK0_PHASE_SHIFT=0 +CLK1_DIVIDE_BY=625 +CLK1_DUTY_CYCLE=50 +CLK1_MULTIPLY_BY=12 +CLK1_PHASE_SHIFT=0 +COMPENSATE_CLOCK=CLK0 +INCLK0_INPUT_FREQUENCY=83333 +INTENDED_DEVICE_FAMILY="MAX 10" +LPM_TYPE=altpll +OPERATION_MODE=NORMAL +PLL_TYPE=AUTO +PORT_ACTIVECLOCK=PORT_UNUSED +PORT_ARESET=PORT_UNUSED +PORT_CLKBAD0=PORT_UNUSED +PORT_CLKBAD1=PORT_UNUSED +PORT_CLKLOSS=PORT_UNUSED +PORT_CLKSWITCH=PORT_UNUSED +PORT_CONFIGUPDATE=PORT_UNUSED +PORT_FBIN=PORT_UNUSED +PORT_INCLK0=PORT_USED +PORT_INCLK1=PORT_UNUSED +PORT_LOCKED=PORT_UNUSED +PORT_PFDENA=PORT_UNUSED +PORT_PHASECOUNTERSELECT=PORT_UNUSED +PORT_PHASEDONE=PORT_UNUSED +PORT_PHASESTEP=PORT_UNUSED +PORT_PHASEUPDOWN=PORT_UNUSED +PORT_PLLENA=PORT_UNUSED +PORT_SCANACLR=PORT_UNUSED +PORT_SCANCLK=PORT_UNUSED +PORT_SCANCLKENA=PORT_UNUSED +PORT_SCANDATA=PORT_UNUSED +PORT_SCANDATAOUT=PORT_UNUSED +PORT_SCANDONE=PORT_UNUSED +PORT_SCANREAD=PORT_UNUSED +PORT_SCANWRITE=PORT_UNUSED +PORT_clk0=PORT_USED +PORT_clk1=PORT_USED +PORT_clk2=PORT_UNUSED +PORT_clk3=PORT_UNUSED +PORT_clk4=PORT_UNUSED +PORT_clk5=PORT_UNUSED +PORT_clkena0=PORT_UNUSED +PORT_clkena1=PORT_UNUSED +PORT_clkena2=PORT_UNUSED +PORT_clkena3=PORT_UNUSED +PORT_clkena4=PORT_UNUSED +PORT_clkena5=PORT_UNUSED +PORT_extclk0=PORT_UNUSED +PORT_extclk1=PORT_UNUSED +PORT_extclk2=PORT_UNUSED +PORT_extclk3=PORT_UNUSED +WIDTH_CLOCK=5 +DEVICE_FAMILY="MAX 10" +CBX_AUTO_BLACKBOX=ALL +inclk +inclk +clk +clk diff --git a/puart2/incremental_db/README b/puart2/incremental_db/README new file mode 100644 index 0000000..9f62dcd --- /dev/null +++ b/puart2/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/puart2/incremental_db/compiled_partitions/intan_m10.db_info b/puart2/incremental_db/compiled_partitions/intan_m10.db_info new file mode 100644 index 0000000..537335f --- /dev/null +++ b/puart2/incremental_db/compiled_partitions/intan_m10.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition +Version_Index = 453135872 +Creation_Time = Mon Apr 29 08:05:13 2024 diff --git a/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.ammdb b/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.ammdb new file mode 100644 index 0000000..ee88bd3 Binary files /dev/null and b/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.ammdb differ diff --git a/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.cdb b/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.cdb new file mode 100644 index 0000000..d7000b9 Binary files /dev/null and b/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.cdb differ diff --git a/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.dfp b/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.dfp new file mode 100644 index 0000000..b1c67d6 Binary files /dev/null and b/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.dfp differ diff --git a/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.hdb b/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.hdb new file mode 100644 index 0000000..c6fb2e7 Binary files /dev/null and b/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.hdb differ diff --git a/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.logdb b/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.logdb @@ -0,0 +1 @@ +v1 diff --git a/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.rcfdb b/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.rcfdb new file mode 100644 index 0000000..b80967a Binary files /dev/null and b/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.rcfdb differ diff --git a/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.map.cdb b/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.map.cdb new file mode 100644 index 0000000..593092d Binary files /dev/null and b/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.map.cdb differ diff --git a/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.map.dpi b/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.map.dpi new file mode 100644 index 0000000..0428e9a Binary files /dev/null and b/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.map.dpi differ diff --git a/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.map.hbdb.cdb b/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.map.hbdb.cdb new file mode 100644 index 0000000..a14916c Binary files /dev/null and b/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.map.hbdb.cdb differ diff --git a/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.map.hbdb.hb_info b/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.map.hbdb.hb_info new file mode 100644 index 0000000..84722d9 Binary files /dev/null and b/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.map.hbdb.hb_info differ diff --git a/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.map.hbdb.hdb b/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.map.hbdb.hdb new file mode 100644 index 0000000..58728fa Binary files /dev/null and b/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.map.hbdb.hdb differ diff --git a/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.map.hbdb.sig b/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.map.hbdb.sig new file mode 100644 index 0000000..299c526 --- /dev/null +++ b/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.map.hbdb.sig @@ -0,0 +1 @@ +2968de0ceaa016e7e5a4320c0e4866fa \ No newline at end of file diff --git a/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.map.hdb b/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.map.hdb new file mode 100644 index 0000000..b8715fb Binary files /dev/null and b/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.map.hdb differ diff --git a/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.map.kpt b/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.map.kpt new file mode 100644 index 0000000..7f288cf Binary files /dev/null and b/puart2/incremental_db/compiled_partitions/intan_m10.root_partition.map.kpt differ diff --git a/puart2/incremental_db/compiled_partitions/intan_m10.rrp.hdb b/puart2/incremental_db/compiled_partitions/intan_m10.rrp.hdb new file mode 100644 index 0000000..948d3ef Binary files /dev/null and b/puart2/incremental_db/compiled_partitions/intan_m10.rrp.hdb differ diff --git a/puart2/intan_m10.archive.rpt b/puart2/intan_m10.archive.rpt new file mode 100644 index 0000000..d0d4eec --- /dev/null +++ b/puart2/intan_m10.archive.rpt @@ -0,0 +1,124 @@ +Archive Project report for intan_m10 +Sat Sep 21 09:52:33 2024 +Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Archive Project Summary + 3. Archive Project Messages + 4. Files Archived + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2017 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++----------------------------------------------------------------+ +; Archive Project Summary ; ++------------------------+---------------------------------------+ +; Archive Project Status ; Successful - Sat Sep 21 09:52:33 2024 ; +; Revision Name ; intan_m10 ; +; Top-level Entity Name ; ddr_ctrl ; +; Family ; MAX 10 ; ++------------------------+---------------------------------------+ + + ++--------------------------+ +; Archive Project Messages ; ++--------------------------+ +Info: File Set 'Source control' contains: + Info: Project source and settings files + Info: Automatically detected source files +Warning: Hierarchical Platform Designer systems and custom IP components(_hw.tcl and associated files) are not archived by the Quartus Archiver +Critical Warning: Analysis & Elaboration was not run successfully. + Critical Warning: The 'Automatically detected source files' file subset will attempt to guess which files are needed. The archive file will likely be larger than required and may still be incomplete. +Warning (225003): Can't find required hierarchy file 20240625.v +Info: Parsing: spi_master_2164.v +Info: Parsing: ddr_ctrl.v +Info: Parsing: clk_gen.v +Info: Parsing: clk_gen_inst.v +Info: Parsing: clk_gen_bb.v +Info: Parsing: spi_master_esp32.v +Info: Parsing: intan_m10.v +Info: Archive will store files relative to the closest common parent directory +Info (13213): Using common directory E:/FPGA/SPItransfer/20240726/ +Info: ---------------------------------------------------------- +Info: ---------------------------------------------------------- +Info: Generated archive 'E:/FPGA/SPItransfer/20240726/uart_tx.qar' +Info: ---------------------------------------------------------- +Info: ---------------------------------------------------------- +Info: Generated report 'intan_m10.archive.rpt' +Error (23031): Evaluation of Tcl script e:/quartuslite/quartus/common/tcl/apps/qpm/qar.tcl unsuccessful +Error: Quartus Prime Shell was unsuccessful. 6 errors, 17 warnings + Error: Peak virtual memory: 4826 megabytes + Error: Processing ended: Sat Sep 21 09:52:33 2024 + Error: Elapsed time: 00:00:10 + Error: Total CPU time (on all processors): 00:00:20 + + ++------------------------------------------------------+ +; Files Archived ; ++------------------------------------------------------+ +; File Name ; ++------------------------------------------------------+ +; clk_gen.ppf ; +; clk_gen.qip ; +; clk_gen.v ; +; clk_gen_bb.v ; +; clk_gen_inst.v ; +; clkgen.ppf ; +; clkgen.qip ; +; clkgen.v ; +; clkgen_bb.v ; +; clkgen_inst.v ; +; ddr_ctrl.v ; +; ddr_ctrl_tb.v ; +; e:/quartuslite/quartus/bin64/assignment_defaults.qdf ; +; intan_m10.qpf ; +; intan_m10.qsf ; +; intan_m10.v ; +; intan_m10_assignment_defaults.qdf ; +; output_files/intan_m10.asm.rpt ; +; output_files/intan_m10.cdf ; +; output_files/intan_m10.done ; +; output_files/intan_m10.eda.rpt ; +; output_files/intan_m10.fit.rpt ; +; output_files/intan_m10.fit.smsg ; +; output_files/intan_m10.fit.summary ; +; output_files/intan_m10.flow.rpt ; +; output_files/intan_m10.jdi ; +; output_files/intan_m10.map.rpt ; +; output_files/intan_m10.map.smsg ; +; output_files/intan_m10.map.summary ; +; output_files/intan_m10.pin ; +; output_files/intan_m10.pof ; +; output_files/intan_m10.pow.rpt ; +; output_files/intan_m10.pow.summary ; +; output_files/intan_m10.sld ; +; output_files/intan_m10.sof ; +; output_files/intan_m10.sta.rpt ; +; output_files/intan_m10.sta.summary ; +; spi_master_2164.v ; +; spi_master_esp32.v ; ++------------------------------------------------------+ + + diff --git a/puart2/intan_m10.qpf b/puart2/intan_m10.qpf new file mode 100644 index 0000000..908ab5d --- /dev/null +++ b/puart2/intan_m10.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition +# Date created = 20:28:17 April 12, 2024 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.1" +DATE = "20:28:17 April 12, 2024" + +# Revisions + +PROJECT_REVISION = "intan_m10" diff --git a/puart2/intan_m10.qsf b/puart2/intan_m10.qsf new file mode 100644 index 0000000..a92a74b --- /dev/null +++ b/puart2/intan_m10.qsf @@ -0,0 +1,89 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition +# Date created = 20:28:17 April 12, 2024 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# intan_m10_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M08SAM153C8G +set_global_assignment -name TOP_LEVEL_ENTITY ddr_ctrl +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:28:17 APRIL 12, 2024" +set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %" +set_location_assignment PIN_J5 -to sys_clk +set_location_assignment PIN_P6 -to cs_n +set_location_assignment PIN_P4 -to miso +set_location_assignment PIN_L7 -to mosi +set_location_assignment PIN_J14 -to rst_n +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cs_n +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to miso +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to mosi +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to rst_n +set_location_assignment PIN_R5 -to sclk +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sclk +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sys_clk +set_location_assignment PIN_J12 -to test_flag +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to test_flag +set_location_assignment PIN_N15 -to test_flag_led +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to test_flag_led +set_location_assignment PIN_M12 -to convert_flag_led +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to convert_flag_led +set_global_assignment -name NUM_PARALLEL_PROCESSORS 4 +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_B14 -to sclk_ESP32 +set_location_assignment PIN_B13 -to cs_ESP32 +set_location_assignment PIN_A14 -to MOSI_ESP32 +set_global_assignment -name VERILOG_FILE spi_master_2164.v +set_global_assignment -name VERILOG_FILE ddr_ctrl.v +set_global_assignment -name QIP_FILE clk_gen.qip +set_global_assignment -name VERILOG_FILE ../../20240625.v +set_global_assignment -name VERILOG_FILE spi_master_esp32.v +set_global_assignment -name VERILOG_FILE uart_tx.v +set_location_assignment PIN_P8 -to tx +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to tx +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cs_ESP32 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MOSI_ESP32 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sclk_ESP32 +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/puart2/intan_m10.qws b/puart2/intan_m10.qws new file mode 100644 index 0000000..5789c4c Binary files /dev/null and b/puart2/intan_m10.qws differ diff --git a/puart2/intan_m10.v b/puart2/intan_m10.v new file mode 100644 index 0000000..b825663 --- /dev/null +++ b/puart2/intan_m10.v @@ -0,0 +1,82 @@ +module uart_tx ( + input wire clk, // 时钟信号 + input wire rst, // 复位信号 + input wire tx_start, // 开始发送信号 + input wire [15:0] tx_data, // 顶层输入的16位待发送数据 + output wire tx, // 串行输出信号 + output reg tx_done // 发送完成信号 +); + +parameter BAUD_RATE = 115200; +parameter CLOCK_FREQ = 12000000; // 12 MHz时钟 + +localparam integer BAUD_TICK = CLOCK_FREQ / BAUD_RATE; // 波特率计数，计算出每个比特的时钟周期数 + +// 波特率计数器 +reg [15:0] baud_counter; +reg [7:0] data_to_send; // 用于存储当前要发送的8位数据 +reg [1:0] byte_select; // 控制发送高8位还是低8位数据 + +// 发送状态机定义 +reg [3:0] tx_state; +reg [9:0] tx_shift_reg; // 10位移位寄存器（8位数据 + 起始位 + 停止位） +reg [3:0] tx_bit_counter; // 用于计数8位数据发送的每一位 + +// 波特率计数器更新 +always @(posedge clk or posedge rst) begin + if (!rst) + baud_counter <= 0; + else if (baud_counter == BAUD_TICK - 1) + baud_counter <= 0; + else + baud_counter <= baud_counter + 1; +end + +// UART发送逻辑 +always @(posedge clk or posedge rst) begin + if (!rst) begin + tx_state <= 0; + tx_done <= 0; + byte_select <= 0; + tx_shift_reg <= 10'b1111111111; // 空闲状态（全1表示停止位） + end + else if (baud_counter == BAUD_TICK - 1) begin + case (tx_state) + 0: begin + if (tx_start) begin + // 根据 byte_select 选择发送高8位或低8位数据 + if (byte_select == 0) + data_to_send <= tx_data[15:8]; // 发送低8位 + else + data_to_send <= tx_data[7:0]; // 发送高8位 + + // 将要发送的8位数据加上起始位（0）和停止位（1） + tx_shift_reg <= {1'b1, data_to_send, 1'b0}; // 1位停止位，8位数据，1位起始位 + tx_bit_counter <= 0; + tx_state <= 1; + tx_done <= 0; + end + end + 1: begin + // 每个波特率时钟周期发送一位 + if (tx_bit_counter == 9) begin // 所有位发送完成后回到空闲状态 + if (byte_select == 0) + byte_select <= 1; // 切换到发送高8位 + else begin + byte_select <= 0; // 重置为低8位 + tx_done <= 1; // 完成整个16位数据的发送 + end + tx_state <= 0; + end + else begin + tx_shift_reg <= {1'b1, tx_shift_reg[9:1]}; // 右移移位寄存器 + tx_bit_counter <= tx_bit_counter + 1; + end + end + endcase + end +end + +assign tx = tx_shift_reg[0]; // 串行输出当前最低位 + +endmodule \ No newline at end of file diff --git a/puart2/intan_m10.v.bak b/puart2/intan_m10.v.bak new file mode 100644 index 0000000..b825663 --- /dev/null +++ b/puart2/intan_m10.v.bak @@ -0,0 +1,82 @@ +module uart_tx ( + input wire clk, // 时钟信号 + input wire rst, // 复位信号 + input wire tx_start, // 开始发送信号 + input wire [15:0] tx_data, // 顶层输入的16位待发送数据 + output wire tx, // 串行输出信号 + output reg tx_done // 发送完成信号 +); + +parameter BAUD_RATE = 115200; +parameter CLOCK_FREQ = 12000000; // 12 MHz时钟 + +localparam integer BAUD_TICK = CLOCK_FREQ / BAUD_RATE; // 波特率计数，计算出每个比特的时钟周期数 + +// 波特率计数器 +reg [15:0] baud_counter; +reg [7:0] data_to_send; // 用于存储当前要发送的8位数据 +reg [1:0] byte_select; // 控制发送高8位还是低8位数据 + +// 发送状态机定义 +reg [3:0] tx_state; +reg [9:0] tx_shift_reg; // 10位移位寄存器（8位数据 + 起始位 + 停止位） +reg [3:0] tx_bit_counter; // 用于计数8位数据发送的每一位 + +// 波特率计数器更新 +always @(posedge clk or posedge rst) begin + if (!rst) + baud_counter <= 0; + else if (baud_counter == BAUD_TICK - 1) + baud_counter <= 0; + else + baud_counter <= baud_counter + 1; +end + +// UART发送逻辑 +always @(posedge clk or posedge rst) begin + if (!rst) begin + tx_state <= 0; + tx_done <= 0; + byte_select <= 0; + tx_shift_reg <= 10'b1111111111; // 空闲状态（全1表示停止位） + end + else if (baud_counter == BAUD_TICK - 1) begin + case (tx_state) + 0: begin + if (tx_start) begin + // 根据 byte_select 选择发送高8位或低8位数据 + if (byte_select == 0) + data_to_send <= tx_data[15:8]; // 发送低8位 + else + data_to_send <= tx_data[7:0]; // 发送高8位 + + // 将要发送的8位数据加上起始位（0）和停止位（1） + tx_shift_reg <= {1'b1, data_to_send, 1'b0}; // 1位停止位，8位数据，1位起始位 + tx_bit_counter <= 0; + tx_state <= 1; + tx_done <= 0; + end + end + 1: begin + // 每个波特率时钟周期发送一位 + if (tx_bit_counter == 9) begin // 所有位发送完成后回到空闲状态 + if (byte_select == 0) + byte_select <= 1; // 切换到发送高8位 + else begin + byte_select <= 0; // 重置为低8位 + tx_done <= 1; // 完成整个16位数据的发送 + end + tx_state <= 0; + end + else begin + tx_shift_reg <= {1'b1, tx_shift_reg[9:1]}; // 右移移位寄存器 + tx_bit_counter <= tx_bit_counter + 1; + end + end + endcase + end +end + +assign tx = tx_shift_reg[0]; // 串行输出当前最低位 + +endmodule \ No newline at end of file diff --git a/puart2/intan_m10_assignment_defaults.qdf b/puart2/intan_m10_assignment_defaults.qdf new file mode 100644 index 0000000..55926a4 --- /dev/null +++ b/puart2/intan_m10_assignment_defaults.qdf @@ -0,0 +1,807 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition +# Date created = 17:57:18 April 15, 2024 +# +# -------------------------------------------------------------------------- # +# +# Note: +# +# 1) Do not modify this file. This file was generated +# automatically by the Quartus Prime software and is used +# to preserve global assignments across Quartus Prime versions. +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off +set_global_assignment -name IP_COMPONENT_INTERNAL Off +set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On +set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off +set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off +set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db +set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off +set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off +set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off +set_global_assignment -name HC_OUTPUT_DIR hc_output +set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off +set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off +set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" +set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On +set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On +set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off +set_global_assignment -name REVISION_TYPE Base -family "Arria V" +set_global_assignment -name REVISION_TYPE Base -family "Stratix V" +set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ" +set_global_assignment -name REVISION_TYPE Base -family "Cyclone V" +set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" +set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On +set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On +set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On +set_global_assignment -name DO_COMBINED_ANALYSIS Off +set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off +set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off +set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off +set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off +set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On +set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10" 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+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ" 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+set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 +set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 +set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On +set_global_assignment -name PARALLEL_SYNTHESIS On +set_global_assignment -name DSP_BLOCK_BALANCING Auto +set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" +set_global_assignment -name NOT_GATE_PUSH_BACK On +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On +set_global_assignment -name IGNORE_CARRY_BUFFERS Off +set_global_assignment -name IGNORE_CASCADE_BUFFERS Off +set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_LCELL_BUFFERS Off +set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO +set_global_assignment -name IGNORE_SOFT_BUFFERS On +set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off +set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off +set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On +set_global_assignment -name AUTO_GLOBAL_OE_MAX On +set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off +set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut +set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name ALLOW_XOR_GATE_USAGE On +set_global_assignment -name AUTO_LCELL_INSERTION On +set_global_assignment -name CARRY_CHAIN_LENGTH 48 +set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 +set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name CASCADE_CHAIN_LENGTH 2 +set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 +set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 +set_global_assignment -name AUTO_CARRY_CHAINS On +set_global_assignment -name AUTO_CASCADE_CHAINS On +set_global_assignment -name AUTO_PARALLEL_EXPANDERS On +set_global_assignment -name AUTO_OPEN_DRAIN_PINS On +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off +set_global_assignment -name AUTO_ROM_RECOGNITION On +set_global_assignment -name AUTO_RAM_RECOGNITION On +set_global_assignment -name AUTO_DSP_RECOGNITION On +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto +set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On +set_global_assignment -name STRICT_RAM_RECOGNITION Off +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On +set_global_assignment -name FORCE_SYNCH_CLEAR Off +set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On +set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off +set_global_assignment -name AUTO_RESOURCE_SHARING Off +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off +set_global_assignment -name MAX7000_FANIN_PER_CELL 100 +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On +set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" +set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off +set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" +set_global_assignment -name REPORT_PARAMETER_SETTINGS On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On +set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100 +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 +set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000 +set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off +set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" +set_global_assignment -name MAX_LABS "-1 (Unlimited)" +set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On +set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" +set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On +set_global_assignment -name PRPOF_ID Off +set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off +set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On +set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name TXPMA_SLEW_RATE Low +set_global_assignment -name ADCE_ENABLED Auto +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name PHYSICAL_SYNTHESIS Off +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name ENABLE_NCEO_OUTPUT Off +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image" +set_global_assignment -name CVP_MODE Off +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V" +set_global_assignment -name VID_OPERATION_MODE "PMBus Slave" +set_global_assignment -name USE_CONF_DONE AUTO +set_global_assignment -name USE_PWRMGT_SCL AUTO +set_global_assignment -name USE_PWRMGT_SDA AUTO +set_global_assignment -name USE_PWRMGT_ALERT AUTO +set_global_assignment -name USE_INIT_DONE AUTO +set_global_assignment -name USE_CVP_CONFDONE AUTO +set_global_assignment -name USE_SEU_ERROR AUTO +set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off +set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On +set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name INIT_DONE_OPEN_DRAIN On +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name ENABLE_CONFIGURATION_PINS On +set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off +set_global_assignment -name ENABLE_NCE_PIN Off +set_global_assignment -name ENABLE_BOOT_SEL_PIN On +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name INTERNAL_SCRUBBING Off +set_global_assignment -name PR_ERROR_OPEN_DRAIN On +set_global_assignment -name PR_READY_OPEN_DRAIN On +set_global_assignment -name ENABLE_CVP_CONFDONE Off +set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On +set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ" +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF +set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto +set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V" +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto +set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" +set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off +set_global_assignment -name PR_DONE_OPEN_DRAIN On +set_global_assignment -name NCEO_OPEN_DRAIN On +set_global_assignment -name ENABLE_CRC_ERROR_PIN Off +set_global_assignment -name ENABLE_PR_PINS Off +set_global_assignment -name RESERVE_PR_PINS Off +set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off +set_global_assignment -name PR_PINS_OPEN_DRAIN Off +set_global_assignment -name CLAMPING_DIODE Off +set_global_assignment -name TRI_STATE_SPI_PINS Off +set_global_assignment -name UNUSED_TSD_PINS_GND Off +set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off +set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V" +set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0 +set_global_assignment -name SEU_FIT_REPORT Off +set_global_assignment -name HYPER_RETIMER Off -family "Arria 10" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE On +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130" +set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000 +set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery" +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0 +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP" +set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V" +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF +set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off +set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off +set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off +set_global_assignment -name POR_SCHEME "Instant ON" +set_global_assignment -name EN_USER_IO_WEAK_PULLUP On +set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On +set_global_assignment -name POF_VERIFY_PROTECT Off +set_global_assignment -name ENABLE_SPI_MODE_CHECK Off +set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On +set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0 +set_global_assignment -name GENERATE_PMSF_FILES On +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off +set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO +set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name DRC_GATED_CLOCK_FEED 30 +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name ENABLE_DRC_SETTINGS Off +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 +set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 +set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 +set_global_assignment -name MERGE_HEX_FILE Off +set_global_assignment -name GENERATE_SVF_FILE Off +set_global_assignment -name GENERATE_ISC_FILE Off +set_global_assignment -name GENERATE_JAM_FILE Off +set_global_assignment -name GENERATE_JBC_FILE Off +set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off +set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off +set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" +set_global_assignment -name HPS_EARLY_IO_RELEASE Off +set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off +set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name POWER_HPS_ENABLE Off +set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 +set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off +set_global_assignment -name IGNORE_PARTITIONS Off +set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off +set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On +set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" +set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On +set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On +set_global_assignment -name RTLV_GROUP_RELATED_NODES On +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off +set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On +set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On +set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On +set_global_assignment -name EQC_BBOX_MERGE On +set_global_assignment -name EQC_LVDS_MERGE On +set_global_assignment -name EQC_RAM_UNMERGING On +set_global_assignment -name EQC_DFF_SS_EMULATION On +set_global_assignment -name EQC_RAM_REGISTER_UNPACK On +set_global_assignment -name EQC_MAC_REGISTER_UNPACK On +set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? +set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? +set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? +set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? +set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? +set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? +set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? +set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? +set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? +set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ? diff --git a/puart2/makefile b/puart2/makefile new file mode 100644 index 0000000..5632451 --- /dev/null +++ b/puart2/makefile @@ -0,0 +1,29 @@ +export TEST_NAME = ddr_ctrl +FILE_LIST = filelist.f + +PLATFORM = LINUX64 +waveform = $(TEST_NAME).fsdb + +all: clean compile sim + +# VCS + +compile: + vcs -notice -debug_acc+all -j8 -timescale=1ns/1ps \ + -sverilog -LDFLAGS -rdynamic -full64 \ + -f $(FILE_LIST) \ + +vcs+lic+wait \ + -l vcs_com.log + +sim: + ./simv \ + +fsdb+autoflush \ + -l vcs_sim.log + +# verdi +verdi: + verdi -nologo -sv -f $(FILE_LIST) -ssf $(TEST_NAME).fsdb & + +# clean +clean: + @rm -rf csrc DVEfiles simv simv.daidir ucli.key novas* VCS* *dat verdi* vcs* *.fsdb diff --git a/puart2/output_files/greybox_tmp/cbx_args.txt b/puart2/output_files/greybox_tmp/cbx_args.txt new file mode 100644 index 0000000..ba166fc --- /dev/null +++ b/puart2/output_files/greybox_tmp/cbx_args.txt @@ -0,0 +1,63 @@ +BANDWIDTH_TYPE=AUTO +CLK0_DIVIDE_BY=625 +CLK0_DUTY_CYCLE=50 +CLK0_MULTIPLY_BY=6 +CLK0_PHASE_SHIFT=0 +CLK1_DIVIDE_BY=625 +CLK1_DUTY_CYCLE=50 +CLK1_MULTIPLY_BY=12 +CLK1_PHASE_SHIFT=0 +COMPENSATE_CLOCK=CLK0 +INCLK0_INPUT_FREQUENCY=83333 +INTENDED_DEVICE_FAMILY="MAX 10" +LPM_TYPE=altpll +OPERATION_MODE=NORMAL +PLL_TYPE=AUTO +PORT_ACTIVECLOCK=PORT_UNUSED +PORT_ARESET=PORT_UNUSED +PORT_CLKBAD0=PORT_UNUSED +PORT_CLKBAD1=PORT_UNUSED +PORT_CLKLOSS=PORT_UNUSED +PORT_CLKSWITCH=PORT_UNUSED +PORT_CONFIGUPDATE=PORT_UNUSED +PORT_FBIN=PORT_UNUSED +PORT_INCLK0=PORT_USED +PORT_INCLK1=PORT_UNUSED +PORT_LOCKED=PORT_UNUSED +PORT_PFDENA=PORT_UNUSED +PORT_PHASECOUNTERSELECT=PORT_UNUSED +PORT_PHASEDONE=PORT_UNUSED +PORT_PHASESTEP=PORT_UNUSED +PORT_PHASEUPDOWN=PORT_UNUSED +PORT_PLLENA=PORT_UNUSED +PORT_SCANACLR=PORT_UNUSED +PORT_SCANCLK=PORT_UNUSED +PORT_SCANCLKENA=PORT_UNUSED +PORT_SCANDATA=PORT_UNUSED +PORT_SCANDATAOUT=PORT_UNUSED +PORT_SCANDONE=PORT_UNUSED +PORT_SCANREAD=PORT_UNUSED +PORT_SCANWRITE=PORT_UNUSED +PORT_clk0=PORT_USED +PORT_clk1=PORT_USED +PORT_clk2=PORT_UNUSED +PORT_clk3=PORT_UNUSED +PORT_clk4=PORT_UNUSED +PORT_clk5=PORT_UNUSED +PORT_clkena0=PORT_UNUSED +PORT_clkena1=PORT_UNUSED +PORT_clkena2=PORT_UNUSED +PORT_clkena3=PORT_UNUSED +PORT_clkena4=PORT_UNUSED +PORT_clkena5=PORT_UNUSED +PORT_extclk0=PORT_UNUSED +PORT_extclk1=PORT_UNUSED +PORT_extclk2=PORT_UNUSED +PORT_extclk3=PORT_UNUSED +WIDTH_CLOCK=5 +DEVICE_FAMILY="MAX 10" +CBX_AUTO_BLACKBOX=ALL +inclk +inclk +clk +clk diff --git a/puart2/output_files/intan_m10.asm.rpt b/puart2/output_files/intan_m10.asm.rpt new file mode 100644 index 0000000..59de77d --- /dev/null +++ b/puart2/output_files/intan_m10.asm.rpt @@ -0,0 +1,90 @@ +Assembler report for intan_m10 +Thu Dec 11 18:00:34 2025 +Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: E:/FPGA/puart2/output_files/intan_m10.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2017 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Thu Dec 11 18:00:34 2025 ; +; Revision Name ; intan_m10 ; +; Top-level Entity Name ; ddr_ctrl ; +; Family ; MAX 10 ; +; Device ; 10M08SAM153C8G ; ++-----------------------+---------------------------------------+ + + ++----------------------------------+ +; Assembler Settings ; ++--------+---------+---------------+ +; Option ; Setting ; Default Value ; ++--------+---------+---------------+ + + ++-------------------------------------------+ +; Assembler Generated Files ; ++-------------------------------------------+ +; File Name ; ++-------------------------------------------+ +; E:/FPGA/puart2/output_files/intan_m10.sof ; ++-------------------------------------------+ + + ++---------------------------------------------------------------------+ +; Assembler Device Options: E:/FPGA/puart2/output_files/intan_m10.sof ; ++----------------+----------------------------------------------------+ +; Option ; Setting ; ++----------------+----------------------------------------------------+ +; JTAG usercode ; 0x0009DE95 ; +; Checksum ; 0x0009DE95 ; ++----------------+----------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Assembler + Info: Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition + Info: Processing started: Thu Dec 11 18:00:32 2025 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10 +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 4672 megabytes + Info: Processing ended: Thu Dec 11 18:00:34 2025 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/puart2/output_files/intan_m10.cdf b/puart2/output_files/intan_m10.cdf new file mode 100644 index 0000000..ccf51d5 --- /dev/null +++ b/puart2/output_files/intan_m10.cdf @@ -0,0 +1,13 @@ +/* Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition */ +JedecChain; + FileRevision(JESD32A); + DefaultMfr(6E); + + P ActionCode(Cfg) + Device PartName(10M08SAM153) Path("E:/FPGA/puart2/output_files/") File("intan_m10.pof") MfrSpec(OpMask(1) Child_OpMask(2 1 1)); + +ChainEnd; + +AlteraBegin; + ChainType(JTAG); +AlteraEnd; diff --git a/puart2/output_files/intan_m10.done b/puart2/output_files/intan_m10.done new file mode 100644 index 0000000..353569b --- /dev/null +++ b/puart2/output_files/intan_m10.done @@ -0,0 +1 @@ +Thu Dec 11 18:00:41 2025 diff --git a/puart2/output_files/intan_m10.eda.rpt b/puart2/output_files/intan_m10.eda.rpt new file mode 100644 index 0000000..87000b0 --- /dev/null +++ b/puart2/output_files/intan_m10.eda.rpt @@ -0,0 +1,60 @@ +EDA Netlist Writer report for intan_m10 +Mon Apr 15 18:12:21 2024 +Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++----------------------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++---------------------------+------------------------------------------------------+ +; EDA Netlist Writer Status ; No Output Files Generated - Mon Apr 15 18:12:21 2024 ; +; Revision Name ; intan_m10 ; +; Top-level Entity Name ; ddr_ctrl ; +; Family ; MAX 10 ; ++---------------------------+------------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime EDA Netlist Writer + Info: Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition + Info: Processing started: Mon Apr 15 18:12:20 2024 +Info: Command: quartus_eda --read_settings_files=on --write_settings_files=off intan_m10 -c intan_m10 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Warning (199027): Can't generate output files. Specify command-line options to generate output files, or update EDA tool settings using GUI or Tcl script. +Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 2 warnings + Info: Peak virtual memory: 4633 megabytes + Info: Processing ended: Mon Apr 15 18:12:21 2024 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:00 + + diff --git a/puart2/output_files/intan_m10.fit.rpt b/puart2/output_files/intan_m10.fit.rpt new file mode 100644 index 0000000..79cc314 --- /dev/null +++ b/puart2/output_files/intan_m10.fit.rpt @@ -0,0 +1,1203 @@ +Fitter report for intan_m10 +Thu Dec 11 18:00:31 2025 +Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Incremental Compilation Preservation Summary + 6. Incremental Compilation Partition Settings + 7. Incremental Compilation Placement Preservation + 8. Pin-Out File + 9. Fitter Resource Usage Summary + 10. Fitter Partition Statistics + 11. Input Pins + 12. Output Pins + 13. Dual Purpose and Dedicated Pins + 14. I/O Bank Usage + 15. All Package Pins + 16. PLL Summary + 17. PLL Usage + 18. I/O Assignment Warnings + 19. Fitter Resource Utilization by Entity + 20. Delay Chain Summary + 21. Pad To Core Delay Chain Fanout + 22. Control Signals + 23. Global & Other Fast Signals + 24. Routing Usage Summary + 25. LAB Logic Elements + 26. LAB-wide Signals + 27. LAB Signals Sourced + 28. LAB Signals Sourced Out + 29. LAB Distinct Inputs + 30. I/O Rules Summary + 31. I/O Rules Details + 32. I/O Rules Matrix + 33. Fitter Device Options + 34. Operating Settings and Conditions + 35. Estimated Delay Added for Hold Timing Summary + 36. Estimated Delay Added for Hold Timing Details + 37. Fitter Messages + 38. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2017 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++----------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+---------------------------------------------+ +; Fitter Status ; Successful - Thu Dec 11 18:00:31 2025 ; +; Quartus Prime Version ; 17.1.0 Build 590 10/25/2017 SJ Lite Edition ; +; Revision Name ; intan_m10 ; +; Top-level Entity Name ; ddr_ctrl ; +; Family ; MAX 10 ; +; Device ; 10M08SAM153C8G ; +; Timing Models ; Final ; +; Total logic elements ; 183 / 8,064 ( 2 % ) ; +; Total combinational functions ; 123 / 8,064 ( 2 % ) ; +; Dedicated logic registers ; 135 / 8,064 ( 2 % ) ; +; Total registers ; 135 ; +; Total pins ; 13 / 112 ( 12 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 387,072 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 48 ( 0 % ) ; +; Total PLLs ; 1 / 1 ( 100 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 1 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; 10M08SAM153C8G ; ; +; Maximum processors allowed for parallel compilation ; 4 ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; Power Optimization During Fitting ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Periphery to Core Placement and Routing Optimization ; Off ; Off ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Auto ; Auto ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.06 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 2.1% ; ++----------------------------+-------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+--------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+--------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 304 ) ; 0.00 % ( 0 / 304 ) ; 0.00 % ( 0 / 304 ) ; +; -- Achieved ; 0.00 % ( 0 / 304 ) ; 0.00 % ( 0 / 304 ) ; 0.00 % ( 0 / 304 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+--------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 286 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 18 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in E:/FPGA/puart2/output_files/intan_m10.pin. + + ++-------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+---------------------+ +; Resource ; Usage ; ++---------------------------------------------+---------------------+ +; Total logic elements ; 183 / 8,064 ( 2 % ) ; +; -- Combinational with no register ; 48 ; +; -- Register only ; 60 ; +; -- Combinational with a register ; 75 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 60 ; +; -- 3 input functions ; 30 ; +; -- <=2 input functions ; 33 ; +; -- Register only ; 60 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 102 ; +; -- arithmetic mode ; 21 ; +; ; ; +; Total registers* ; 135 / 8,597 ( 2 % ) ; +; -- Dedicated logic registers ; 135 / 8,064 ( 2 % ) ; +; -- I/O registers ; 0 / 533 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 15 / 504 ( 3 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 13 / 112 ( 12 % ) ; +; -- Clock pins ; 2 / 4 ( 50 % ) ; +; -- Dedicated input pins ; 1 / 1 ( 100 % ) ; +; ; ; +; M9Ks ; 0 / 42 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 1 ( 0 % ) ; +; Total block memory bits ; 0 / 387,072 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 387,072 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 48 ( 0 % ) ; +; PLLs ; 1 / 1 ( 100 % ) ; +; Global signals ; 2 ; +; -- Global clocks ; 2 / 10 ( 20 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; Remote update blocks ; 0 / 1 ( 0 % ) ; +; Oscillator blocks ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0.4% / 0.4% / 0.3% ; +; Peak interconnect usage (total/H/V) ; 1.4% / 1.5% / 1.2% ; +; Maximum fan-out ; 104 ; +; Highest non-global fan-out ; 95 ; +; Total fan-out ; 904 ; +; Average fan-out ; 2.56 ; ++---------------------------------------------+---------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++---------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+--------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++---------------------------------------------+--------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; +; ; ; ; +; Total logic elements ; 183 / 8064 ( 2 % ) ; 0 / 8064 ( 0 % ) ; +; -- Combinational with no register ; 48 ; 0 ; +; -- Register only ; 60 ; 0 ; +; -- Combinational with a register ; 75 ; 0 ; +; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; +; -- 4 input functions ; 60 ; 0 ; +; -- 3 input functions ; 30 ; 0 ; +; -- <=2 input functions ; 33 ; 0 ; +; -- Register only ; 60 ; 0 ; +; ; ; ; +; Logic elements by mode ; ; ; +; -- normal mode ; 102 ; 0 ; +; -- arithmetic mode ; 21 ; 0 ; +; ; ; ; +; Total registers ; 135 ; 0 ; +; -- Dedicated logic registers ; 135 / 8064 ( 2 % ) ; 0 / 8064 ( 0 % ) ; +; -- I/O registers ; 0 ; 0 ; +; ; ; ; +; Total LABs: partially or completely used ; 15 / 504 ( 3 % ) ; 0 / 504 ( 0 % ) ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 13 ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 / 48 ( 0 % ) ; 0 / 48 ( 0 % ) ; +; Total memory bits ; 0 ; 0 ; +; Total RAM block bits ; 0 ; 0 ; +; PLL ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ; +; Clock control block ; 1 / 12 ( 8 % ) ; 1 / 12 ( 8 % ) ; +; User Flash Memory ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; +; Analog-to-Digital Converter ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 104 ; 1 ; +; -- Registered Input Connections ; 104 ; 0 ; +; -- Output Connections ; 1 ; 104 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 902 ; 115 ; +; -- Registered Connections ; 456 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 105 ; +; -- hard_block:auto_generated_inst ; 105 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 4 ; 1 ; +; -- Output Ports ; 9 ; 1 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++---------------------------------------------+--------------------+--------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++-----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ; ++-----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; miso ; P4 ; 3 ; 3 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVCMOS ; -- ; User ; 0 ; +; rst_n ; J14 ; 5 ; 31 ; 6 ; 0 ; 95 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVCMOS ; -- ; User ; 0 ; +; sys_clk ; J5 ; 2 ; 0 ; 7 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVCMOS ; -- ; User ; 0 ; +; test_flag ; J12 ; 6 ; 31 ; 9 ; 21 ; 5 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVCMOS ; -- ; User ; 0 ; ++-----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; MOSI_ESP32 ; A14 ; 8 ; 13 ; 25 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 2mA ; Off ; -- ; no ; no ; User ; - ; - ; +; convert_flag_led ; M12 ; 5 ; 31 ; 1 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 2mA ; Off ; -- ; no ; no ; User ; - ; - ; +; cs_ESP32 ; B13 ; 8 ; 15 ; 25 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 2mA ; Off ; -- ; no ; no ; User ; - ; - ; +; cs_n ; P6 ; 3 ; 9 ; 0 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 2mA ; Off ; -- ; no ; no ; User ; - ; - ; +; mosi ; L7 ; 3 ; 6 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 2mA ; Off ; -- ; no ; no ; User ; - ; - ; +; sclk ; R5 ; 3 ; 6 ; 0 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 2mA ; Off ; -- ; no ; no ; User ; - ; - ; +; sclk_ESP32 ; B14 ; 8 ; 15 ; 25 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 2mA ; Off ; -- ; no ; no ; User ; - ; - ; +; test_flag_led ; N15 ; 5 ; 31 ; 1 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 2mA ; Off ; -- ; no ; no ; User ; - ; - ; +; tx ; P8 ; 3 ; 6 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 2mA ; Off ; -- ; no ; no ; User ; - ; - ; ++------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Dual Purpose and Dedicated Pins ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ +; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ +; G1 ; DIFFIO_RX_L11n, DIFFOUT_L11n, TMS, Low_Speed ; Reserved as secondary function ; ~ALTERA_TMS~ ; Dual Purpose Pin ; +; J1 ; DIFFIO_RX_L11p, DIFFOUT_L11p, TCK, Low_Speed ; Reserved as secondary function ; ~ALTERA_TCK~ ; Dual Purpose Pin ; +; H5 ; DIFFIO_RX_L12n, DIFFOUT_L12n, TDI, Low_Speed ; Reserved as secondary function ; ~ALTERA_TDI~ ; Dual Purpose Pin ; +; H4 ; DIFFIO_RX_L12p, DIFFOUT_L12p, TDO, Low_Speed ; Reserved as secondary function ; ~ALTERA_TDO~ ; Dual Purpose Pin ; +; D8 ; CONFIG_SEL, Low_Speed ; Reserved as secondary function ; ~ALTERA_CONFIG_SEL~ ; Dual Purpose Pin ; +; E8 ; nCONFIG, Low_Speed ; Reserved as secondary function ; ~ALTERA_nCONFIG~ ; Dual Purpose Pin ; +; D6 ; DIFFIO_RX_T24p, DIFFOUT_T24p, nSTATUS, Low_Speed ; Reserved as secondary function ; ~ALTERA_nSTATUS~ ; Dual Purpose Pin ; +; E6 ; DIFFIO_RX_T24n, DIFFOUT_T24n, CONF_DONE, Low_Speed ; Reserved as secondary function ; ~ALTERA_CONF_DONE~ ; Dual Purpose Pin ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ + + ++-----------------------------------------------------------+ +; I/O Bank Usage ; ++----------+-----------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+-----------------+---------------+--------------+ +; 1A ; 0 / 8 ( 0 % ) ; 2.5V ; -- ; +; 1B ; 4 / 10 ( 40 % ) ; 2.5V ; -- ; +; 2 ; 1 / 10 ( 10 % ) ; 3.3V ; -- ; +; 3 ; 5 / 28 ( 18 % ) ; 3.3V ; -- ; +; 5 ; 3 / 12 ( 25 % ) ; 3.3V ; -- ; +; 6 ; 1 / 16 ( 6 % ) ; 3.3V ; -- ; +; 8 ; 7 / 28 ( 25 % ) ; 3.3V ; -- ; ++----------+-----------------+---------------+--------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+-----------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+-----------+------------+-----------------+----------+--------------+ +; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A2 ; 248 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A3 ; 250 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A5 ; 243 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A7 ; 241 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A9 ; 237 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A11 ; 239 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A13 ; 231 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; A14 ; 227 ; 8 ; MOSI_ESP32 ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; A15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B1 ; 10 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B3 ; ; -- ; VCCA3 ; power ; ; 3.0V/3.3V ; -- ; ; -- ; -- ; +; B4 ; 245 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B5 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; B6 ; 238 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B7 ; 236 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B8 ; 226 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B9 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; B10 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; B11 ; 235 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B12 ; 233 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B13 ; 225 ; 8 ; cs_ESP32 ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; B14 ; 223 ; 8 ; sclk_ESP32 ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; B15 ; 221 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C1 ; 8 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C2 ; 2 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C8 ; 224 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C14 ; 179 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C15 ; 177 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D2 ; 0 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D4 ; ; ; ANAIN1 ; ; ; ; -- ; ; -- ; -- ; +; D5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D6 ; 244 ; 8 ; ~ALTERA_nSTATUS~ / RESERVED_INPUT ; input ; 3.3 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; D7 ; 240 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D8 ; 232 ; 8 ; ~ALTERA_CONFIG_SEL~ / RESERVED_INPUT ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; D9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D10 ; 222 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D11 ; 220 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D12 ; 190 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D14 ; ; -- ; VCCA2 ; power ; ; 3.0V/3.3V ; -- ; ; -- ; -- ; +; E1 ; 12 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E2 ; 14 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E4 ; ; ; REFGND ; ; ; ; -- ; ; -- ; -- ; +; E5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E6 ; 246 ; 8 ; ~ALTERA_CONF_DONE~ / RESERVED_INPUT ; input ; 3.3 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; E7 ; 242 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E8 ; 234 ; 8 ; ~ALTERA_nCONFIG~ / RESERVED_INPUT ; input ; 3.3 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; E9 ; 230 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E10 ; 228 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E11 ; 188 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E14 ; 175 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E15 ; 173 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; F2 ; ; 1A ; VCCIO1A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F4 ; ; ; ADC_VREF ; ; ; ; -- ; ; -- ; -- ; +; F5 ; 4 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F11 ; 176 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F12 ; 178 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F14 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; G1 ; 20 ; 1B ; ~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; On ; +; G2 ; 21 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G5 ; 6 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G7 ; 18 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G8 ; ; -- ; VCC_ONE ; power ; ; 3.0V/3.3V ; -- ; ; -- ; -- ; +; G9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G11 ; 172 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G12 ; 174 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G14 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; G15 ; 158 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H2 ; ; 1B ; VCCIO1B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H3 ; 28 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H4 ; 26 ; 1B ; ~ALTERA_TDO~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; H5 ; 24 ; 1B ; ~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; On ; +; H7 ; ; -- ; VCC_ONE ; power ; ; 3.0V/3.3V ; -- ; ; -- ; -- ; +; H8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H9 ; ; -- ; VCC_ONE ; power ; ; 3.0V/3.3V ; -- ; ; -- ; -- ; +; H11 ; 150 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H12 ; 152 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H13 ; 154 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J1 ; 22 ; 1B ; ~ALTERA_TCK~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; Off ; +; J2 ; 30 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J4 ; 36 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J5 ; 38 ; 2 ; sys_clk ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; J7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J8 ; ; -- ; VCC_ONE ; power ; ; 3.0V/3.3V ; -- ; ; -- ; -- ; +; J9 ; 140 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J11 ; 142 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J12 ; 148 ; 6 ; test_flag ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; J14 ; 143 ; 5 ; rst_n ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; J15 ; 156 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K2 ; 34 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K4 ; 42 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K5 ; 40 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K11 ; 132 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K12 ; 134 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K14 ; 141 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L1 ; 32 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L2 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; L4 ; 46 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L5 ; 44 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L6 ; 64 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L7 ; 66 ; 3 ; mosi ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; L8 ; 72 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L9 ; 84 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L10 ; 88 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L11 ; 122 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; L15 ; 135 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; M2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M4 ; 60 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M5 ; 62 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M7 ; 74 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M8 ; 76 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M9 ; 86 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; 90 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M12 ; 120 ; 5 ; convert_flag_led ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; M14 ; 133 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N1 ; 56 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N2 ; ; -- ; VCCA1 ; power ; ; 3.0V/3.3V ; -- ; ; -- ; -- ; +; N8 ; 78 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N14 ; 123 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N15 ; 121 ; 5 ; test_flag_led ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; P1 ; 45 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; P2 ; 58 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P3 ; 61 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P4 ; 65 ; 3 ; miso ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; P5 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; P6 ; 68 ; 3 ; cs_n ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; P7 ; 70 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P8 ; 71 ; 3 ; tx ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; P9 ; 73 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P10 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; P11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; P12 ; 79 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P13 ; ; -- ; VCCA4 ; power ; ; 3.0V/3.3V ; -- ; ; -- ; -- ; +; P14 ; 92 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P15 ; 82 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R2 ; 47 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R3 ; 63 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R5 ; 67 ; 3 ; sclk ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; R7 ; 69 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R9 ; 75 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R11 ; 77 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; R13 ; 94 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R14 ; 80 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+-----------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++-----------------------------------------------------------------------------------------------------------------+ +; PLL Summary ; ++-------------------------------+---------------------------------------------------------------------------------+ +; Name ; clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|pll1 ; ++-------------------------------+---------------------------------------------------------------------------------+ +; SDC pin name ; clk_gen_inst|altpll_component|auto_generated|pll1 ; +; PLL mode ; Normal ; +; Compensate clock ; clock0 ; +; Compensated input/output pins ; -- ; +; Switchover type ; -- ; +; Input frequency 0 ; 12.0 MHz ; +; Input frequency 1 ; -- ; +; Nominal PFD frequency ; 12.0 MHz ; +; Nominal VCO frequency ; 432.0 MHz ; +; VCO post scale K counter ; 2 ; +; VCO frequency control ; Auto ; +; VCO phase shift step ; 289 ps ; +; VCO multiply ; -- ; +; VCO divide ; -- ; +; Freq min lock ; 9.8 MHz ; +; Freq max lock ; 18.06 MHz ; +; M VCO Tap ; 0 ; +; M Initial ; 1 ; +; M value ; 36 ; +; N value ; 1 ; +; Charge pump current ; setting 1 ; +; Loop filter resistance ; setting 24 ; +; Loop filter capacitance ; setting 0 ; +; Bandwidth ; 450 kHz to 980 kHz ; +; Bandwidth type ; Medium ; +; Real time reconfigurable ; Off ; +; Scan chain MIF file ; -- ; +; Preserve PLL counter order ; Off ; +; PLL location ; PLL_1 ; +; Inclk0 signal ; sys_clk ; +; Inclk1 signal ; -- ; +; Inclk0 signal type ; Dedicated Pin ; +; Inclk1 signal type ; -- ; ++-------------------------------+---------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; PLL Usage ; ++--------------------------------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+-------------+---------------+---------+---------+----------------------------------------------------------+ +; Name ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift ; Phase Shift Step ; Duty Cycle ; Counter ; Counter Value ; High / Low ; Cascade Input ; Initial ; VCO Tap ; SDC Pin Name ; ++--------------------------------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+-------------+---------------+---------+---------+----------------------------------------------------------+ +; clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|wire_pll1_clk[0] ; clock0 ; 6 ; 625 ; 0.12 MHz ; 0 (0 ps) ; 0.12 (289 ps) ; 50/50 ; C1 ; 375 ; 188/187 Odd ; C0 ; 1 ; 0 ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; +; clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|wire_pll1_clk[0]~cascade_in ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; C0 ; 10 ; 5/5 Even ; -- ; 1 ; 0 ; ; ++--------------------------------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+-------------+---------------+---------+---------+----------------------------------------------------------+ + + ++-------------------------------------------+ +; I/O Assignment Warnings ; ++------------------+------------------------+ +; Pin Name ; Reason ; ++------------------+------------------------+ +; mosi ; Missing drive strength ; +; cs_n ; Missing drive strength ; +; sclk ; Missing drive strength ; +; MOSI_ESP32 ; Missing drive strength ; +; cs_ESP32 ; Missing drive strength ; +; sclk_ESP32 ; Missing drive strength ; +; tx ; Missing drive strength ; +; test_flag_led ; Missing drive strength ; +; convert_flag_led ; Missing drive strength ; ++------------------+------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++------------------------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+--------------------------------------------------------------------------------------+-----------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ; ++------------------------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+--------------------------------------------------------------------------------------+-----------------+--------------+ +; |ddr_ctrl ; 183 (65) ; 135 (52) ; 0 (0) ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 13 ; 0 ; 48 (13) ; 60 (26) ; 75 (22) ; 0 ; |ddr_ctrl ; ddr_ctrl ; work ; +; |clk_gen:clk_gen_inst| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; |ddr_ctrl|clk_gen:clk_gen_inst ; clk_gen ; work ; +; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; |ddr_ctrl|clk_gen:clk_gen_inst|altpll:altpll_component ; altpll ; work ; +; |clk_gen_altpll:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; |ddr_ctrl|clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated ; clk_gen_altpll ; work ; +; |spi_master_2164:u_spi_master_2164| ; 71 (71) ; 43 (43) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 24 (24) ; 34 (34) ; 13 (13) ; 0 ; |ddr_ctrl|spi_master_2164:u_spi_master_2164 ; spi_master_2164 ; work ; +; |uart_tx:u_uart_pc| ; 51 (51) ; 40 (40) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 11 (11) ; 0 (0) ; 40 (40) ; 0 ; |ddr_ctrl|uart_tx:u_uart_pc ; uart_tx ; work ; ++------------------------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+--------------------------------------------------------------------------------------+-----------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++--------------------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++------------------+----------+---------------+---------------+-----------------------+-----+------+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; ++------------------+----------+---------------+---------------+-----------------------+-----+------+ +; mosi ; Output ; -- ; -- ; -- ; -- ; -- ; +; cs_n ; Output ; -- ; -- ; -- ; -- ; -- ; +; sclk ; Output ; -- ; -- ; -- ; -- ; -- ; +; MOSI_ESP32 ; Output ; -- ; -- ; -- ; -- ; -- ; +; cs_ESP32 ; Output ; -- ; -- ; -- ; -- ; -- ; +; sclk_ESP32 ; Output ; -- ; -- ; -- ; -- ; -- ; +; tx ; Output ; -- ; -- ; -- ; -- ; -- ; +; test_flag_led ; Output ; -- ; -- ; -- ; -- ; -- ; +; convert_flag_led ; Output ; -- ; -- ; -- ; -- ; -- ; +; test_flag ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; +; rst_n ; Input ; (6) 873 ps ; -- ; -- ; -- ; -- ; +; sys_clk ; Input ; -- ; -- ; -- ; -- ; -- ; +; miso ; Input ; (6) 868 ps ; -- ; -- ; -- ; -- ; ++------------------+----------+---------------+---------------+-----------------------+-----+------+ + + ++-------------------------------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++-------------------------------------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++-------------------------------------------------------+-------------------+---------+ +; test_flag ; ; ; +; - Selector8~0 ; 1 ; 0 ; +; - spi_master_2164:u_spi_master_2164|Selector0~5 ; 1 ; 0 ; +; - Selector7~0 ; 1 ; 0 ; +; - test_flag_led~output ; 1 ; 0 ; +; - convert_flag_led~output ; 1 ; 0 ; +; rst_n ; ; ; +; - state[1] ; 0 ; 6 ; +; - state[2] ; 0 ; 6 ; +; - state[3] ; 0 ; 6 ; +; - state[4] ; 0 ; 6 ; +; - state[5] ; 0 ; 6 ; +; - state[6] ; 0 ; 6 ; +; - state[7] ; 0 ; 6 ; +; - state[8] ; 0 ; 6 ; +; - state[9] ; 0 ; 6 ; +; - state[10] ; 0 ; 6 ; +; - state[11] ; 0 ; 6 ; +; - state[12] ; 0 ; 6 ; +; - state[13] ; 0 ; 6 ; +; - state[14] ; 0 ; 6 ; +; - state[15] ; 0 ; 6 ; +; - state[16] ; 0 ; 6 ; +; - state[17] ; 0 ; 6 ; +; - state[18] ; 0 ; 6 ; +; - state[19] ; 0 ; 6 ; +; - state[20] ; 0 ; 6 ; +; - state[21] ; 0 ; 6 ; +; - state[22] ; 0 ; 6 ; +; - state[23] ; 0 ; 6 ; +; - state[24] ; 0 ; 6 ; +; - state[25] ; 0 ; 6 ; +; - state[26] ; 0 ; 6 ; +; - state[27] ; 0 ; 6 ; +; - state[28] ; 0 ; 6 ; +; - state[29] ; 0 ; 6 ; +; - state[30] ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|mosi ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|sclk ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|cnt[2] ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|cnt[1] ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|cnt[4] ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|cnt[3] ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|cnt[5] ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|cnt[6] ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|cnt[0] ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|cs_n ; 0 ; 6 ; +; - uart_tx:u_uart_pc|tx_shift_reg[0] ; 0 ; 6 ; +; - state[0] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|tx_state.0001 ; 0 ; 6 ; +; - uart_tx:u_uart_pc|tx_shift_reg[1] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|baud_counter[15] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|baud_counter[14] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|baud_counter[13] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|baud_counter[12] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|baud_counter[11] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|baud_counter[10] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|baud_counter[9] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|baud_counter[8] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|baud_counter[7] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|baud_counter[6] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|baud_counter[5] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|baud_counter[4] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|baud_counter[3] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|baud_counter[2] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|baud_counter[1] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|baud_counter[0] ; 0 ; 6 ; +; - start1 ; 0 ; 6 ; +; - uart_tx:u_uart_pc|tx_shift_reg[2] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|tx_bit_counter[0]~0 ; 0 ; 6 ; +; - state_top.IDLE ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|done ; 0 ; 6 ; +; - state_top.SEND1 ; 0 ; 6 ; +; - sent_data[15]~0 ; 0 ; 6 ; +; - uart_tx:u_uart_pc|tx_done ; 0 ; 6 ; +; - start_uart~0 ; 0 ; 6 ; +; - state_top.SEND_uart ; 0 ; 6 ; +; - uart_tx:u_uart_pc|byte_select.01 ; 0 ; 6 ; +; - uart_tx:u_uart_pc|data_to_send[0]~2 ; 0 ; 6 ; +; - uart_tx:u_uart_pc|tx_shift_reg[3] ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|dout[0] ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|dout[8] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|tx_shift_reg[4] ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|dout[1] ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|dout[9] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|tx_shift_reg[5] ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|dout_r[15]~0 ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|dout[2] ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|dout[10] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|tx_shift_reg[6] ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|dout[3] ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|dout[11] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|tx_shift_reg[7] ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|dout[4] ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|dout[12] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|tx_shift_reg[8] ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|dout[5] ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|dout[13] ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|dout[6] ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|dout[14] ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|dout[7] ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|dout[15] ; 0 ; 6 ; +; sys_clk ; ; ; +; miso ; ; ; +; - spi_master_2164:u_spi_master_2164|dout_r[0] ; 0 ; 6 ; ++-------------------------------------------------------+-------------------+---------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++---------------------------------------------------------------------------------------------+-------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++---------------------------------------------------------------------------------------------+-------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ +; clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|wire_pll1_clk[0] ; PLL_1 ; 104 ; Clock ; yes ; Global Clock ; GCLK4 ; -- ; +; rst_n ; PIN_J14 ; 95 ; Async. clear ; no ; -- ; -- ; -- ; +; sent_data[15]~0 ; LCCOMB_X24_Y5_N26 ; 17 ; Clock enable ; no ; -- ; -- ; -- ; +; spi_master_2164:u_spi_master_2164|Equal0~2 ; LCCOMB_X15_Y7_N2 ; 8 ; Sync. clear ; no ; -- ; -- ; -- ; +; spi_master_2164:u_spi_master_2164|Equal1~0 ; LCCOMB_X20_Y7_N18 ; 16 ; Clock enable ; no ; -- ; -- ; -- ; +; spi_master_2164:u_spi_master_2164|cs_n ; FF_X1_Y9_N31 ; 31 ; Clock ; yes ; Global Clock ; GCLK1 ; -- ; +; spi_master_2164:u_spi_master_2164|dout_r[15]~0 ; LCCOMB_X19_Y7_N4 ; 16 ; Clock enable ; no ; -- ; -- ; -- ; +; sys_clk ; PIN_J5 ; 1 ; Clock ; no ; -- ; -- ; -- ; +; uart_tx:u_uart_pc|data_to_send[0]~2 ; LCCOMB_X23_Y5_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_tx:u_uart_pc|tx_bit_counter[0]~0 ; LCCOMB_X23_Y5_N6 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; uart_tx:u_uart_pc|tx_shift_reg[8]~1 ; LCCOMB_X23_Y5_N14 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; ++---------------------------------------------------------------------------------------------+-------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++---------------------------------------------------------------------------------------------+--------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++---------------------------------------------------------------------------------------------+--------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ +; clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|wire_pll1_clk[0] ; PLL_1 ; 104 ; 0 ; Global Clock ; GCLK4 ; -- ; +; spi_master_2164:u_spi_master_2164|cs_n ; FF_X1_Y9_N31 ; 31 ; 0 ; Global Clock ; GCLK1 ; -- ; ++---------------------------------------------------------------------------------------------+--------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ + + ++------------------------------------------------+ +; Routing Usage Summary ; ++-----------------------+------------------------+ +; Routing Resource Type ; Usage ; ++-----------------------+------------------------+ +; Block interconnects ; 171 / 27,275 ( < 1 % ) ; +; C16 interconnects ; 2 / 1,240 ( < 1 % ) ; +; C4 interconnects ; 70 / 20,832 ( < 1 % ) ; +; Direct links ; 47 / 27,275 ( < 1 % ) ; +; Global clocks ; 2 / 10 ( 20 % ) ; +; Local interconnects ; 132 / 8,064 ( 2 % ) ; +; R24 interconnects ; 10 / 1,320 ( < 1 % ) ; +; R4 interconnects ; 91 / 28,560 ( < 1 % ) ; ++-----------------------+------------------------+ + + ++----------------------------------------------------------------------------+ +; LAB Logic Elements ; ++---------------------------------------------+------------------------------+ +; Number of Logic Elements (Average = 12.20) ; Number of LABs (Total = 15) ; ++---------------------------------------------+------------------------------+ +; 1 ; 3 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 2 ; +; 13 ; 0 ; +; 14 ; 1 ; +; 15 ; 2 ; +; 16 ; 7 ; ++---------------------------------------------+------------------------------+ + + ++-------------------------------------------------------------------+ +; LAB-wide Signals ; ++------------------------------------+------------------------------+ +; LAB-wide Signals (Average = 2.00) ; Number of LABs (Total = 15) ; ++------------------------------------+------------------------------+ +; 1 Async. clear ; 10 ; +; 1 Clock ; 12 ; +; 1 Clock enable ; 3 ; +; 2 Clock enables ; 3 ; +; 2 Clocks ; 2 ; ++------------------------------------+------------------------------+ + + ++-----------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++----------------------------------------------+------------------------------+ +; Number of Signals Sourced (Average = 20.40) ; Number of LABs (Total = 15) ; ++----------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 2 ; +; 2 ; 1 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; +; 17 ; 0 ; +; 18 ; 1 ; +; 19 ; 1 ; +; 20 ; 0 ; +; 21 ; 0 ; +; 22 ; 0 ; +; 23 ; 3 ; +; 24 ; 2 ; +; 25 ; 1 ; +; 26 ; 0 ; +; 27 ; 0 ; +; 28 ; 1 ; +; 29 ; 0 ; +; 30 ; 0 ; +; 31 ; 1 ; +; 32 ; 2 ; ++----------------------------------------------+------------------------------+ + + ++--------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+------------------------------+ +; Number of Signals Sourced Out (Average = 7.20) ; Number of LABs (Total = 15) ; ++-------------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 3 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 3 ; +; 5 ; 2 ; +; 6 ; 1 ; +; 7 ; 1 ; +; 8 ; 0 ; +; 9 ; 2 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 1 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 1 ; +; 17 ; 0 ; +; 18 ; 0 ; +; 19 ; 0 ; +; 20 ; 0 ; +; 21 ; 0 ; +; 22 ; 0 ; +; 23 ; 0 ; +; 24 ; 1 ; ++-------------------------------------------------+------------------------------+ + + ++-----------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++----------------------------------------------+------------------------------+ +; Number of Distinct Inputs (Average = 10.13) ; Number of LABs (Total = 15) ; ++----------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 3 ; +; 4 ; 1 ; +; 5 ; 2 ; +; 6 ; 0 ; +; 7 ; 1 ; +; 8 ; 1 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 2 ; +; 13 ; 1 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; +; 17 ; 0 ; +; 18 ; 0 ; +; 19 ; 0 ; +; 20 ; 0 ; +; 21 ; 0 ; +; 22 ; 0 ; +; 23 ; 1 ; +; 24 ; 0 ; +; 25 ; 1 ; +; 26 ; 0 ; +; 27 ; 0 ; +; 28 ; 0 ; +; 29 ; 1 ; ++----------------------------------------------+------------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 30 ; +; Number of I/O Rules Passed ; 9 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 21 ; ++----------------------------------+-------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+ +; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ; +; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength or Termination assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Total Pass ; 13 ; 0 ; 13 ; 0 ; 0 ; 13 ; 13 ; 0 ; 13 ; 13 ; 0 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 13 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 0 ; 13 ; 0 ; 13 ; 13 ; 0 ; 0 ; 13 ; 0 ; 0 ; 13 ; 13 ; 13 ; 13 ; 9 ; 13 ; 13 ; 9 ; 13 ; 13 ; 13 ; 13 ; 13 ; 13 ; 13 ; 13 ; 13 ; 0 ; 13 ; 13 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; mosi ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; cs_n ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; sclk ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; MOSI_ESP32 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; cs_ESP32 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; sclk_ESP32 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tx ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; test_flag_led ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; convert_flag_led ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; test_flag ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; rst_n ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; sys_clk ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; miso ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ + + ++-------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Internal Configuration ; +; Enable Error Detection CRC_ERROR pin ; Off ; +; Enable open drain on CRC_ERROR pin ; Off ; +; Enable nCONFIG, nSTATUS, and CONF_DONE pins ; On ; +; Enable JTAG pin sharing ; Off ; +; Enable nCE pin ; Off ; +; Enable CONFIG_SEL pin ; On ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; Data[0] ; Unreserved ; +; Data[1]/ASDO ; Unreserved ; +; FLASH_nCE/nCSO ; Unreserved ; +; DCLK ; Unreserved ; ++------------------------------------------------------------------+------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 C ; +; High Junction Temperature ; 85 C ; ++---------------------------+--------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing Summary ; ++----------------------------------------------------------+----------------------------------------------------------+-------------------+ +; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; ++----------------------------------------------------------+----------------------------------------------------------+-------------------+ +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 2.4 ; ++----------------------------------------------------------+----------------------------------------------------------+-------------------+ +Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. +This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer. + + ++-----------------------------------------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing Details ; ++-------------------------------------+-------------------------------------+-------------------+ +; Source Register ; Destination Register ; Delay Added in ns ; ++-------------------------------------+-------------------------------------+-------------------+ +; sent_data[0] ; uart_tx:u_uart_pc|data_to_send[0] ; 0.132 ; +; sent_data[1] ; uart_tx:u_uart_pc|data_to_send[1] ; 0.132 ; +; sent_data[2] ; uart_tx:u_uart_pc|data_to_send[2] ; 0.132 ; +; sent_data[3] ; uart_tx:u_uart_pc|data_to_send[3] ; 0.132 ; +; sent_data[4] ; uart_tx:u_uart_pc|data_to_send[4] ; 0.132 ; +; sent_data[5] ; uart_tx:u_uart_pc|data_to_send[5] ; 0.132 ; +; sent_data[6] ; uart_tx:u_uart_pc|data_to_send[6] ; 0.132 ; +; sent_data[7] ; uart_tx:u_uart_pc|data_to_send[7] ; 0.132 ; +; uart_tx:u_uart_pc|tx_bit_counter[0] ; uart_tx:u_uart_pc|tx_bit_counter[2] ; 0.126 ; +; uart_tx:u_uart_pc|tx_state.0001 ; uart_tx:u_uart_pc|tx_shift_reg[8] ; 0.110 ; +; sent_data[8] ; uart_tx:u_uart_pc|data_to_send[0] ; 0.094 ; +; sent_data[9] ; uart_tx:u_uart_pc|data_to_send[1] ; 0.094 ; +; sent_data[10] ; uart_tx:u_uart_pc|data_to_send[2] ; 0.094 ; +; sent_data[11] ; uart_tx:u_uart_pc|data_to_send[3] ; 0.094 ; +; sent_data[12] ; uart_tx:u_uart_pc|data_to_send[4] ; 0.094 ; +; sent_data[13] ; uart_tx:u_uart_pc|data_to_send[5] ; 0.094 ; +; sent_data[14] ; uart_tx:u_uart_pc|data_to_send[6] ; 0.094 ; +; sent_data[15] ; uart_tx:u_uart_pc|data_to_send[7] ; 0.094 ; +; uart_tx:u_uart_pc|tx_bit_counter[1] ; uart_tx:u_uart_pc|tx_bit_counter[2] ; 0.026 ; ++-------------------------------------+-------------------------------------+-------------------+ +Note: This table only shows the top 19 path(s) that have the largest delay added for hold. + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Info (20032): Parallel compilation is enabled and will use up to 4 processors +Info (119006): Selected device 10M08SAM153C8G for design "intan_m10" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (15535): Implemented PLL "clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|pll1" as MAX 10 PLL type File: E:/FPGA/puart2/db/clk_gen_altpll.v Line: 43 + Info (15099): Implementing clock multiplication of 6, clock division of 625, and phase shift of 0 degrees (0 ps) for clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|wire_pll1_clk[0] port File: E:/FPGA/puart2/db/clk_gen_altpll.v Line: 43 +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Critical Warning (16562): Review the Power Analyzer report file (.pow.rpt) to ensure your design is within the maximum power utilization limit of the single power-supply target device and to avoid functional failures. +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info (176445): Device 10M08SAM153C8GES is compatible + Info (176445): Device 10M04SAM153C8G is compatible +Info (169124): Fitter converted 8 user pins into dedicated programming pins + Info (169125): Pin ~ALTERA_TMS~ is reserved at location G1 + Info (169125): Pin ~ALTERA_TCK~ is reserved at location J1 + Info (169125): Pin ~ALTERA_TDI~ is reserved at location H5 + Info (169125): Pin ~ALTERA_TDO~ is reserved at location H4 + Info (169125): Pin ~ALTERA_CONFIG_SEL~ is reserved at location D8 + Info (169125): Pin ~ALTERA_nCONFIG~ is reserved at location E8 + Info (169125): Pin ~ALTERA_nSTATUS~ is reserved at location D6 + Info (169125): Pin ~ALTERA_CONF_DONE~ is reserved at location E6 +Info (169141): DATA[0] dual-purpose pin not reserved +Info (12825): Data[1]/ASDO dual-purpose pin not reserved +Info (12825): nCSO dual-purpose pin not reserved +Info (12825): DCLK dual-purpose pin not reserved +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Critical Warning (332012): Synopsys Design Constraints File file not found: 'intan_m10.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained generated clocks found in the design +Info (332144): No user constrained base clocks found in the design +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (176353): Automatically promoted node clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|wire_pll1_clk[0] (placed in counter C1 of PLL_1) File: E:/FPGA/puart2/db/clk_gen_altpll.v Line: 77 + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4 +Info (176353): Automatically promoted node spi_master_2164:u_spi_master_2164|cs_n File: E:/FPGA/puart2/spi_master_2164.v Line: 11 + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock + Info (176356): Following destination nodes may be non-global or may not use global or regional clocks + Info (176357): Destination node cs_n~output File: E:/FPGA/puart2/ddr_ctrl.v Line: 9 +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 +Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X10_Y0 to location X20_Y12 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped +Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 +Info (11888): Total time spent on timing analysis during the Fitter is 0.15 seconds. +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01 +Warning (169177): 4 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing MAX 10 Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems. + Info (169178): Pin test_flag uses I/O standard 3.3-V LVCMOS at J12 File: E:/FPGA/puart2/ddr_ctrl.v Line: 4 + Info (169178): Pin rst_n uses I/O standard 3.3-V LVCMOS at J14 File: E:/FPGA/puart2/ddr_ctrl.v Line: 3 + Info (169178): Pin sys_clk uses I/O standard 3.3-V LVCMOS at J5 File: E:/FPGA/puart2/ddr_ctrl.v Line: 2 + Info (169178): Pin miso uses I/O standard 3.3-V LVCMOS at P4 File: E:/FPGA/puart2/ddr_ctrl.v Line: 7 +Warning (169202): Inconsistent VCCIO across multiple banks of configuration pins. The configuration pins are contained in 2 banks in 'Internal Configuration' configuration scheme and there are 2 different VCCIOs. +Info (144001): Generated suppressed messages file E:/FPGA/puart2/output_files/intan_m10.fit.smsg +Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings + Info: Peak virtual memory: 5547 megabytes + Info: Processing ended: Thu Dec 11 18:00:31 2025 + Info: Elapsed time: 00:00:05 + Info: Total CPU time (on all processors): 00:00:06 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in E:/FPGA/puart2/output_files/intan_m10.fit.smsg. + + diff --git a/puart2/output_files/intan_m10.fit.smsg b/puart2/output_files/intan_m10.fit.smsg new file mode 100644 index 0000000..7121cbb --- /dev/null +++ b/puart2/output_files/intan_m10.fit.smsg @@ -0,0 +1,8 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/puart2/output_files/intan_m10.fit.summary b/puart2/output_files/intan_m10.fit.summary new file mode 100644 index 0000000..82d8893 --- /dev/null +++ b/puart2/output_files/intan_m10.fit.summary @@ -0,0 +1,18 @@ +Fitter Status : Successful - Thu Dec 11 18:00:31 2025 +Quartus Prime Version : 17.1.0 Build 590 10/25/2017 SJ Lite Edition +Revision Name : intan_m10 +Top-level Entity Name : ddr_ctrl +Family : MAX 10 +Device : 10M08SAM153C8G +Timing Models : Final +Total logic elements : 183 / 8,064 ( 2 % ) + Total combinational functions : 123 / 8,064 ( 2 % ) + Dedicated logic registers : 135 / 8,064 ( 2 % ) +Total registers : 135 +Total pins : 13 / 112 ( 12 % ) +Total virtual pins : 0 +Total memory bits : 0 / 387,072 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 1 / 1 ( 100 % ) +UFM blocks : 0 / 1 ( 0 % ) +ADC blocks : 0 / 1 ( 0 % ) diff --git a/puart2/output_files/intan_m10.flow.rpt b/puart2/output_files/intan_m10.flow.rpt new file mode 100644 index 0000000..3a979d7 --- /dev/null +++ b/puart2/output_files/intan_m10.flow.rpt @@ -0,0 +1,136 @@ +Flow report for intan_m10 +Thu Dec 11 18:00:41 2025 +Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2017 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++----------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+---------------------------------------------+ +; Flow Status ; Successful - Thu Dec 11 18:00:36 2025 ; +; Quartus Prime Version ; 17.1.0 Build 590 10/25/2017 SJ Lite Edition ; +; Revision Name ; intan_m10 ; +; Top-level Entity Name ; ddr_ctrl ; +; Family ; MAX 10 ; +; Device ; 10M08SAM153C8G ; +; Timing Models ; Final ; +; Total logic elements ; 183 / 8,064 ( 2 % ) ; +; Total combinational functions ; 123 / 8,064 ( 2 % ) ; +; Dedicated logic registers ; 135 / 8,064 ( 2 % ) ; +; Total registers ; 135 ; +; Total pins ; 13 / 112 ( 12 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 387,072 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 48 ( 0 % ) ; +; Total PLLs ; 1 / 1 ( 100 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 1 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 12/11/2025 18:00:16 ; +; Main task ; Compilation ; +; Revision Name ; intan_m10 ; ++-------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; COMPILER_SIGNATURE_ID ; 92384129777849.176544721619224 ; -- ; -- ; -- ; +; FLOW_ENABLE_POWER_ANALYZER ; On ; Off ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; MISC_FILE ; clk_gen_inst.v ; -- ; -- ; -- ; +; MISC_FILE ; clk_gen_bb.v ; -- ; -- ; -- ; +; MISC_FILE ; clk_gen.ppf ; -- ; -- ; -- ; +; NUM_PARALLEL_PROCESSORS ; 4 ; -- ; -- ; -- ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; ddr_ctrl ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; ddr_ctrl ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; ddr_ctrl ; Top ; +; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ; +; POWER_DEFAULT_INPUT_IO_TOGGLE_RATE ; 12.5 % ; 12.5% ; -- ; -- ; +; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; +; TOP_LEVEL_ENTITY ; ddr_ctrl ; intan_m10 ; -- ; -- ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:10 ; 1.0 ; 4766 MB ; 00:00:21 ; +; Fitter ; 00:00:05 ; 1.1 ; 5547 MB ; 00:00:06 ; +; Assembler ; 00:00:02 ; 1.0 ; 4671 MB ; 00:00:01 ; +; Power Analyzer ; 00:00:01 ; 1.1 ; 4812 MB ; 00:00:02 ; +; TimeQuest Timing Analyzer ; 00:00:04 ; 1.1 ; 4784 MB ; 00:00:03 ; +; Total ; 00:00:22 ; -- ; -- ; 00:00:33 ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++-----------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++---------------------------+------------------+------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++---------------------------+------------------+------------+------------+----------------+ +; Analysis & Synthesis ; LAPTOP-DER6L7FD ; Windows 10 ; 10.0 ; x86_64 ; +; Fitter ; LAPTOP-DER6L7FD ; Windows 10 ; 10.0 ; x86_64 ; +; Assembler ; LAPTOP-DER6L7FD ; Windows 10 ; 10.0 ; x86_64 ; +; Power Analyzer ; LAPTOP-DER6L7FD ; Windows 10 ; 10.0 ; x86_64 ; +; TimeQuest Timing Analyzer ; LAPTOP-DER6L7FD ; Windows 10 ; 10.0 ; x86_64 ; ++---------------------------+------------------+------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off intan_m10 -c intan_m10 +quartus_fit --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10 +quartus_asm --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10 +quartus_pow --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10 +quartus_sta intan_m10 -c intan_m10 + + + diff --git a/puart2/output_files/intan_m10.jdi b/puart2/output_files/intan_m10.jdi new file mode 100644 index 0000000..386e7d3 --- /dev/null +++ b/puart2/output_files/intan_m10.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/puart2/output_files/intan_m10.map.rpt b/puart2/output_files/intan_m10.map.rpt new file mode 100644 index 0000000..bcaf6b9 --- /dev/null +++ b/puart2/output_files/intan_m10.map.rpt @@ -0,0 +1,998 @@ +Analysis & Synthesis report for intan_m10 +Thu Dec 11 18:00:25 2025 +Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. Analysis & Synthesis IP Cores Summary + 9. State Machine - |ddr_ctrl|state_top + 10. State Machine - |ddr_ctrl|uart_tx:u_uart_pc|byte_select + 11. State Machine - |ddr_ctrl|uart_tx:u_uart_pc|tx_state + 12. State Machine - |ddr_ctrl|spi_master_esp32:tranfer|state + 13. Registers Removed During Synthesis + 14. Removed Registers Triggering Further Register Optimizations + 15. General Register Statistics + 16. Inverted Register Statistics + 17. Multiplexer Restructuring Statistics (Restructuring Performed) + 18. Parameter Settings for User Entity Instance: Top-level Entity: |ddr_ctrl + 19. Parameter Settings for User Entity Instance: clk_gen:clk_gen_inst|altpll:altpll_component + 20. Parameter Settings for User Entity Instance: uart_tx:u_uart_pc + 21. altpll Parameter Settings by Entity Instance + 22. Port Connectivity Checks: "spi_master_2164:u_spi_master_2164" + 23. Port Connectivity Checks: "clk_gen:clk_gen_inst" + 24. Post-Synthesis Netlist Statistics for Top Partition + 25. Elapsed Time Per Partition + 26. Analysis & Synthesis Messages + 27. Analysis & Synthesis Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2017 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++----------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+---------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Thu Dec 11 18:00:25 2025 ; +; Quartus Prime Version ; 17.1.0 Build 590 10/25/2017 SJ Lite Edition ; +; Revision Name ; intan_m10 ; +; Top-level Entity Name ; ddr_ctrl ; +; Family ; MAX 10 ; +; Total logic elements ; 198 ; +; Total combinational functions ; 121 ; +; Dedicated logic registers ; 135 ; +; Total registers ; 135 ; +; Total pins ; 13 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 1 ; +; UFM blocks ; 0 ; +; ADC blocks ; 0 ; ++------------------------------------+---------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; 10M08SAM153C8G ; ; +; Top-level entity name ; ddr_ctrl ; intan_m10 ; +; Family name ; MAX 10 ; Cyclone V ; +; Maximum processors allowed for parallel compilation ; 4 ; ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM Block Balancing ; On ; On ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; ++----------------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 0.0% ; ++----------------------------+-------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------+------------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------------+------------------------------------------------------------------+---------+ +; spi_master_2164.v ; yes ; User Verilog HDL File ; E:/FPGA/puart2/spi_master_2164.v ; ; +; ddr_ctrl.v ; yes ; User Verilog HDL File ; E:/FPGA/puart2/ddr_ctrl.v ; ; +; clk_gen.v ; yes ; User Wizard-Generated File ; E:/FPGA/puart2/clk_gen.v ; ; +; spi_master_esp32.v ; yes ; User Verilog HDL File ; E:/FPGA/puart2/spi_master_esp32.v ; ; +; uart_tx.v ; yes ; User Verilog HDL File ; E:/FPGA/puart2/uart_tx.v ; ; +; altpll.tdf ; yes ; Megafunction ; e:/quartuslite/quartus/libraries/megafunctions/altpll.tdf ; ; +; aglobal171.inc ; yes ; Megafunction ; e:/quartuslite/quartus/libraries/megafunctions/aglobal171.inc ; ; +; stratix_pll.inc ; yes ; Megafunction ; e:/quartuslite/quartus/libraries/megafunctions/stratix_pll.inc ; ; +; stratixii_pll.inc ; yes ; Megafunction ; e:/quartuslite/quartus/libraries/megafunctions/stratixii_pll.inc ; ; +; cycloneii_pll.inc ; yes ; Megafunction ; e:/quartuslite/quartus/libraries/megafunctions/cycloneii_pll.inc ; ; +; db/clk_gen_altpll.v ; yes ; Auto-Generated Megafunction ; E:/FPGA/puart2/db/clk_gen_altpll.v ; ; ++----------------------------------+-----------------+------------------------------+------------------------------------------------------------------+---------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+---------------------------------------------------------------------------------------------+ +; Resource ; Usage ; ++---------------------------------------------+---------------------------------------------------------------------------------------------+ +; Estimated Total logic elements ; 198 ; +; ; ; +; Total combinational functions ; 121 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 60 ; +; -- 3 input functions ; 30 ; +; -- <=2 input functions ; 31 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 100 ; +; -- arithmetic mode ; 21 ; +; ; ; +; Total registers ; 135 ; +; -- Dedicated logic registers ; 135 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 13 ; +; ; ; +; Embedded Multiplier 9-bit elements ; 0 ; +; ; ; +; Total PLLs ; 1 ; +; -- PLLs ; 1 ; +; ; ; +; Maximum fan-out node ; clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|wire_pll1_clk[0] ; +; Maximum fan-out ; 105 ; +; Total fan-out ; 843 ; +; Average fan-out ; 2.98 ; ++---------------------------------------------+---------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++------------------------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+--------------------------------------------------------------------------------------+-----------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ; ++------------------------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+--------------------------------------------------------------------------------------+-----------------+--------------+ +; |ddr_ctrl ; 121 (33) ; 135 (52) ; 0 ; 0 ; 0 ; 0 ; 0 ; 13 ; 0 ; 0 ; |ddr_ctrl ; ddr_ctrl ; work ; +; |clk_gen:clk_gen_inst| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ddr_ctrl|clk_gen:clk_gen_inst ; clk_gen ; work ; +; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ddr_ctrl|clk_gen:clk_gen_inst|altpll:altpll_component ; altpll ; work ; +; |clk_gen_altpll:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ddr_ctrl|clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated ; clk_gen_altpll ; work ; +; |spi_master_2164:u_spi_master_2164| ; 37 (37) ; 43 (43) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ddr_ctrl|spi_master_2164:u_spi_master_2164 ; spi_master_2164 ; work ; +; |uart_tx:u_uart_pc| ; 51 (51) ; 40 (40) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ddr_ctrl|uart_tx:u_uart_pc ; uart_tx ; work ; ++------------------------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+--------------------------------------------------------------------------------------+-----------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis IP Cores Summary ; ++--------+--------------+---------+--------------+--------------+--------------------------------+-----------------+ +; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ; ++--------+--------------+---------+--------------+--------------+--------------------------------+-----------------+ +; Altera ; ALTPLL ; 17.1 ; N/A ; N/A ; |ddr_ctrl|clk_gen:clk_gen_inst ; clk_gen.v ; ++--------+--------------+---------+--------------+--------------+--------------------------------+-----------------+ + + +Encoding Type: One-Hot ++------------------------------------------------------------------------------------------------+ +; State Machine - |ddr_ctrl|state_top ; ++---------------------+---------------------+-----------------+-----------------+----------------+ +; Name ; state_top.SEND_uart ; state_top.SEND2 ; state_top.SEND1 ; state_top.IDLE ; ++---------------------+---------------------+-----------------+-----------------+----------------+ +; state_top.IDLE ; 0 ; 0 ; 0 ; 0 ; +; state_top.SEND1 ; 0 ; 0 ; 1 ; 1 ; +; state_top.SEND2 ; 0 ; 1 ; 0 ; 1 ; +; state_top.SEND_uart ; 1 ; 0 ; 0 ; 1 ; ++---------------------+---------------------+-----------------+-----------------+----------------+ + + +Encoding Type: One-Hot ++---------------------------------------------------------+ +; State Machine - |ddr_ctrl|uart_tx:u_uart_pc|byte_select ; ++----------------+----------------------------------------+ +; Name ; byte_select.01 ; ++----------------+----------------------------------------+ +; byte_select.00 ; 0 ; +; byte_select.01 ; 1 ; ++----------------+----------------------------------------+ + + +Encoding Type: One-Hot ++------------------------------------------------------+ +; State Machine - |ddr_ctrl|uart_tx:u_uart_pc|tx_state ; ++---------------+--------------------------------------+ +; Name ; tx_state.0001 ; ++---------------+--------------------------------------+ +; tx_state.0000 ; 0 ; +; tx_state.0001 ; 1 ; ++---------------+--------------------------------------+ + + +Encoding Type: One-Hot ++-----------------------------------------------------------+ +; State Machine - |ddr_ctrl|spi_master_esp32:tranfer|state ; ++----------------+------------+------------+----------------+ +; Name ; state.IDLE ; state.DONE ; state.TRANSFER ; ++----------------+------------+------------+----------------+ +; state.IDLE ; 0 ; 0 ; 0 ; +; state.TRANSFER ; 1 ; 0 ; 1 ; +; state.DONE ; 1 ; 1 ; 0 ; ++----------------+------------+------------+----------------+ + + ++--------------------------------------------------------------------------------------------+ +; Registers Removed During Synthesis ; ++----------------------------------------------+---------------------------------------------+ +; Register name ; Reason for Removal ; ++----------------------------------------------+---------------------------------------------+ +; uart_tx:u_uart_pc|tx_shift_reg[9] ; Stuck at VCC due to stuck port data_in ; +; state_top~8 ; Lost fanout ; +; state_top~9 ; Lost fanout ; +; uart_tx:u_uart_pc|byte_select~6 ; Lost fanout ; +; uart_tx:u_uart_pc|tx_state~7 ; Lost fanout ; +; uart_tx:u_uart_pc|tx_state~8 ; Lost fanout ; +; uart_tx:u_uart_pc|tx_state~9 ; Lost fanout ; +; state_top.SEND2 ; Stuck at GND due to stuck port data_in ; +; start2 ; Stuck at GND due to stuck port data_in ; +; spi_master_esp32:tranfer|shift_reg[13] ; Stuck at GND due to stuck port clock_enable ; +; spi_master_esp32:tranfer|bit_cnt[0..3] ; Stuck at GND due to stuck port clock_enable ; +; spi_master_esp32:tranfer|done ; Stuck at GND due to stuck port clock_enable ; +; spi_master_esp32:tranfer|shift_reg[0..12,15] ; Stuck at GND due to stuck port clock_enable ; +; spi_master_esp32:tranfer|cs ; Stuck at VCC due to stuck port clock_enable ; +; spi_master_esp32:tranfer|sclk_reg ; Stuck at GND due to stuck port clock_enable ; +; spi_master_esp32:tranfer|shift_reg[14] ; Stuck at GND due to stuck port clock_enable ; +; spi_master_esp32:tranfer|state.TRANSFER ; Stuck at GND due to stuck port data_in ; +; spi_master_esp32:tranfer|state.DONE ; Stuck at GND due to stuck port data_in ; +; spi_master_esp32:tranfer|state.IDLE ; Stuck at GND due to stuck port data_in ; +; Total Number of Removed Registers = 35 ; ; ++----------------------------------------------+---------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Removed Registers Triggering Further Register Optimizations ; ++-----------------+---------------------------+--------------------------------------------------------------------------------------+ +; Register name ; Reason for Removal ; Registers Removed due to This Register ; ++-----------------+---------------------------+--------------------------------------------------------------------------------------+ +; state_top.SEND2 ; Stuck at GND ; start2, spi_master_esp32:tranfer|shift_reg[13], spi_master_esp32:tranfer|bit_cnt[3], ; +; ; due to stuck port data_in ; spi_master_esp32:tranfer|bit_cnt[2], spi_master_esp32:tranfer|bit_cnt[1], ; +; ; ; spi_master_esp32:tranfer|bit_cnt[0], spi_master_esp32:tranfer|done, ; +; ; ; spi_master_esp32:tranfer|shift_reg[12], spi_master_esp32:tranfer|shift_reg[11], ; +; ; ; spi_master_esp32:tranfer|shift_reg[10], spi_master_esp32:tranfer|shift_reg[9], ; +; ; ; spi_master_esp32:tranfer|shift_reg[8], spi_master_esp32:tranfer|shift_reg[7], ; +; ; ; spi_master_esp32:tranfer|shift_reg[6], spi_master_esp32:tranfer|shift_reg[5], ; +; ; ; spi_master_esp32:tranfer|shift_reg[4], spi_master_esp32:tranfer|shift_reg[3], ; +; ; ; spi_master_esp32:tranfer|shift_reg[2], spi_master_esp32:tranfer|shift_reg[1], ; +; ; ; spi_master_esp32:tranfer|shift_reg[0], spi_master_esp32:tranfer|shift_reg[15], ; +; ; ; spi_master_esp32:tranfer|cs, spi_master_esp32:tranfer|sclk_reg, ; +; ; ; spi_master_esp32:tranfer|shift_reg[14] ; ++-----------------+---------------------------+--------------------------------------------------------------------------------------+ + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 135 ; +; Number of registers using Synchronous Clear ; 7 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 90 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 68 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++---------------------------------------------------+ +; Inverted Register Statistics ; ++-----------------------------------------+---------+ +; Inverted Register ; Fan out ; ++-----------------------------------------+---------+ +; spi_master_2164:u_spi_master_2164|cs_n ; 32 ; +; uart_tx:u_uart_pc|tx_shift_reg[0] ; 1 ; +; state[0] ; 3 ; +; uart_tx:u_uart_pc|tx_shift_reg[1] ; 1 ; +; uart_tx:u_uart_pc|tx_shift_reg[2] ; 1 ; +; uart_tx:u_uart_pc|tx_shift_reg[3] ; 1 ; +; uart_tx:u_uart_pc|tx_shift_reg[4] ; 1 ; +; uart_tx:u_uart_pc|tx_shift_reg[5] ; 1 ; +; uart_tx:u_uart_pc|tx_shift_reg[6] ; 1 ; +; uart_tx:u_uart_pc|tx_shift_reg[7] ; 1 ; +; uart_tx:u_uart_pc|tx_shift_reg[8] ; 1 ; +; Total number of inverted registers = 11 ; ; ++-----------------------------------------+---------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Restructuring Statistics (Restructuring Performed) ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------+ +; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------+ +; 4:1 ; 15 bits ; 30 LEs ; 15 LEs ; 15 LEs ; Yes ; |ddr_ctrl|spi_master_esp32:tranfer|shift_reg[2] ; +; 3:1 ; 7 bits ; 14 LEs ; 7 LEs ; 7 LEs ; Yes ; |ddr_ctrl|uart_tx:u_uart_pc|tx_shift_reg[4] ; +; 7:1 ; 4 bits ; 16 LEs ; 8 LEs ; 8 LEs ; No ; |ddr_ctrl|Selector3 ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------+ + + ++--------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Top-level Entity: |ddr_ctrl ; ++----------------+-------+-------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-------------------------------------------------+ +; IDLE ; 00 ; Unsigned Binary ; +; SEND1 ; 01 ; Unsigned Binary ; +; SEND2 ; 10 ; Unsigned Binary ; +; SEND_uart ; 11 ; Unsigned Binary ; ++----------------+-------+-------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: clk_gen:clk_gen_inst|altpll:altpll_component ; ++-------------------------------+---------------------------+-------------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------------+---------------------------+-------------------------------+ +; OPERATION_MODE ; NORMAL ; Untyped ; +; PLL_TYPE ; AUTO ; Untyped ; +; LPM_HINT ; CBX_MODULE_PREFIX=clk_gen ; Untyped ; +; QUALIFY_CONF_DONE ; OFF ; Untyped ; +; COMPENSATE_CLOCK ; CLK0 ; Untyped ; +; SCAN_CHAIN ; LONG ; Untyped ; +; PRIMARY_CLOCK ; INCLK0 ; Untyped ; +; INCLK0_INPUT_FREQUENCY ; 83333 ; Signed Integer ; +; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ; +; GATE_LOCK_SIGNAL ; NO ; Untyped ; +; GATE_LOCK_COUNTER ; 0 ; Untyped ; +; LOCK_HIGH ; 1 ; Untyped ; +; LOCK_LOW ; 1 ; Untyped ; +; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ; +; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ; +; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ; +; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ; +; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ; +; SKIP_VCO ; OFF ; Untyped ; +; SWITCH_OVER_COUNTER ; 0 ; Untyped ; +; SWITCH_OVER_TYPE ; AUTO ; Untyped ; +; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ; +; BANDWIDTH ; 0 ; Untyped ; +; BANDWIDTH_TYPE ; AUTO ; Untyped ; +; SPREAD_FREQUENCY ; 0 ; Untyped ; +; DOWN_SPREAD ; 0 ; Untyped ; +; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ; +; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ; +; CLK9_MULTIPLY_BY ; 0 ; Untyped ; +; CLK8_MULTIPLY_BY ; 0 ; Untyped ; +; CLK7_MULTIPLY_BY ; 0 ; Untyped ; +; CLK6_MULTIPLY_BY ; 0 ; Untyped ; +; CLK5_MULTIPLY_BY ; 1 ; Untyped ; +; CLK4_MULTIPLY_BY ; 1 ; Untyped ; +; CLK3_MULTIPLY_BY ; 1 ; Untyped ; +; CLK2_MULTIPLY_BY ; 1 ; Untyped ; +; CLK1_MULTIPLY_BY ; 12 ; Signed Integer ; +; CLK0_MULTIPLY_BY ; 6 ; Signed Integer ; +; CLK9_DIVIDE_BY ; 0 ; Untyped ; +; CLK8_DIVIDE_BY ; 0 ; Untyped ; +; CLK7_DIVIDE_BY ; 0 ; Untyped ; +; CLK6_DIVIDE_BY ; 0 ; Untyped ; +; CLK5_DIVIDE_BY ; 1 ; Untyped ; +; CLK4_DIVIDE_BY ; 1 ; Untyped ; +; CLK3_DIVIDE_BY ; 1 ; Untyped ; +; CLK2_DIVIDE_BY ; 1 ; Untyped ; +; CLK1_DIVIDE_BY ; 625 ; Signed Integer ; +; CLK0_DIVIDE_BY ; 625 ; Signed Integer ; +; CLK9_PHASE_SHIFT ; 0 ; Untyped ; +; CLK8_PHASE_SHIFT ; 0 ; Untyped ; +; CLK7_PHASE_SHIFT ; 0 ; Untyped ; +; CLK6_PHASE_SHIFT ; 0 ; Untyped ; +; CLK5_PHASE_SHIFT ; 0 ; Untyped ; +; CLK4_PHASE_SHIFT ; 0 ; Untyped ; +; CLK3_PHASE_SHIFT ; 0 ; Untyped ; +; CLK2_PHASE_SHIFT ; 0 ; Untyped ; +; CLK1_PHASE_SHIFT ; 0 ; Untyped ; +; CLK0_PHASE_SHIFT ; 0 ; Untyped ; +; CLK5_TIME_DELAY ; 0 ; Untyped ; +; CLK4_TIME_DELAY ; 0 ; Untyped ; +; CLK3_TIME_DELAY ; 0 ; Untyped ; +; CLK2_TIME_DELAY ; 0 ; Untyped ; +; CLK1_TIME_DELAY ; 0 ; Untyped ; +; CLK0_TIME_DELAY ; 0 ; Untyped ; +; CLK9_DUTY_CYCLE ; 50 ; Untyped ; +; CLK8_DUTY_CYCLE ; 50 ; Untyped ; +; CLK7_DUTY_CYCLE ; 50 ; Untyped ; +; CLK6_DUTY_CYCLE ; 50 ; Untyped ; +; CLK5_DUTY_CYCLE ; 50 ; Untyped ; +; CLK4_DUTY_CYCLE ; 50 ; Untyped ; +; CLK3_DUTY_CYCLE ; 50 ; Untyped ; +; CLK2_DUTY_CYCLE ; 50 ; Untyped ; +; CLK1_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; LOCK_WINDOW_UI ; 0.05 ; Untyped ; +; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ; +; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ; +; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ; +; DPA_MULTIPLY_BY ; 0 ; Untyped ; +; DPA_DIVIDE_BY ; 1 ; Untyped ; +; DPA_DIVIDER ; 0 ; Untyped ; +; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK3_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK2_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK1_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK0_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ; +; VCO_MULTIPLY_BY ; 0 ; Untyped ; +; VCO_DIVIDE_BY ; 0 ; Untyped ; +; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ; +; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ; +; VCO_MIN ; 0 ; Untyped ; +; VCO_MAX ; 0 ; Untyped ; +; VCO_CENTER ; 0 ; Untyped ; +; PFD_MIN ; 0 ; Untyped ; +; PFD_MAX ; 0 ; Untyped ; +; M_INITIAL ; 0 ; Untyped ; +; M ; 0 ; Untyped ; +; N ; 1 ; Untyped ; +; M2 ; 1 ; Untyped ; +; N2 ; 1 ; Untyped ; +; SS ; 1 ; Untyped ; +; C0_HIGH ; 0 ; Untyped ; +; C1_HIGH ; 0 ; Untyped ; +; C2_HIGH ; 0 ; Untyped ; +; C3_HIGH ; 0 ; Untyped ; +; C4_HIGH ; 0 ; Untyped ; +; C5_HIGH ; 0 ; Untyped ; +; C6_HIGH ; 0 ; Untyped ; +; C7_HIGH ; 0 ; Untyped ; +; C8_HIGH ; 0 ; Untyped ; +; C9_HIGH ; 0 ; Untyped ; +; C0_LOW ; 0 ; Untyped ; +; C1_LOW ; 0 ; Untyped ; +; C2_LOW ; 0 ; Untyped ; +; C3_LOW ; 0 ; Untyped ; +; C4_LOW ; 0 ; Untyped ; +; C5_LOW ; 0 ; Untyped ; +; C6_LOW ; 0 ; Untyped ; +; C7_LOW ; 0 ; Untyped ; +; C8_LOW ; 0 ; Untyped ; +; C9_LOW ; 0 ; Untyped ; +; C0_INITIAL ; 0 ; Untyped ; +; C1_INITIAL ; 0 ; Untyped ; +; C2_INITIAL ; 0 ; Untyped ; +; C3_INITIAL ; 0 ; Untyped ; +; C4_INITIAL ; 0 ; Untyped ; +; C5_INITIAL ; 0 ; Untyped ; +; C6_INITIAL ; 0 ; Untyped ; +; C7_INITIAL ; 0 ; Untyped ; +; C8_INITIAL ; 0 ; Untyped ; +; C9_INITIAL ; 0 ; Untyped ; +; C0_MODE ; BYPASS ; Untyped ; +; C1_MODE ; BYPASS ; Untyped ; +; C2_MODE ; BYPASS ; Untyped ; +; C3_MODE ; BYPASS ; Untyped ; +; C4_MODE ; BYPASS ; Untyped ; +; C5_MODE ; BYPASS ; Untyped ; +; C6_MODE ; BYPASS ; Untyped ; +; C7_MODE ; BYPASS ; Untyped ; +; C8_MODE ; BYPASS ; Untyped ; +; C9_MODE ; BYPASS ; Untyped ; +; C0_PH ; 0 ; Untyped ; +; C1_PH ; 0 ; Untyped ; +; C2_PH ; 0 ; Untyped ; +; C3_PH ; 0 ; Untyped ; +; C4_PH ; 0 ; Untyped ; +; C5_PH ; 0 ; Untyped ; +; C6_PH ; 0 ; Untyped ; +; C7_PH ; 0 ; Untyped ; +; C8_PH ; 0 ; Untyped ; +; C9_PH ; 0 ; Untyped ; +; L0_HIGH ; 1 ; Untyped ; +; L1_HIGH ; 1 ; Untyped ; +; G0_HIGH ; 1 ; Untyped ; +; G1_HIGH ; 1 ; Untyped ; +; G2_HIGH ; 1 ; Untyped ; +; G3_HIGH ; 1 ; Untyped ; +; E0_HIGH ; 1 ; Untyped ; +; E1_HIGH ; 1 ; Untyped ; +; E2_HIGH ; 1 ; Untyped ; +; E3_HIGH ; 1 ; Untyped ; +; L0_LOW ; 1 ; Untyped ; +; L1_LOW ; 1 ; Untyped ; +; G0_LOW ; 1 ; Untyped ; +; G1_LOW ; 1 ; Untyped ; +; G2_LOW ; 1 ; Untyped ; +; G3_LOW ; 1 ; Untyped ; +; E0_LOW ; 1 ; Untyped ; +; E1_LOW ; 1 ; Untyped ; +; E2_LOW ; 1 ; Untyped ; +; E3_LOW ; 1 ; Untyped ; +; L0_INITIAL ; 1 ; Untyped ; +; L1_INITIAL ; 1 ; Untyped ; +; G0_INITIAL ; 1 ; Untyped ; +; G1_INITIAL ; 1 ; Untyped ; +; G2_INITIAL ; 1 ; Untyped ; +; G3_INITIAL ; 1 ; Untyped ; +; E0_INITIAL ; 1 ; Untyped ; +; E1_INITIAL ; 1 ; Untyped ; +; E2_INITIAL ; 1 ; Untyped ; +; E3_INITIAL ; 1 ; Untyped ; +; L0_MODE ; BYPASS ; Untyped ; +; L1_MODE ; BYPASS ; Untyped ; +; G0_MODE ; BYPASS ; Untyped ; +; G1_MODE ; BYPASS ; Untyped ; +; G2_MODE ; BYPASS ; Untyped ; +; G3_MODE ; BYPASS ; Untyped ; +; E0_MODE ; BYPASS ; Untyped ; +; E1_MODE ; BYPASS ; Untyped ; +; E2_MODE ; BYPASS ; Untyped ; +; E3_MODE ; BYPASS ; Untyped ; +; L0_PH ; 0 ; Untyped ; +; L1_PH ; 0 ; Untyped ; +; G0_PH ; 0 ; Untyped ; +; G1_PH ; 0 ; Untyped ; +; G2_PH ; 0 ; Untyped ; +; G3_PH ; 0 ; Untyped ; +; E0_PH ; 0 ; Untyped ; +; E1_PH ; 0 ; Untyped ; +; E2_PH ; 0 ; Untyped ; +; E3_PH ; 0 ; Untyped ; +; M_PH ; 0 ; Untyped ; +; C1_USE_CASC_IN ; OFF ; Untyped ; +; C2_USE_CASC_IN ; OFF ; Untyped ; +; C3_USE_CASC_IN ; OFF ; Untyped ; +; C4_USE_CASC_IN ; OFF ; Untyped ; +; C5_USE_CASC_IN ; OFF ; Untyped ; +; C6_USE_CASC_IN ; OFF ; Untyped ; +; C7_USE_CASC_IN ; OFF ; Untyped ; +; C8_USE_CASC_IN ; OFF ; Untyped ; +; C9_USE_CASC_IN ; OFF ; Untyped ; +; CLK0_COUNTER ; G0 ; Untyped ; +; CLK1_COUNTER ; G0 ; Untyped ; +; CLK2_COUNTER ; G0 ; Untyped ; +; CLK3_COUNTER ; G0 ; Untyped ; +; CLK4_COUNTER ; G0 ; Untyped ; +; CLK5_COUNTER ; G0 ; Untyped ; +; CLK6_COUNTER ; E0 ; Untyped ; +; CLK7_COUNTER ; E1 ; Untyped ; +; CLK8_COUNTER ; E2 ; Untyped ; +; CLK9_COUNTER ; E3 ; Untyped ; +; L0_TIME_DELAY ; 0 ; Untyped ; +; L1_TIME_DELAY ; 0 ; Untyped ; +; G0_TIME_DELAY ; 0 ; Untyped ; +; G1_TIME_DELAY ; 0 ; Untyped ; +; G2_TIME_DELAY ; 0 ; Untyped ; +; G3_TIME_DELAY ; 0 ; Untyped ; +; E0_TIME_DELAY ; 0 ; Untyped ; +; E1_TIME_DELAY ; 0 ; Untyped ; +; E2_TIME_DELAY ; 0 ; Untyped ; +; E3_TIME_DELAY ; 0 ; Untyped ; +; M_TIME_DELAY ; 0 ; Untyped ; +; N_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK3_COUNTER ; E3 ; Untyped ; +; EXTCLK2_COUNTER ; E2 ; Untyped ; +; EXTCLK1_COUNTER ; E1 ; Untyped ; +; EXTCLK0_COUNTER ; E0 ; Untyped ; +; ENABLE0_COUNTER ; L0 ; Untyped ; +; ENABLE1_COUNTER ; L0 ; Untyped ; +; CHARGE_PUMP_CURRENT ; 2 ; Untyped ; +; LOOP_FILTER_R ; 1.000000 ; Untyped ; +; LOOP_FILTER_C ; 5 ; Untyped ; +; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ; +; LOOP_FILTER_R_BITS ; 9999 ; Untyped ; +; LOOP_FILTER_C_BITS ; 9999 ; Untyped ; +; VCO_POST_SCALE ; 0 ; Untyped ; +; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; INTENDED_DEVICE_FAMILY ; MAX 10 ; Untyped ; +; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA2 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ; +; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ; +; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ; +; PORT_CLK0 ; PORT_USED ; Untyped ; +; PORT_CLK1 ; PORT_USED ; Untyped ; +; PORT_CLK2 ; PORT_UNUSED ; Untyped ; +; PORT_CLK3 ; PORT_UNUSED ; Untyped ; +; PORT_CLK4 ; PORT_UNUSED ; Untyped ; +; PORT_CLK5 ; PORT_UNUSED ; Untyped ; +; PORT_CLK6 ; PORT_UNUSED ; Untyped ; +; PORT_CLK7 ; PORT_UNUSED ; Untyped ; +; PORT_CLK8 ; PORT_UNUSED ; Untyped ; +; PORT_CLK9 ; PORT_UNUSED ; Untyped ; +; PORT_SCANDATA ; PORT_UNUSED ; Untyped ; +; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ; +; PORT_SCANDONE ; PORT_UNUSED ; Untyped ; +; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ; +; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ; +; PORT_INCLK1 ; PORT_UNUSED ; Untyped ; +; PORT_INCLK0 ; PORT_USED ; Untyped ; +; PORT_FBIN ; PORT_UNUSED ; Untyped ; +; PORT_PLLENA ; PORT_UNUSED ; Untyped ; +; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ; +; PORT_ARESET ; PORT_UNUSED ; Untyped ; +; PORT_PFDENA ; PORT_UNUSED ; Untyped ; +; PORT_SCANCLK ; PORT_UNUSED ; Untyped ; +; PORT_SCANACLR ; PORT_UNUSED ; Untyped ; +; PORT_SCANREAD ; PORT_UNUSED ; Untyped ; +; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ; +; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_LOCKED ; PORT_UNUSED ; Untyped ; +; PORT_CONFIGUPDATE ; PORT_UNUSED ; Untyped ; +; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ; +; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ; +; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ; +; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ; +; PORT_SCANCLKENA ; PORT_UNUSED ; Untyped ; +; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ; +; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ; +; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ; +; M_TEST_SOURCE ; 5 ; Untyped ; +; C0_TEST_SOURCE ; 5 ; Untyped ; +; C1_TEST_SOURCE ; 5 ; Untyped ; +; C2_TEST_SOURCE ; 5 ; Untyped ; +; C3_TEST_SOURCE ; 5 ; Untyped ; +; C4_TEST_SOURCE ; 5 ; Untyped ; +; C5_TEST_SOURCE ; 5 ; Untyped ; +; C6_TEST_SOURCE ; 5 ; Untyped ; +; C7_TEST_SOURCE ; 5 ; Untyped ; +; C8_TEST_SOURCE ; 5 ; Untyped ; +; C9_TEST_SOURCE ; 5 ; Untyped ; +; CBXI_PARAMETER ; clk_gen_altpll ; Untyped ; +; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ; +; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ; +; WIDTH_CLOCK ; 5 ; Signed Integer ; +; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ; +; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ; +; DEVICE_FAMILY ; MAX 10 ; Untyped ; +; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ; +; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++-------------------------------+---------------------------+-------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: uart_tx:u_uart_pc ; ++----------------+--------+--------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+--------+--------------------------------------+ +; BAUD_RATE ; 115200 ; Signed Integer ; +; CLOCK_FREQ ; 115200 ; Signed Integer ; ++----------------+--------+--------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------+ +; altpll Parameter Settings by Entity Instance ; ++-------------------------------+----------------------------------------------+ +; Name ; Value ; ++-------------------------------+----------------------------------------------+ +; Number of entity instances ; 1 ; +; Entity Instance ; clk_gen:clk_gen_inst|altpll:altpll_component ; +; -- OPERATION_MODE ; NORMAL ; +; -- PLL_TYPE ; AUTO ; +; -- PRIMARY_CLOCK ; INCLK0 ; +; -- INCLK0_INPUT_FREQUENCY ; 83333 ; +; -- INCLK1_INPUT_FREQUENCY ; 0 ; +; -- VCO_MULTIPLY_BY ; 0 ; +; -- VCO_DIVIDE_BY ; 0 ; ++-------------------------------+----------------------------------------------+ + + ++---------------------------------------------------------------+ +; Port Connectivity Checks: "spi_master_2164:u_spi_master_2164" ; ++------+--------+----------+------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------+--------+----------+------------------------------------+ +; cnt ; Output ; Info ; Explicitly unconnected ; ++------+--------+----------+------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "clk_gen:clk_gen_inst" ; ++------+--------+----------+-------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------+--------+----------+-------------------------------------------------------------------------------------+ +; c1 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++------+--------+----------+-------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------+ +; Post-Synthesis Netlist Statistics for Top Partition ; ++-----------------------+-----------------------------+ +; Type ; Count ; ++-----------------------+-----------------------------+ +; boundary_port ; 13 ; +; cycloneiii_ff ; 135 ; +; CLR ; 58 ; +; CLR SCLR ; 7 ; +; ENA ; 43 ; +; ENA CLR ; 25 ; +; plain ; 2 ; +; cycloneiii_lcell_comb ; 126 ; +; arith ; 21 ; +; 2 data inputs ; 20 ; +; 3 data inputs ; 1 ; +; normal ; 105 ; +; 0 data inputs ; 2 ; +; 1 data inputs ; 7 ; +; 2 data inputs ; 7 ; +; 3 data inputs ; 29 ; +; 4 data inputs ; 60 ; +; cycloneiii_pll ; 1 ; +; ; ; +; Max LUT depth ; 8.00 ; +; Average LUT depth ; 3.04 ; ++-----------------------+-----------------------------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:00 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Analysis & Synthesis + Info: Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition + Info: Processing started: Thu Dec 11 18:00:15 2025 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off intan_m10 -c intan_m10 +Info (20032): Parallel compilation is enabled and will use up to 4 processors +Info (12021): Found 1 design units, including 1 entities, in source file spi_master_2164.v + Info (12023): Found entity 1: spi_master_2164 File: E:/FPGA/puart2/spi_master_2164.v Line: 1 +Info (12021): Found 1 design units, including 1 entities, in source file ddr_ctrl.v + Info (12023): Found entity 1: ddr_ctrl File: E:/FPGA/puart2/ddr_ctrl.v Line: 1 +Info (12021): Found 1 design units, including 1 entities, in source file clk_gen.v + Info (12023): Found entity 1: clk_gen File: E:/FPGA/puart2/clk_gen.v Line: 39 +Warning (12019): Can't analyze file -- file ../../20240625.v is missing +Info (12021): Found 1 design units, including 1 entities, in source file spi_master_esp32.v + Info (12023): Found entity 1: spi_master_esp32 File: E:/FPGA/puart2/spi_master_esp32.v Line: 1 +Info (12021): Found 1 design units, including 1 entities, in source file uart_tx.v + Info (12023): Found entity 1: uart_tx File: E:/FPGA/puart2/uart_tx.v Line: 1 +Info (12127): Elaborating entity "ddr_ctrl" for the top level hierarchy +Warning (10036): Verilog HDL or VHDL warning at ddr_ctrl.v(71): object "received_data" assigned a value but never read File: E:/FPGA/puart2/ddr_ctrl.v Line: 71 +Warning (10763): Verilog HDL warning at ddr_ctrl.v(153): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness File: E:/FPGA/puart2/ddr_ctrl.v Line: 153 +Warning (10208): Verilog HDL Case Statement warning at ddr_ctrl.v(153): honored full_case synthesis attribute - differences between design synthesis and simulation may occur File: E:/FPGA/puart2/ddr_ctrl.v Line: 153 +Info (12128): Elaborating entity "clk_gen" for hierarchy "clk_gen:clk_gen_inst" File: E:/FPGA/puart2/ddr_ctrl.v Line: 204 +Info (12128): Elaborating entity "altpll" for hierarchy "clk_gen:clk_gen_inst|altpll:altpll_component" File: E:/FPGA/puart2/clk_gen.v Line: 94 +Info (12130): Elaborated megafunction instantiation "clk_gen:clk_gen_inst|altpll:altpll_component" File: E:/FPGA/puart2/clk_gen.v Line: 94 +Info (12133): Instantiated megafunction "clk_gen:clk_gen_inst|altpll:altpll_component" with the following parameter: File: E:/FPGA/puart2/clk_gen.v Line: 94 + Info (12134): Parameter "bandwidth_type" = "AUTO" + Info (12134): Parameter "clk0_divide_by" = "625" + Info (12134): Parameter "clk0_duty_cycle" = "50" + Info (12134): Parameter "clk0_multiply_by" = "6" + Info (12134): Parameter "clk0_phase_shift" = "0" + Info (12134): Parameter "clk1_divide_by" = "625" + Info (12134): Parameter "clk1_duty_cycle" = "50" + Info (12134): Parameter "clk1_multiply_by" = "12" + Info (12134): Parameter "clk1_phase_shift" = "0" + Info (12134): Parameter "compensate_clock" = "CLK0" + Info (12134): Parameter "inclk0_input_frequency" = "83333" + Info (12134): Parameter "intended_device_family" = "MAX 10" + Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=clk_gen" + Info (12134): Parameter "lpm_type" = "altpll" + Info (12134): Parameter "operation_mode" = "NORMAL" + Info (12134): Parameter "pll_type" = "AUTO" + Info (12134): Parameter "port_activeclock" = "PORT_UNUSED" + Info (12134): Parameter "port_areset" = "PORT_UNUSED" + Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED" + Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED" + Info (12134): Parameter "port_clkloss" = "PORT_UNUSED" + Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED" + Info (12134): Parameter "port_configupdate" = "PORT_UNUSED" + Info (12134): Parameter "port_fbin" = "PORT_UNUSED" + Info (12134): Parameter "port_inclk0" = "PORT_USED" + Info (12134): Parameter "port_inclk1" = "PORT_UNUSED" + Info (12134): Parameter "port_locked" = "PORT_UNUSED" + Info (12134): Parameter "port_pfdena" = "PORT_UNUSED" + Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED" + Info (12134): Parameter "port_phasedone" = "PORT_UNUSED" + Info (12134): Parameter "port_phasestep" = "PORT_UNUSED" + Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED" + Info (12134): Parameter "port_pllena" = "PORT_UNUSED" + Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED" + Info (12134): Parameter "port_scanclk" = "PORT_UNUSED" + Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED" + Info (12134): Parameter "port_scandata" = "PORT_UNUSED" + Info (12134): Parameter "port_scandataout" = "PORT_UNUSED" + Info (12134): Parameter "port_scandone" = "PORT_UNUSED" + Info (12134): Parameter "port_scanread" = "PORT_UNUSED" + Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED" + Info (12134): Parameter "port_clk0" = "PORT_USED" + Info (12134): Parameter "port_clk1" = "PORT_USED" + Info (12134): Parameter "port_clk2" = "PORT_UNUSED" + Info (12134): Parameter "port_clk3" = "PORT_UNUSED" + Info (12134): Parameter "port_clk4" = "PORT_UNUSED" + Info (12134): Parameter "port_clk5" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena0" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena1" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena2" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena3" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena4" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena5" = "PORT_UNUSED" + Info (12134): Parameter "port_extclk0" = "PORT_UNUSED" + Info (12134): Parameter "port_extclk1" = "PORT_UNUSED" + Info (12134): Parameter "port_extclk2" = "PORT_UNUSED" + Info (12134): Parameter "port_extclk3" = "PORT_UNUSED" + Info (12134): Parameter "width_clock" = "5" +Info (12021): Found 1 design units, including 1 entities, in source file db/clk_gen_altpll.v + Info (12023): Found entity 1: clk_gen_altpll File: E:/FPGA/puart2/db/clk_gen_altpll.v Line: 29 +Info (12128): Elaborating entity "clk_gen_altpll" for hierarchy "clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated" File: e:/quartuslite/quartus/libraries/megafunctions/altpll.tdf Line: 897 +Info (12128): Elaborating entity "spi_master_2164" for hierarchy "spi_master_2164:u_spi_master_2164" File: E:/FPGA/puart2/ddr_ctrl.v Line: 221 +Info (12128): Elaborating entity "spi_master_esp32" for hierarchy "spi_master_esp32:tranfer" File: E:/FPGA/puart2/ddr_ctrl.v Line: 234 +Warning (10230): Verilog HDL assignment warning at spi_master_esp32.v(50): truncated value with size 32 to match size of target (4) File: E:/FPGA/puart2/spi_master_esp32.v Line: 50 +Info (12128): Elaborating entity "uart_tx" for hierarchy "uart_tx:u_uart_pc" File: E:/FPGA/puart2/ddr_ctrl.v Line: 243 +Warning (10230): Verilog HDL assignment warning at uart_tx.v(32): truncated value with size 32 to match size of target (16) File: E:/FPGA/puart2/uart_tx.v Line: 32 +Warning (10230): Verilog HDL assignment warning at uart_tx.v(74): truncated value with size 32 to match size of target (4) File: E:/FPGA/puart2/uart_tx.v Line: 74 +Info (13000): Registers with preset signals will power-up high File: E:/FPGA/puart2/spi_master_2164.v Line: 11 +Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back +Warning (13024): Output pins are stuck at VCC or GND + Warning (13410): Pin "MOSI_ESP32" is stuck at GND File: E:/FPGA/puart2/ddr_ctrl.v Line: 12 + Warning (13410): Pin "cs_ESP32" is stuck at VCC File: E:/FPGA/puart2/ddr_ctrl.v Line: 13 + Warning (13410): Pin "sclk_ESP32" is stuck at GND File: E:/FPGA/puart2/ddr_ctrl.v Line: 14 +Info (286030): Timing-Driven Synthesis is running +Info (17049): 6 registers lost all their fanouts during netlist optimizations. +Info (144001): Generated suppressed messages file E:/FPGA/puart2/output_files/intan_m10.map.smsg +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL +Warning (15899): PLL "clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected File: E:/FPGA/puart2/db/clk_gen_altpll.v Line: 43 +Info (21057): Implemented 213 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 4 input pins + Info (21059): Implemented 9 output pins + Info (21061): Implemented 199 logic cells + Info (21065): Implemented 1 PLLs +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings + Info: Peak virtual memory: 4766 megabytes + Info: Processing ended: Thu Dec 11 18:00:25 2025 + Info: Elapsed time: 00:00:10 + Info: Total CPU time (on all processors): 00:00:21 + + ++------------------------------------------+ +; Analysis & Synthesis Suppressed Messages ; ++------------------------------------------+ +The suppressed messages can be found in E:/FPGA/puart2/output_files/intan_m10.map.smsg. + + diff --git a/puart2/output_files/intan_m10.map.smsg b/puart2/output_files/intan_m10.map.smsg new file mode 100644 index 0000000..5073da8 --- /dev/null +++ b/puart2/output_files/intan_m10.map.smsg @@ -0,0 +1,2 @@ +Warning (10268): Verilog HDL information at ddr_ctrl.v(151): always construct contains both blocking and non-blocking assignments File: E:/FPGA/puart2/ddr_ctrl.v Line: 151 +Info (10281): Verilog HDL Declaration information at spi_master_esp32.v(6): object "done" differs only in case from object "DONE" in the same scope File: E:/FPGA/puart2/spi_master_esp32.v Line: 6 diff --git a/puart2/output_files/intan_m10.map.summary b/puart2/output_files/intan_m10.map.summary new file mode 100644 index 0000000..2b1a07f --- /dev/null +++ b/puart2/output_files/intan_m10.map.summary @@ -0,0 +1,16 @@ +Analysis & Synthesis Status : Successful - Thu Dec 11 18:00:25 2025 +Quartus Prime Version : 17.1.0 Build 590 10/25/2017 SJ Lite Edition +Revision Name : intan_m10 +Top-level Entity Name : ddr_ctrl +Family : MAX 10 +Total logic elements : 198 + Total combinational functions : 121 + Dedicated logic registers : 135 +Total registers : 135 +Total pins : 13 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 1 +UFM blocks : 0 +ADC blocks : 0 diff --git a/puart2/output_files/intan_m10.pin b/puart2/output_files/intan_m10.pin new file mode 100644 index 0000000..61c465c --- /dev/null +++ b/puart2/output_files/intan_m10.pin @@ -0,0 +1,222 @@ + -- Copyright (C) 2017 Intel Corporation. All rights reserved. + -- Your use of Intel Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Intel Program License + -- Subscription Agreement, the Intel Quartus Prime License Agreement, + -- the Intel FPGA IP License Agreement, or other applicable license + -- agreement, including, without limitation, that your use is for + -- the sole purpose of programming logic devices manufactured by + -- Intel and sold by Intel or its authorized distributors. Please + -- refer to the applicable agreement for further details. + -- + -- This is a Quartus Prime output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus Prime input file. This file cannot be used + -- to make Quartus Prime pin assignments - for instructions on how to make pin + -- assignments, please see Quartus Prime help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1A: 2.5V + -- Bank 1B: 2.5V + -- Bank 2: 3.3V + -- Bank 3: 3.3V + -- Bank 5: 3.3V + -- Bank 6: 3.3V + -- Bank 8: 3.3V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition +CHIP "intan_m10" ASSIGNED TO AN: 10M08SAM153C8G + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : A1 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 8 : +MOSI_ESP32 : A14 : output : 3.3-V LVCMOS : : 8 : Y +GND : A15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 1A : +GND : B2 : gnd : : : : +VCCA3 : B3 : power : : 3.0V/3.3V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 : +VCCIO8 : B5 : power : : 3.3V : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8 : +VCCIO8 : B9 : power : : 3.3V : 8 : +VCCIO8 : B10 : power : : 3.3V : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 8 : +cs_ESP32 : B13 : output : 3.3-V LVCMOS : : 8 : Y +sclk_ESP32 : B14 : output : 3.3-V LVCMOS : : 8 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1A : +ANAIN1 : D4 : : : : : +GND : D5 : gnd : : : : +~ALTERA_nSTATUS~ / RESERVED_INPUT : D6 : input : 3.3 V Schmitt Trigger : : 8 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 : +~ALTERA_CONFIG_SEL~ / RESERVED_INPUT : D8 : input : 3.3-V LVTTL : : 8 : N +GND : D9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 6 : +VCCA2 : D14 : power : : 3.0V/3.3V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : : : : 1A : +REFGND : E4 : : : : : +GND : E5 : gnd : : : : +~ALTERA_CONF_DONE~ / RESERVED_INPUT : E6 : input : 3.3 V Schmitt Trigger : : 8 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8 : +~ALTERA_nCONFIG~ / RESERVED_INPUT : E8 : input : 3.3 V Schmitt Trigger : : 8 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 6 : +GND : E12 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 6 : +VCCIO1A : F2 : power : : 2.5V : 1A : +ADC_VREF : F4 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 6 : +VCCIO6 : F14 : power : : 3.3V : 6 : +~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : input : 2.5 V Schmitt Trigger : : 1B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : G2 : : : : 1B : +GND : G4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 1B : +VCC_ONE : G8 : power : : 3.0V/3.3V : : +GND : G9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 6 : +VCCIO6 : G14 : power : : 3.3V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 6 : +VCCIO1B : H2 : power : : 2.5V : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1B : +~ALTERA_TDO~ : H4 : output : 2.5 V : : 1B : N +~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP : H5 : input : 2.5 V Schmitt Trigger : : 1B : N +VCC_ONE : H7 : power : : 3.0V/3.3V : : +GND : H8 : gnd : : : : +VCC_ONE : H9 : power : : 3.0V/3.3V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : H11 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 6 : +GND : H14 : gnd : : : : +~ALTERA_TCK~ / RESERVED_INPUT : J1 : input : 2.5 V Schmitt Trigger : : 1B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : J2 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 2 : +sys_clk : J5 : input : 3.3-V LVCMOS : : 2 : Y +GND : J7 : gnd : : : : +VCC_ONE : J8 : power : : 3.0V/3.3V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J9 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J11 : : : : 5 : +test_flag : J12 : input : 3.3-V LVCMOS : : 6 : Y +rst_n : J14 : input : 3.3-V LVCMOS : : 5 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K11 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K12 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1B : +VCCIO2 : L2 : power : : 3.3V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L6 : : : : 3 : +mosi : L7 : output : 3.3-V LVCMOS : : 3 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L11 : : : : 5 : +GND : L12 : gnd : : : : +VCCIO5 : L14 : power : : 3.3V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L15 : : : : 5 : +GND : M2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M5 : : : : 3 : +GND : M6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M9 : : : : 3 : +GND : M10 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M11 : : : : 3 : +convert_flag_led : M12 : output : 3.3-V LVCMOS : : 5 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : M14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N1 : : : : 2 : +VCCA1 : N2 : power : : 3.0V/3.3V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N14 : : : : 5 : +test_flag_led : N15 : output : 3.3-V LVCMOS : : 5 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P3 : : : : 3 : +miso : P4 : input : 3.3-V LVCMOS : : 3 : Y +VCCIO3 : P5 : power : : 3.3V : 3 : +cs_n : P6 : output : 3.3-V LVCMOS : : 3 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : P7 : : : : 3 : +tx : P8 : output : 3.3-V LVCMOS : : 3 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : P9 : : : : 3 : +VCCIO3 : P10 : power : : 3.3V : 3 : +VCCIO3 : P11 : power : : 3.3V : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P12 : : : : 3 : +VCCA4 : P13 : power : : 3.0V/3.3V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P14 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P15 : : : : 3 : +GND : R1 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 3 : +sclk : R5 : output : 3.3-V LVCMOS : : 3 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R13 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R14 : : : : 3 : +GND : R15 : gnd : : : : diff --git a/puart2/output_files/intan_m10.pof b/puart2/output_files/intan_m10.pof new file mode 100644 index 0000000..0b8cb7d Binary files /dev/null and b/puart2/output_files/intan_m10.pof differ diff --git a/puart2/output_files/intan_m10.pow.rpt b/puart2/output_files/intan_m10.pow.rpt new file mode 100644 index 0000000..ef01385 --- /dev/null +++ b/puart2/output_files/intan_m10.pow.rpt @@ -0,0 +1,309 @@ +Power Analyzer report for intan_m10 +Thu Dec 11 18:00:36 2025 +Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Parallel Compilation + 3. Power Analyzer Summary + 4. Power Analyzer Settings + 5. Indeterminate Toggle Rates + 6. Operating Conditions Used + 7. Thermal Power Dissipation by Block + 8. Thermal Power Dissipation by Block Type + 9. Thermal Power Dissipation by Hierarchy + 10. Core Dynamic Thermal Power Dissipation by Clock Domain + 11. Current Drawn from Voltage Supplies Summary + 12. VCCIO Supply Current Drawn by I/O Bank + 13. VCCIO Supply Current Drawn by Voltage + 14. Confidence Metric Details + 15. Signal Activities + 16. Power Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2017 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.13 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 4.3% ; ++----------------------------+-------------+ + + ++-------------------------------------------------------------------------------------------+ +; Power Analyzer Summary ; ++----------------------------------------+--------------------------------------------------+ +; Power Analyzer Status ; Successful - Thu Dec 11 18:00:36 2025 ; +; Quartus Prime Version ; 17.1.0 Build 590 10/25/2017 SJ Lite Edition ; +; Revision Name ; intan_m10 ; +; Top-level Entity Name ; ddr_ctrl ; +; Family ; MAX 10 ; +; Device ; 10M08SAM153C8G ; +; Power Models ; Final ; +; Total Thermal Power Dissipation ; 149.66 mW ; +; Core Dynamic Thermal Power Dissipation ; 0.00 mW ; +; Core Static Thermal Power Dissipation ; 121.22 mW ; +; I/O Thermal Power Dissipation ; 28.44 mW ; +; Power Estimation Confidence ; Low: user provided insufficient toggle rate data ; ++----------------------------------------+--------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Power Analyzer Settings ; ++----------------------------------------------------------------------------+---------------------------------------+---------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+---------------------------------------+---------------+ +; Maximum processors allowed for parallel compilation ; 4 ; ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Default Power Input I/O Toggle Rate ; 12.5% ; 12.5% ; +; Preset Cooling Solution ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; ; +; Board thermal model ; None (CONSERVATIVE) ; ; +; Default Power Toggle Rate ; 12.5% ; 12.5% ; +; Use vectorless estimation ; On ; On ; +; Use Input Files ; Off ; Off ; +; Filter Glitches in VCD File Reader ; On ; On ; +; Power Analyzer Report Signal Activity ; Off ; Off ; +; Power Analyzer Report Power Dissipation ; Off ; Off ; +; Device Power Characteristics ; TYPICAL ; TYPICAL ; +; Automatically Compute Junction Temperature ; On ; On ; +; Specified Junction Temperature ; 25 ; 25 ; +; Ambient Temperature ; 25 ; 25 ; +; Use Custom Cooling Solution ; Off ; Off ; +; Board Temperature ; 25 ; 25 ; ++----------------------------------------------------------------------------+---------------------------------------+---------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------+ +; Indeterminate Toggle Rates ; ++-----------------------------------------------------------------------------------------------------+-----------------------------+ +; Node ; Reason ; ++-----------------------------------------------------------------------------------------------------+-----------------------------+ +; clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|wire_pll1_clk[0] ; No valid clock domain found ; +; test_flag ; No valid clock domain found ; +; rst_n ; No valid clock domain found ; +; sys_clk ; No valid clock domain found ; +; miso ; No valid clock domain found ; +; clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|wire_pll1_clk[0]~clkctrl ; No valid clock domain found ; +; spi_master_2164:u_spi_master_2164|cs_n~clkctrl ; No valid clock domain found ; ++-----------------------------------------------------------------------------------------------------+-----------------------------+ + + ++--------------------------------------------------------------------------+ +; Operating Conditions Used ; ++---------------------------------------------+----------------------------+ +; Setting ; Value ; ++---------------------------------------------+----------------------------+ +; Device power characteristics ; Typical ; +; ; ; +; Voltages ; ; +; VCCA ; 3.00 V ; +; VCC_ONE ; 3.00 V ; +; 3.3-V LVTTL I/O Standard ; 3.3 V ; +; 3.3-V LVCMOS I/O Standard ; 3.3 V ; +; 2.5 V I/O Standard ; 2.5 V ; +; 3.3 V Schmitt Trigger I/O Standard ; 3.3 V ; +; 2.5 V Schmitt Trigger I/O Standard ; 2.5 V ; +; ; ; +; Auto computed junction temperature ; 28.8 degrees Celsius ; +; Ambient temperature ; 25.0 degrees Celsius ; +; Junction-to-Case thermal resistance ; 11.00 degrees Celsius/Watt ; +; Case-to-Heat Sink thermal resistance ; 0.10 degrees Celsius/Watt ; +; Heat Sink-to-Ambient thermal resistance ; 14.30 degrees Celsius/Watt ; +; ; ; +; Board model used ; None ; ++---------------------------------------------+----------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------+ +; Thermal Power Dissipation by Block ; ++------------+------------+---------------------+-----------------------------+--------------------------------+-------------------------------+ +; Block Name ; Block Type ; Total Thermal Power ; Block Thermal Dynamic Power ; Block Thermal Static Power (1) ; Routing Thermal Dynamic Power ; ++------------+------------+---------------------+-----------------------------+--------------------------------+-------------------------------+ +(1) The "Thermal Power Dissipation by Block" Table has been hidden. To show this table, please select the "Write power dissipation by block to report file" option under "PowerPlay Power Analyzer Settings". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Thermal Power Dissipation by Block Type ; ++---------------------+-----------------------------------+-----------------------------+--------------------------------+-------------------------------+-----------------------------------------------------------+ +; Block Type ; Total Thermal Power by Block Type ; Block Thermal Dynamic Power ; Block Thermal Static Power (1) ; Routing Thermal Dynamic Power ; Block Average Toggle Rate (millions of transitions / sec) ; ++---------------------+-----------------------------------+-----------------------------+--------------------------------+-------------------------------+-----------------------------------------------------------+ +; Combinational cell ; 0.00 mW ; 0.00 mW ; -- ; 0.00 mW ; 0.000 ; +; Clock control block ; 0.00 mW ; 0.00 mW ; -- ; 0.00 mW ; 0.000 ; +; Register cell ; 0.00 mW ; 0.00 mW ; -- ; 0.00 mW ; 0.000 ; +; I/O ; 0.78 mW ; 0.00 mW ; 0.78 mW ; 0.00 mW ; 0.000 ; +; Voltage Regulator ; 0.76 mW ; 0.00 mW ; 0.76 mW ; -- ; -- ; ++---------------------+-----------------------------------+-----------------------------+--------------------------------+-------------------------------+-----------------------------------------------------------+ +(1) The "Block Thermal Static Power" for all block types except Pins and the Voltage Regulator, if one exists, is part of the "Core Static Thermal Power Dissipation" value found on the PowerPlay Power Analyzer-->Summary report panel. The "Core Static Thermal Power Dissipation" also contains the thermal static power dissipated by the routing. + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Thermal Power Dissipation by Hierarchy ; ++--------------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+--------------------------------------------------------------------------------------+ +; Compilation Hierarchy Node ; Total Thermal Power by Hierarchy (1) ; Block Thermal Dynamic Power (1) ; Block Thermal Static Power (1)(2) ; Routing Thermal Dynamic Power (1) ; Full Hierarchy Name ; ++--------------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+--------------------------------------------------------------------------------------+ +; |ddr_ctrl ; 1.55 mW (1.55 mW) ; 0.00 mW (0.00 mW) ; 1.55 mW (1.55 mW) ; 0.00 mW (0.00 mW) ; |ddr_ctrl ; +; |hard_block:auto_generated_inst ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |ddr_ctrl|hard_block:auto_generated_inst ; +; |clk_gen:clk_gen_inst ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |ddr_ctrl|clk_gen:clk_gen_inst ; +; |altpll:altpll_component ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |ddr_ctrl|clk_gen:clk_gen_inst|altpll:altpll_component ; +; |clk_gen_altpll:auto_generated ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |ddr_ctrl|clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated ; +; |spi_master_esp32:tranfer ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |ddr_ctrl|spi_master_esp32:tranfer ; +; |spi_master_2164:u_spi_master_2164 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |ddr_ctrl|spi_master_2164:u_spi_master_2164 ; +; |uart_tx:u_uart_pc ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |ddr_ctrl|uart_tx:u_uart_pc ; ++--------------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+--------------------------------------------------------------------------------------+ +(1) Value in parentheses is the power consumed at that level of hierarchy. Value not in parentheses is the power consumed at that level of hierarchy plus the power consumed by all levels of hierarchy below it. + +(2) The "Block Thermal Static Power" for all levels of hierarchy except the top-level hierarchy is part of the "Core Static Thermal Power Dissipation" value found on the PowerPlay Power Analyzer-->Summary report panel. The "Core Static Thermal Power Dissipation" also contains the thermal static power dissipated by the routing. + + ++--------------------------------------------------------------------+ +; Core Dynamic Thermal Power Dissipation by Clock Domain ; ++-----------------+-----------------------+--------------------------+ +; Clock Domain ; Clock Frequency (MHz) ; Total Core Dynamic Power ; ++-----------------+-----------------------+--------------------------+ +; No clock domain ; 0.00 ; 0.00 ; ++-----------------+-----------------------+--------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Current Drawn from Voltage Supplies Summary ; ++----------------+-------------------------+---------------------------+--------------------------+----------------------------------+ +; Voltage Supply ; Total Current Drawn (1) ; Dynamic Current Drawn (1) ; Static Current Drawn (1) ; Minimum Power Supply Current (2) ; ++----------------+-------------------------+---------------------------+--------------------------+----------------------------------+ +; VCCIO ; 8.79 mA ; 0.00 mA ; 8.79 mA ; 8.79 mA ; +; VCCA ; 3.03 mA ; 0.00 mA ; 3.03 mA ; 3.03 mA ; +; VCC_ONE ; 37.38 mA ; 0.00 mA ; 37.38 mA ; 37.38 mA ; ++----------------+-------------------------+---------------------------+--------------------------+----------------------------------+ +(1) Currents reported in columns "Total Current Drawn", "Dynamic Current Drawn", and "Static Current Drawn" are sufficient for user operation of the device. +(2) Currents reported in column "Minimum Power Supply Current" are sufficient for power-up, configuration, and user operation of the device. + + ++-----------------------------------------------------------------------------------------------+ +; VCCIO Supply Current Drawn by I/O Bank ; ++----------+---------------+---------------------+-----------------------+----------------------+ +; I/O Bank ; VCCIO Voltage ; Total Current Drawn ; Dynamic Current Drawn ; Static Current Drawn ; ++----------+---------------+---------------------+-----------------------+----------------------+ +; 1A ; 2.5V ; 0.25 mA ; 0.00 mA ; 0.25 mA ; +; 1B ; 2.5V ; 0.26 mA ; 0.00 mA ; 0.26 mA ; +; 2 ; 3.3V ; 1.62 mA ; 0.00 mA ; 1.62 mA ; +; 3 ; 3.3V ; 1.68 mA ; 0.00 mA ; 1.68 mA ; +; 4 ; -- ; -- ; -- ; -- ; +; 5 ; 3.3V ; 1.65 mA ; 0.00 mA ; 1.65 mA ; +; 6 ; 3.3V ; 1.62 mA ; 0.00 mA ; 1.62 mA ; +; 7 ; -- ; -- ; -- ; -- ; +; 8 ; 3.3V ; 1.72 mA ; 0.00 mA ; 1.72 mA ; ++----------+---------------+---------------------+-----------------------+----------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------+ +; VCCIO Supply Current Drawn by Voltage ; ++---------------+-------------------------+---------------------------+--------------------------+----------------------------------+ +; VCCIO Voltage ; Total Current Drawn (1) ; Dynamic Current Drawn (1) ; Static Current Drawn (1) ; Minimum Power Supply Current (2) ; ++---------------+-------------------------+---------------------------+--------------------------+----------------------------------+ +; 2.5V ; 0.51 mA ; 0.00 mA ; 0.51 mA ; 0.51 mA ; +; 3.3V ; 8.28 mA ; 0.00 mA ; 8.28 mA ; 8.28 mA ; ++---------------+-------------------------+---------------------------+--------------------------+----------------------------------+ +(1) Currents reported in columns "Total Current Drawn", "Dynamic Current Drawn", and "Static Current Drawn" are sufficient for user operation of the device. +(2) Currents reported in column "Minimum Power Supply Current" are sufficient for power-up, configuration, and user operation of the device. + + ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; Confidence Metric Details ; ++----------------------------------------------------------------------------------------+-------------+------------+--------------+---------------+ +; Data Source ; Total ; Pin ; Registered ; Combinational ; ++----------------------------------------------------------------------------------------+-------------+------------+--------------+---------------+ +; Simulation (from file) ; ; ; ; ; +; -- Number of signals with Toggle Rate from Simulation ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; +; -- Number of signals with Static Probability from Simulation ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; +; ; ; ; ; ; +; Node, entity or clock assignment ; ; ; ; ; +; -- Number of signals with Toggle Rate from Node, entity or clock assignment ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; +; -- Number of signals with Static Probability from Node, entity or clock assignment ; 2 (0.5%) ; 0 (0.0%) ; 0 (0.0%) ; 2 (1.0%) ; +; ; ; ; ; ; +; Vectorless estimation ; ; ; ; ; +; -- Number of signals with Toggle Rate from Vectorless estimation ; 355 (97.0%) ; 11 (52.4%) ; 135 (100.0%) ; 209 (99.5%) ; +; -- Number of signals with Zero toggle rate, from Vectorless estimation ; 19 (5.2%) ; 6 (28.6%) ; 0 (0.0%) ; 13 (6.2%) ; +; -- Number of signals with Static Probability from Vectorless estimation ; 353 (96.4%) ; 11 (52.4%) ; 135 (100.0%) ; 207 (98.6%) ; +; ; ; ; ; ; +; Default assignment ; ; ; ; ; +; -- Number of signals with Toggle Rate from Default assignment ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; +; -- Number of signals with Static Probability from Default assignment ; 11 (3.0%) ; 10 (47.6%) ; 0 (0.0%) ; 1 (0.5%) ; +; ; ; ; ; ; +; Assumed 0 ; ; ; ; ; +; -- Number of signals with Toggle Rate assumed 0 ; 11 (3.0%) ; 10 (47.6%) ; 0 (0.0%) ; 1 (0.5%) ; ++----------------------------------------------------------------------------------------+-------------+------------+--------------+---------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Activities ; ++--------+------+---------------------------------------------+-------------------------+--------------------+--------------------------------+ +; Signal ; Type ; Toggle Rate (millions of transitions / sec) ; Toggle Rate Data Source ; Static Probability ; Static Probability Data Source ; ++--------+------+---------------------------------------------+-------------------------+--------------------+--------------------------------+ +(1) The "Signal Activity" Table has been hidden. To show this table, please select the "Write signal activities to report file" option under "PowerPlay Power Analyzer Settings". + + ++-------------------------+ +; Power Analyzer Messages ; ++-------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Power Analyzer + Info: Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition + Info: Processing started: Thu Dec 11 18:00:35 2025 +Info: Command: quartus_pow --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10 +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'intan_m10.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Warning (332060): Node: sys_clk was determined to be a clock but was found without an associated clock assignment. + Info (13166): Register spi_master_2164:u_spi_master_2164|cnt[1] is being clocked by sys_clk +Warning (332060): Node: spi_master_2164:u_spi_master_2164|cs_n was determined to be a clock but was found without an associated clock assignment. + Info (13166): Register state[2] is being clocked by spi_master_2164:u_spi_master_2164|cs_n +Warning (332068): No clocks defined in design. +Warning (332056): PLL cross checking found inconsistent PLL clock settings: + Warning (332056): Node: clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 83.333 +Info (223000): Starting Vectorless Power Activity Estimation +Warning (222013): Relative toggle rates could not be calculated because no clock domain could be identified for some nodes +Info (223001): Completed Vectorless Power Activity Estimation +Info (218000): Using Advanced I/O Power to simulate I/O buffers with the specified board trace model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (215049): Average toggle rate for this design is 0.000 millions of transitions / sec +Info (215031): Total thermal power estimate for the design is 149.66 mW +Info: Quartus Prime Power Analyzer was successful. 0 errors, 7 warnings + Info: Peak virtual memory: 4812 megabytes + Info: Processing ended: Thu Dec 11 18:00:37 2025 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/puart2/output_files/intan_m10.pow.summary b/puart2/output_files/intan_m10.pow.summary new file mode 100644 index 0000000..c4b9524 --- /dev/null +++ b/puart2/output_files/intan_m10.pow.summary @@ -0,0 +1,12 @@ +Power Analyzer Status : Successful - Thu Dec 11 18:00:36 2025 +Quartus Prime Version : 17.1.0 Build 590 10/25/2017 SJ Lite Edition +Revision Name : intan_m10 +Top-level Entity Name : ddr_ctrl +Family : MAX 10 +Device : 10M08SAM153C8G +Power Models : Final +Total Thermal Power Dissipation : 149.66 mW +Core Dynamic Thermal Power Dissipation : 0.00 mW +Core Static Thermal Power Dissipation : 121.22 mW +I/O Thermal Power Dissipation : 28.44 mW +Power Estimation Confidence : Low: user provided insufficient toggle rate data diff --git a/puart2/output_files/intan_m10.sld b/puart2/output_files/intan_m10.sld new file mode 100644 index 0000000..f7d3ed7 --- /dev/null +++ b/puart2/output_files/intan_m10.sld @@ -0,0 +1 @@ + diff --git a/puart2/output_files/intan_m10.sof b/puart2/output_files/intan_m10.sof new file mode 100644 index 0000000..ac04529 Binary files /dev/null and b/puart2/output_files/intan_m10.sof differ diff --git a/puart2/output_files/intan_m10.sta.rpt b/puart2/output_files/intan_m10.sta.rpt new file mode 100644 index 0000000..6ebf30b --- /dev/null +++ b/puart2/output_files/intan_m10.sta.rpt @@ -0,0 +1,637 @@ +TimeQuest Timing Analyzer report for intan_m10 +Thu Dec 11 18:00:41 2025 +Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. TimeQuest Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow 1200mV 85C Model Fmax Summary + 6. Slow 1200mV 85C Model Setup Summary + 7. Slow 1200mV 85C Model Hold Summary + 8. Slow 1200mV 85C Model Recovery Summary + 9. Slow 1200mV 85C Model Removal Summary + 10. Slow 1200mV 85C Model Minimum Pulse Width Summary + 11. Slow 1200mV 85C Model Metastability Summary + 12. Slow 1200mV 0C Model Fmax Summary + 13. Slow 1200mV 0C Model Setup Summary + 14. Slow 1200mV 0C Model Hold Summary + 15. Slow 1200mV 0C Model Recovery Summary + 16. Slow 1200mV 0C Model Removal Summary + 17. Slow 1200mV 0C Model Minimum Pulse Width Summary + 18. Slow 1200mV 0C Model Metastability Summary + 19. Fast 1200mV 0C Model Setup Summary + 20. Fast 1200mV 0C Model Hold Summary + 21. Fast 1200mV 0C Model Recovery Summary + 22. Fast 1200mV 0C Model Removal Summary + 23. Fast 1200mV 0C Model Minimum Pulse Width Summary + 24. Fast 1200mV 0C Model Metastability Summary + 25. Multicorner Timing Analysis Summary + 26. Board Trace Model Assignments + 27. Input Transition Times + 28. Signal Integrity Metrics (Slow 1200mv 0c Model) + 29. Signal Integrity Metrics (Slow 1200mv 85c Model) + 30. Signal Integrity Metrics (Fast 1200mv 0c Model) + 31. Setup Transfers + 32. Hold Transfers + 33. Report TCCS + 34. Report RSKM + 35. Unconstrained Paths Summary + 36. Clock Status Summary + 37. Unconstrained Input Ports + 38. Unconstrained Output Ports + 39. Unconstrained Input Ports + 40. Unconstrained Output Ports + 41. TimeQuest Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2017 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++-----------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++-----------------------+-----------------------------------------------------+ +; Quartus Prime Version ; Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition ; +; Timing Analyzer ; TimeQuest ; +; Revision Name ; intan_m10 ; +; Device Family ; MAX 10 ; +; Device Name ; 10M08SAM153C8G ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++-----------------------+-----------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.10 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 3.4% ; +; Processors 3-4 ; 3.4% ; ++----------------------------+-------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clocks ; ++----------------------------------------------------------+-----------+----------+------------+-------+----------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------+------------------------------------------------------------+--------------------------------------------------------------+ +; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; ++----------------------------------------------------------+-----------+----------+------------+-------+----------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------+------------------------------------------------------------+--------------------------------------------------------------+ +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 8680.520 ; 0.12 MHz ; 0.000 ; 4340.260 ; 50.00 ; 625 ; 6 ; ; ; ; ; false ; sys_clk ; clk_gen_inst|altpll_component|auto_generated|pll1|inclk[0] ; { clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] } ; +; spi_master_2164:u_spi_master_2164|cs_n ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { spi_master_2164:u_spi_master_2164|cs_n } ; +; sys_clk ; Base ; 83.333 ; 12.0 MHz ; 0.000 ; 41.666 ; ; ; ; ; ; ; ; ; ; ; { sys_clk } ; ++----------------------------------------------------------+-----------+----------+------------+-------+----------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------+------------------------------------------------------------+--------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++------------+-----------------+----------------------------------------------------------+------------------------------------------------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+----------------------------------------------------------+------------------------------------------------+ +; 154.2 MHz ; 154.2 MHz ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; ; +; 609.01 MHz ; 402.09 MHz ; spi_master_2164:u_spi_master_2164|cs_n ; limit due to minimum period restriction (tmin) ; ++------------+-----------------+----------------------------------------------------------+------------------------------------------------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + ++-----------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Setup Summary ; ++----------------------------------------------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------------+--------+---------------+ +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; -6.744 ; -6.744 ; +; spi_master_2164:u_spi_master_2164|cs_n ; -0.642 ; -7.912 ; ++----------------------------------------------------------+--------+---------------+ + + ++----------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Hold Summary ; ++----------------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------------+-------+---------------+ +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.362 ; 0.000 ; +; spi_master_2164:u_spi_master_2164|cs_n ; 0.363 ; 0.000 ; ++----------------------------------------------------------+-------+---------------+ + + +------------------------------------------ +; Slow 1200mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1200mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + ++-------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Minimum Pulse Width Summary ; ++----------------------------------------------------------+----------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------------+----------+---------------+ +; spi_master_2164:u_spi_master_2164|cs_n ; -1.487 ; -46.097 ; +; sys_clk ; 41.554 ; 0.000 ; +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 4339.989 ; 0.000 ; ++----------------------------------------------------------+----------+---------------+ + + +----------------------------------------------- +; Slow 1200mV 85C Model Metastability Summary ; +----------------------------------------------- +The design MTBF is not calculated because there are no specified synchronizers in the design. +Number of Synchronizer Chains Found: 1 +Shortest Synchronizer Chain: 2 Registers +Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 +Worst Case Available Settling Time: 17358.585 ns + + + + ++------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Fmax Summary ; ++------------+-----------------+----------------------------------------------------------+------------------------------------------------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+----------------------------------------------------------+------------------------------------------------+ +; 164.42 MHz ; 164.42 MHz ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; ; +; 642.67 MHz ; 402.09 MHz ; spi_master_2164:u_spi_master_2164|cs_n ; limit due to minimum period restriction (tmin) ; ++------------+-----------------+----------------------------------------------------------+------------------------------------------------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + ++-----------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Setup Summary ; ++----------------------------------------------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------------+--------+---------------+ +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; -6.215 ; -6.215 ; +; spi_master_2164:u_spi_master_2164|cs_n ; -0.556 ; -5.863 ; ++----------------------------------------------------------+--------+---------------+ + + ++----------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Hold Summary ; ++----------------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------------+-------+---------------+ +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.324 ; 0.000 ; +; spi_master_2164:u_spi_master_2164|cs_n ; 0.325 ; 0.000 ; ++----------------------------------------------------------+-------+---------------+ + + +----------------------------------------- +; Slow 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + ++-------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Minimum Pulse Width Summary ; ++----------------------------------------------------------+----------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------------+----------+---------------+ +; spi_master_2164:u_spi_master_2164|cs_n ; -1.487 ; -46.097 ; +; sys_clk ; 41.555 ; 0.000 ; +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 4340.000 ; 0.000 ; ++----------------------------------------------------------+----------+---------------+ + + +---------------------------------------------- +; Slow 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +The design MTBF is not calculated because there are no specified synchronizers in the design. +Number of Synchronizer Chains Found: 1 +Shortest Synchronizer Chain: 2 Registers +Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 +Worst Case Available Settling Time: 17358.726 ns + + + + ++-----------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Setup Summary ; ++----------------------------------------------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------------+--------+---------------+ +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; -2.312 ; -2.312 ; +; spi_master_2164:u_spi_master_2164|cs_n ; 0.304 ; 0.000 ; ++----------------------------------------------------------+--------+---------------+ + + ++----------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Hold Summary ; ++----------------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------------+-------+---------------+ +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.151 ; 0.000 ; +; spi_master_2164:u_spi_master_2164|cs_n ; 0.151 ; 0.000 ; ++----------------------------------------------------------+-------+---------------+ + + +----------------------------------------- +; Fast 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + ++-------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Minimum Pulse Width Summary ; ++----------------------------------------------------------+----------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------------+----------+---------------+ +; spi_master_2164:u_spi_master_2164|cs_n ; -1.000 ; -31.000 ; +; sys_clk ; 41.180 ; 0.000 ; +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 4340.041 ; 0.000 ; ++----------------------------------------------------------+----------+---------------+ + + +---------------------------------------------- +; Fast 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +The design MTBF is not calculated because there are no specified synchronizers in the design. +Number of Synchronizer Chains Found: 1 +Shortest Synchronizer Chain: 2 Registers +Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 +Worst Case Available Settling Time: 17359.966 ns + + + + ++------------------------------------------------------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++-----------------------------------------------------------+---------+-------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++-----------------------------------------------------------+---------+-------+----------+---------+---------------------+ +; Worst-case Slack ; -6.744 ; 0.151 ; N/A ; N/A ; -1.487 ; +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; -6.744 ; 0.151 ; N/A ; N/A ; 4339.989 ; +; spi_master_2164:u_spi_master_2164|cs_n ; -0.642 ; 0.151 ; N/A ; N/A ; -1.487 ; +; sys_clk ; N/A ; N/A ; N/A ; N/A ; 41.180 ; +; Design-wide TNS ; -14.656 ; 0.0 ; 0.0 ; 0.0 ; -46.097 ; +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; -6.744 ; 0.000 ; N/A ; N/A ; 0.000 ; +; spi_master_2164:u_spi_master_2164|cs_n ; -7.912 ; 0.000 ; N/A ; N/A ; -46.097 ; +; sys_clk ; N/A ; N/A ; N/A ; N/A ; 0.000 ; ++-----------------------------------------------------------+---------+-------+----------+---------+---------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; mosi ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; cs_n ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; sclk ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; MOSI_ESP32 ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; cs_ESP32 ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; sclk_ESP32 ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; tx ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; test_flag_led ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; convert_flag_led ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++---------------------------------------------------------------------------------+ +; Input Transition Times ; ++---------------------+-----------------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++---------------------+-----------------------+-----------------+-----------------+ +; test_flag ; 3.3-V LVCMOS ; 2640 ps ; 2640 ps ; +; rst_n ; 3.3-V LVCMOS ; 2640 ps ; 2640 ps ; +; sys_clk ; 3.3-V LVCMOS ; 2640 ps ; 2640 ps ; +; miso ; 3.3-V LVCMOS ; 2640 ps ; 2640 ps ; +; ~ALTERA_TMS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_TCK~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_TDI~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_CONFIG_SEL~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ~ALTERA_nCONFIG~ ; 3.3 V Schmitt Trigger ; 2640 ps ; 2640 ps ; +; ~ALTERA_nSTATUS~ ; 3.3 V Schmitt Trigger ; 2640 ps ; 2640 ps ; +; ~ALTERA_CONF_DONE~ ; 3.3 V Schmitt Trigger ; 2640 ps ; 2640 ps ; ++---------------------+-----------------------+-----------------+-----------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 0c Model) ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; mosi ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0411 V ; 0.283 V ; 0.209 V ; 9e-10 s ; 1.03e-09 s ; No ; No ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0411 V ; 0.283 V ; 0.209 V ; 9e-10 s ; 1.03e-09 s ; No ; No ; +; cs_n ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0417 V ; 0.287 V ; 0.209 V ; 8.99e-10 s ; 1.03e-09 s ; No ; No ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0417 V ; 0.287 V ; 0.209 V ; 8.99e-10 s ; 1.03e-09 s ; No ; No ; +; sclk ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0464 V ; 0.207 V ; 0.276 V ; 8.51e-10 s ; 8.52e-10 s ; No ; No ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0464 V ; 0.207 V ; 0.276 V ; 8.51e-10 s ; 8.52e-10 s ; No ; No ; +; MOSI_ESP32 ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0463 V ; 0.208 V ; 0.277 V ; 8.5e-10 s ; 8.53e-10 s ; No ; No ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0463 V ; 0.208 V ; 0.277 V ; 8.5e-10 s ; 8.53e-10 s ; No ; No ; +; cs_ESP32 ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0464 V ; 0.207 V ; 0.276 V ; 8.51e-10 s ; 8.52e-10 s ; No ; No ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0464 V ; 0.207 V ; 0.276 V ; 8.51e-10 s ; 8.52e-10 s ; No ; No ; +; sclk_ESP32 ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0463 V ; 0.208 V ; 0.277 V ; 8.5e-10 s ; 8.53e-10 s ; No ; No ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0463 V ; 0.208 V ; 0.277 V ; 8.5e-10 s ; 8.53e-10 s ; No ; No ; +; tx ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0464 V ; 0.207 V ; 0.276 V ; 8.51e-10 s ; 8.52e-10 s ; No ; No ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0464 V ; 0.207 V ; 0.276 V ; 8.51e-10 s ; 8.52e-10 s ; No ; No ; +; test_flag_led ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0464 V ; 0.207 V ; 0.276 V ; 8.51e-10 s ; 8.52e-10 s ; No ; No ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0464 V ; 0.207 V ; 0.276 V ; 8.51e-10 s ; 8.52e-10 s ; No ; No ; +; convert_flag_led ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0464 V ; 0.207 V ; 0.276 V ; 8.51e-10 s ; 8.52e-10 s ; No ; No ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0464 V ; 0.207 V ; 0.276 V ; 8.51e-10 s ; 8.52e-10 s ; No ; No ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.49e-09 V ; 2.38 V ; -0.0505 V ; 0.23 V ; 0.155 V ; 4.84e-10 s ; 6.18e-10 s ; Yes ; No ; 2.32 V ; 7.49e-09 V ; 2.38 V ; -0.0505 V ; 0.23 V ; 0.155 V ; 4.84e-10 s ; 6.18e-10 s ; Yes ; No ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 85c Model) ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; mosi ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.018 V ; 0.27 V ; 0.216 V ; 1.11e-09 s ; 1.22e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.018 V ; 0.27 V ; 0.216 V ; 1.11e-09 s ; 1.22e-09 s ; Yes ; Yes ; +; cs_n ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.018 V ; 0.27 V ; 0.217 V ; 1.11e-09 s ; 1.22e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.018 V ; 0.27 V ; 0.217 V ; 1.11e-09 s ; 1.22e-09 s ; Yes ; Yes ; +; sclk ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; +; MOSI_ESP32 ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0199 V ; 0.191 V ; 0.262 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0199 V ; 0.191 V ; 0.262 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; +; cs_ESP32 ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; +; sclk_ESP32 ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0199 V ; 0.191 V ; 0.262 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0199 V ; 0.191 V ; 0.262 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; +; tx ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; +; test_flag_led ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; +; convert_flag_led ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.88e-07 V ; 2.36 V ; -0.0211 V ; 0.162 V ; 0.122 V ; 6.58e-10 s ; 7.79e-10 s ; No ; Yes ; 2.32 V ; 7.88e-07 V ; 2.36 V ; -0.0211 V ; 0.162 V ; 0.122 V ; 6.58e-10 s ; 7.79e-10 s ; No ; Yes ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1200mv 0c Model) ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; mosi ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 8.93e-07 V ; 3.52 V ; -0.0321 V ; 0.324 V ; 0.176 V ; 6.87e-10 s ; 8.14e-10 s ; No ; Yes ; 3.46 V ; 8.93e-07 V ; 3.52 V ; -0.0321 V ; 0.324 V ; 0.176 V ; 6.87e-10 s ; 8.14e-10 s ; No ; Yes ; +; cs_n ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0325 V ; 0.324 V ; 0.176 V ; 6.87e-10 s ; 8.14e-10 s ; No ; Yes ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0325 V ; 0.324 V ; 0.176 V ; 6.87e-10 s ; 8.14e-10 s ; No ; Yes ; +; sclk ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.252 V ; 6.55e-10 s ; 6.68e-10 s ; No ; Yes ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.252 V ; 6.55e-10 s ; 6.68e-10 s ; No ; Yes ; +; MOSI_ESP32 ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.251 V ; 6.54e-10 s ; 6.68e-10 s ; No ; Yes ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.251 V ; 6.54e-10 s ; 6.68e-10 s ; No ; Yes ; +; cs_ESP32 ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.252 V ; 6.55e-10 s ; 6.68e-10 s ; No ; Yes ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.252 V ; 6.55e-10 s ; 6.68e-10 s ; No ; Yes ; +; sclk_ESP32 ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.251 V ; 6.54e-10 s ; 6.68e-10 s ; No ; Yes ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.251 V ; 6.54e-10 s ; 6.68e-10 s ; No ; Yes ; +; tx ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.252 V ; 6.55e-10 s ; 6.68e-10 s ; No ; Yes ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.252 V ; 6.55e-10 s ; 6.68e-10 s ; No ; Yes ; +; test_flag_led ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.252 V ; 6.55e-10 s ; 6.68e-10 s ; No ; Yes ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.252 V ; 6.55e-10 s ; 6.68e-10 s ; No ; Yes ; +; convert_flag_led ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.252 V ; 6.55e-10 s ; 6.68e-10 s ; No ; Yes ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.252 V ; 6.55e-10 s ; 6.68e-10 s ; No ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0395 V ; 0.361 V ; 0.109 V ; 3.1e-10 s ; 4.41e-10 s ; No ; Yes ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0395 V ; 0.361 V ; 0.109 V ; 3.1e-10 s ; 4.41e-10 s ; No ; Yes ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Setup Transfers ; ++----------------------------------------------------------+----------------------------------------------------------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++----------------------------------------------------------+----------------------------------------------------------+----------+----------+----------+----------+ +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 1138 ; 0 ; 0 ; 0 ; +; spi_master_2164:u_spi_master_2164|cs_n ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 0 ; 179 ; 0 ; 0 ; +; spi_master_2164:u_spi_master_2164|cs_n ; spi_master_2164:u_spi_master_2164|cs_n ; 0 ; 0 ; 0 ; 31 ; ++----------------------------------------------------------+----------------------------------------------------------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Hold Transfers ; ++----------------------------------------------------------+----------------------------------------------------------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++----------------------------------------------------------+----------------------------------------------------------+----------+----------+----------+----------+ +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 1138 ; 0 ; 0 ; 0 ; +; spi_master_2164:u_spi_master_2164|cs_n ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 0 ; 179 ; 0 ; 0 ; +; spi_master_2164:u_spi_master_2164|cs_n ; spi_master_2164:u_spi_master_2164|cs_n ; 0 ; 0 ; 0 ; 31 ; ++----------------------------------------------------------+----------------------------------------------------------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 3 ; 3 ; +; Unconstrained Input Port Paths ; 139 ; 139 ; +; Unconstrained Output Ports ; 6 ; 6 ; +; Unconstrained Output Port Paths ; 6 ; 6 ; ++---------------------------------+-------+------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Status Summary ; ++----------------------------------------------------------+----------------------------------------------------------+-----------+-------------+ +; Target ; Clock ; Type ; Status ; ++----------------------------------------------------------+----------------------------------------------------------+-----------+-------------+ +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; Generated ; Constrained ; +; spi_master_2164:u_spi_master_2164|cs_n ; spi_master_2164:u_spi_master_2164|cs_n ; Base ; Constrained ; +; sys_clk ; sys_clk ; Base ; Constrained ; ++----------------------------------------------------------+----------------------------------------------------------+-----------+-------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; miso ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; rst_n ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; test_flag ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++------------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++------------------+---------------------------------------------------------------------------------------+ +; convert_flag_led ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; cs_n ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; mosi ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; sclk ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; test_flag_led ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tx ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------------+---------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; miso ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; rst_n ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; test_flag ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++------------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++------------------+---------------------------------------------------------------------------------------+ +; convert_flag_led ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; cs_n ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; mosi ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; sclk ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; test_flag_led ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tx ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------------+---------------------------------------------------------------------------------------+ + + ++------------------------------------+ +; TimeQuest Timing Analyzer Messages ; ++------------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime TimeQuest Timing Analyzer + Info: Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition + Info: Processing started: Thu Dec 11 18:00:37 2025 +Info: Command: quartus_sta intan_m10 -c intan_m10 +Info: qsta_default_script.tcl version: #3 +Info (20032): Parallel compilation is enabled and will use up to 4 processors +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'intan_m10.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained generated clocks found in the design. Calling "derive_pll_clocks -create_base_clocks" +Info (332110): Deriving PLL clocks + Info (332110): create_clock -period 83.333 -waveform {0.000 41.666} -name sys_clk sys_clk + Info (332110): create_generated_clock -source {clk_gen_inst|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 625 -multiply_by 6 -duty_cycle 50.00 -name {clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]} {clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]} +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332105): Deriving Clocks + Info (332105): create_clock -period 1.000 -name spi_master_2164:u_spi_master_2164|cs_n spi_master_2164:u_spi_master_2164|cs_n +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. +Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info: Analyzing Slow 1200mV 85C Model +Info: Can't run Report Timing Closure Recommendations. The current device family is not supported. +Critical Warning (332148): Timing requirements not met +Info (332146): Worst-case setup slack is -6.744 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -6.744 -6.744 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] + Info (332119): -0.642 -7.912 spi_master_2164:u_spi_master_2164|cs_n +Info (332146): Worst-case hold slack is 0.362 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.362 0.000 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 0.363 0.000 spi_master_2164:u_spi_master_2164|cs_n +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is -1.487 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -1.487 -46.097 spi_master_2164:u_spi_master_2164|cs_n + Info (332119): 41.554 0.000 sys_clk + Info (332119): 4339.989 0.000 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] +Info (332114): Report Metastability: Found 1 synchronizer chains. + Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design. + Info (332114): Number of Synchronizer Chains Found: 1 + Info (332114): Shortest Synchronizer Chain: 2 Registers + Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 + Info (332114): Worst Case Available Settling Time: 17358.585 ns + Info (332114): +Info: Analyzing Slow 1200mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. +Critical Warning (332148): Timing requirements not met +Info (332146): Worst-case setup slack is -6.215 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -6.215 -6.215 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] + Info (332119): -0.556 -5.863 spi_master_2164:u_spi_master_2164|cs_n +Info (332146): Worst-case hold slack is 0.324 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.324 0.000 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 0.325 0.000 spi_master_2164:u_spi_master_2164|cs_n +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is -1.487 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -1.487 -46.097 spi_master_2164:u_spi_master_2164|cs_n + Info (332119): 41.555 0.000 sys_clk + Info (332119): 4340.000 0.000 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] +Info (332114): Report Metastability: Found 1 synchronizer chains. + Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design. + Info (332114): Number of Synchronizer Chains Found: 1 + Info (332114): Shortest Synchronizer Chain: 2 Registers + Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 + Info (332114): Worst Case Available Settling Time: 17358.726 ns + Info (332114): +Info: Analyzing Fast 1200mV 0C Model +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. +Critical Warning (332148): Timing requirements not met +Info (332146): Worst-case setup slack is -2.312 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -2.312 -2.312 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 0.304 0.000 spi_master_2164:u_spi_master_2164|cs_n +Info (332146): Worst-case hold slack is 0.151 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.151 0.000 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 0.151 0.000 spi_master_2164:u_spi_master_2164|cs_n +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is -1.000 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -1.000 -31.000 spi_master_2164:u_spi_master_2164|cs_n + Info (332119): 41.180 0.000 sys_clk + Info (332119): 4340.041 0.000 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] +Info (332114): Report Metastability: Found 1 synchronizer chains. + Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design. + Info (332114): Number of Synchronizer Chains Found: 1 + Info (332114): Shortest Synchronizer Chain: 2 Registers + Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 + Info (332114): Worst Case Available Settling Time: 17359.966 ns + Info (332114): +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings + Info: Peak virtual memory: 4784 megabytes + Info: Processing ended: Thu Dec 11 18:00:41 2025 + Info: Elapsed time: 00:00:04 + Info: Total CPU time (on all processors): 00:00:03 + + diff --git a/puart2/output_files/intan_m10.sta.summary b/puart2/output_files/intan_m10.sta.summary new file mode 100644 index 0000000..5da5fc9 --- /dev/null +++ b/puart2/output_files/intan_m10.sta.summary @@ -0,0 +1,89 @@ +------------------------------------------------------------ +TimeQuest Timing Analyzer Summary +------------------------------------------------------------ + +Type : Slow 1200mV 85C Model Setup 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]' +Slack : -6.744 +TNS : -6.744 + +Type : Slow 1200mV 85C Model Setup 'spi_master_2164:u_spi_master_2164|cs_n' +Slack : -0.642 +TNS : -7.912 + +Type : Slow 1200mV 85C Model Hold 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]' +Slack : 0.362 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Hold 'spi_master_2164:u_spi_master_2164|cs_n' +Slack : 0.363 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Minimum Pulse Width 'spi_master_2164:u_spi_master_2164|cs_n' +Slack : -1.487 +TNS : -46.097 + +Type : Slow 1200mV 85C Model Minimum Pulse Width 'sys_clk' +Slack : 41.554 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Minimum Pulse Width 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]' +Slack : 4339.989 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Setup 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]' +Slack : -6.215 +TNS : -6.215 + +Type : Slow 1200mV 0C Model Setup 'spi_master_2164:u_spi_master_2164|cs_n' +Slack : -0.556 +TNS : -5.863 + +Type : Slow 1200mV 0C Model Hold 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]' +Slack : 0.324 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Hold 'spi_master_2164:u_spi_master_2164|cs_n' +Slack : 0.325 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Minimum Pulse Width 'spi_master_2164:u_spi_master_2164|cs_n' +Slack : -1.487 +TNS : -46.097 + +Type : Slow 1200mV 0C Model Minimum Pulse Width 'sys_clk' +Slack : 41.555 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Minimum Pulse Width 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]' +Slack : 4340.000 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Setup 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]' +Slack : -2.312 +TNS : -2.312 + +Type : Fast 1200mV 0C Model Setup 'spi_master_2164:u_spi_master_2164|cs_n' +Slack : 0.304 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Hold 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]' +Slack : 0.151 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Hold 'spi_master_2164:u_spi_master_2164|cs_n' +Slack : 0.151 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Minimum Pulse Width 'spi_master_2164:u_spi_master_2164|cs_n' +Slack : -1.000 +TNS : -31.000 + +Type : Fast 1200mV 0C Model Minimum Pulse Width 'sys_clk' +Slack : 41.180 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Minimum Pulse Width 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]' +Slack : 4340.041 +TNS : 0.000 + +------------------------------------------------------------ diff --git a/puart2/spi_master_2164.v b/puart2/spi_master_2164.v new file mode 100644 index 0000000..7bb752a --- /dev/null +++ b/puart2/spi_master_2164.v @@ -0,0 +1,129 @@ +module spi_master_2164( + input sys_clk, + input rst_n, + input [15:0] din, + input wire start, + output reg [15:0] dout, + output reg done, + + // connect to 2164 + output reg sclk, + output reg cs_n, + output reg mosi, + input miso, + + // for test only + output reg [6:0] cnt // count to 47 +); + + localparam cnt_total = 'd42; + + reg [15:0] dout_r; + + +//================== cnt =====================// + always @ (posedge sys_clk or negedge rst_n) begin + if(!rst_n) + cnt <= 'd0; + else if(cnt == cnt_total) + cnt <= 'd0; + else + if (start) begin + cnt <= cnt + 1'b1; + end +end + + +//================== send data ===============// + always @ (posedge sys_clk or negedge rst_n) begin + if(!rst_n) begin + sclk <= 1'b0; + cs_n <= 1'b1; + mosi <= 1'b0; + end + else begin + + case(cnt) + 6'd0: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end + 6'd1: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end + 6'd2: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= 1'b0; end + 6'd3: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= 1'b0; end + 6'd4: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[15]; end + 6'd5: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[15]; dout_r <= {dout_r[14:0],miso}; end + 6'd6: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[14]; end + 6'd7: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[14]; dout_r <= {dout_r[14:0],miso}; end + 6'd8: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[13]; end + 6'd9: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[13]; dout_r <= {dout_r[14:0],miso}; end + 6'd10: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[12]; end + 6'd11: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[12]; dout_r <= {dout_r[14:0],miso}; end + 6'd12: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[11]; end + 6'd13: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[11]; dout_r <= {dout_r[14:0],miso}; end + 6'd14: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[10]; end + 6'd15: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[10]; dout_r <= {dout_r[14:0],miso}; end + 6'd16: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[9]; end + 6'd17: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[9]; dout_r <= {dout_r[14:0],miso}; end + 6'd18: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[8]; end + 6'd19: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[8]; dout_r <= {dout_r[14:0],miso}; end + 6'd20: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[7]; end + 6'd21: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[7]; dout_r <= {dout_r[14:0],miso}; end + 6'd22: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[6]; end + 6'd23: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[6]; dout_r <= {dout_r[14:0],miso}; end + 6'd24: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[5]; end + 6'd25: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[5]; dout_r <= {dout_r[14:0],miso}; end + 6'd26: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[4]; end + 6'd27: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[4]; dout_r <= {dout_r[14:0],miso}; end + 6'd28: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[3]; end + 6'd29: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[3]; dout_r <= {dout_r[14:0],miso}; end + 6'd30: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[2]; end + 6'd31: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[2]; dout_r <= {dout_r[14:0],miso}; end + 6'd32: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[1]; end + 6'd33: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[1]; dout_r <= {dout_r[14:0],miso}; end + 6'd34: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[0]; end + 6'd35: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[0]; dout_r <= {dout_r[14:0],miso}; end + 6'd36: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= 1'b0; end + 6'd37: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= 1'b0; end + 6'd38: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= 1'b0; end + 6'd39: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= 1'b0; end + 6'd40: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end + 6'd41: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end + 6'd42: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end + 6'd43: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end + 6'd44: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end + 6'd45: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end + 6'd46: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end + 6'd47: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end + default: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end + endcase + + end + end + + +//================ done =================// + always @ (posedge sys_clk or negedge rst_n) begin + if(!rst_n) + done <= 1'b0; + else if(cnt == cnt_total) + begin + done <= 1'b1; + + end + else + done <= 1'b0; + end + + + +//================ dout =================// + always@(posedge sys_clk or negedge rst_n) begin + if(!rst_n) + dout <= 'd0; + else if(cnt == 'd38) + dout <= dout_r; + else + dout <= dout; + end + + + +endmodule diff --git a/puart2/spi_master_2164.v.bak b/puart2/spi_master_2164.v.bak new file mode 100644 index 0000000..0078345 --- /dev/null +++ b/puart2/spi_master_2164.v.bak @@ -0,0 +1,116 @@ +module spi_master_2164( + input sys_clk, + input rst_n, + input [15:0] din, + output reg [31:0] dout, + output reg done, + + // connect to 2164 + output reg sclk, + output reg cs_n, + output reg mosi, + input miso, + + // for test only + output reg [5:0] cnt // count to 42 +); + + + reg [31:0] dout_r; + + +//================== cnt =====================// + always @ (posedge sys_clk or negedge rst_n) begin + if(!rst_n) + cnt <= 'd0; + else if(cnt == 'd41) + cnt <= 'd0; + else + cnt <= cnt + 1'b1; + end + + + +//================== send data ===============// + always @ (posedge sys_clk or negedge rst_n) begin + if(!rst_n) begin + sclk <= 1'b0; + cs_n <= 1'b1; + mosi <= 1'b0; + end + else begin + case(cnt) + 6'd0: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end + 6'd1: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end + 6'd2: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= 1'b0; end + 6'd3: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[15]; end + 6'd4: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[15]; end + 6'd5: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[14]; dout_r <= {dout_r[30:0],miso}; end + 6'd6: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[14]; dout_r <= {dout_r[30:0],miso}; end + 6'd7: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[13]; dout_r <= {dout_r[30:0],miso}; end + 6'd8: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[13]; dout_r <= {dout_r[30:0],miso}; end + 6'd9: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[12]; dout_r <= {dout_r[30:0],miso}; end + 6'd10: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[12]; dout_r <= {dout_r[30:0],miso}; end + 6'd11: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[11]; dout_r <= {dout_r[30:0],miso}; end + 6'd12: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[11]; dout_r <= {dout_r[30:0],miso}; end + 6'd13: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[10]; dout_r <= {dout_r[30:0],miso}; end + 6'd14: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[10]; dout_r <= {dout_r[30:0],miso}; end + 6'd15: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[9]; dout_r <= {dout_r[30:0],miso}; end + 6'd16: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[9]; dout_r <= {dout_r[30:0],miso}; end + 6'd17: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[8]; dout_r <= {dout_r[30:0],miso}; end + 6'd18: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[8]; dout_r <= {dout_r[30:0],miso}; end + 6'd19: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[7]; dout_r <= {dout_r[30:0],miso}; end + 6'd20: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[7]; dout_r <= {dout_r[30:0],miso}; end + 6'd21: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[6]; dout_r <= {dout_r[30:0],miso}; end + 6'd22: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[6]; dout_r <= {dout_r[30:0],miso}; end + 6'd23: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[5]; dout_r <= {dout_r[30:0],miso}; end + 6'd24: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[5]; dout_r <= {dout_r[30:0],miso}; end + 6'd25: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[4]; dout_r <= {dout_r[30:0],miso}; end + 6'd26: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[4]; dout_r <= {dout_r[30:0],miso}; end + 6'd27: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[3]; dout_r <= {dout_r[30:0],miso}; end + 6'd28: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[3]; dout_r <= {dout_r[30:0],miso}; end + 6'd29: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[2]; dout_r <= {dout_r[30:0],miso}; end + 6'd30: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[2]; dout_r <= {dout_r[30:0],miso}; end + 6'd31: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[1]; dout_r <= {dout_r[30:0],miso}; end + 6'd32: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[1]; dout_r <= {dout_r[30:0],miso}; end + 6'd33: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[0]; dout_r <= {dout_r[30:0],miso}; end + 6'd34: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[0]; dout_r <= {dout_r[30:0],miso}; end + 6'd35: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= 1'b0; dout_r <= {dout_r[30:0],miso}; end + 6'd36: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; dout_r <= {dout_r[30:0],miso}; end + 6'd37: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end + 6'd38: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end + 6'd39: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end + 6'd40: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end + 6'd41: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end + default: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end + endcase + end + end + + + +//================ done =================// + always @ (posedge sys_clk or negedge rst_n) begin + if(!rst_n) + done <= 1'b0; + else if(cnt == 'd41) + done <= 1'b1; + else + done <= 1'b0; + end + + + +//================ dout =================// + always@(posedge sys_clk or negedge rst_n) begin + if(!rst_n) + dout <= 'd0; + else if(cnt == 'd41) + dout <= dout_r; + else + dout <= dout; + end + + + +endmodule diff --git a/puart2/spi_master_esp32.v b/puart2/spi_master_esp32.v new file mode 100644 index 0000000..33c8ea0 --- /dev/null +++ b/puart2/spi_master_esp32.v @@ -0,0 +1,68 @@ +module spi_master_esp32( + input wire clk, + input wire rst_n, + input wire start, + input wire [15:0] din, + output reg done, + output wire sclk, + output wire mosi, + output reg cs +); + +reg [3:0] bit_cnt; +reg [15:0] shift_reg; +reg sclk_reg; +reg [1:0] state; + +localparam IDLE = 2'b00, TRANSFER = 2'b01, DONE = 2'b10; + +assign sclk = sclk_reg; +assign mosi = shift_reg[15]; + +always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + state <= IDLE; + cs <= 1; + sclk_reg <= 0; + bit_cnt <= 0; + shift_reg <= 0; + done <= 0; + end + else begin + + if (start) begin + case (state) + IDLE: begin + + + state <= TRANSFER; + cs <= 0; // 选择从机 + shift_reg <= din; + bit_cnt <= 0; + done <= 0; + + end + + TRANSFER: begin + sclk_reg <= ~sclk_reg; //这样也是一个系统时钟周期新的sclk反转一次，所以sclk的频率也是115200. + if (sclk_reg) begin //看上面的assign mosi = shift_reg[15]; 所以每个sclk高电平mosi输出要输出的值。 + shift_reg <= {shift_reg[14:0], 1'b0}; + bit_cnt <= bit_cnt + 1; + if (bit_cnt == 15) begin + state <= DONE; + end + end + end + + DONE: begin + state <= IDLE; + cs <= 1; // 取消选择从机 + done <= 1; + end + + endcase + end + end +end + +endmodule \ No newline at end of file diff --git a/puart2/spi_master_esp32.v.bak b/puart2/spi_master_esp32.v.bak new file mode 100644 index 0000000..dc8cd99 --- /dev/null +++ b/puart2/spi_master_esp32.v.bak @@ -0,0 +1 @@ +,fghfghfghfghfg \ No newline at end of file diff --git a/puart2/uart_tx.qar b/puart2/uart_tx.qar new file mode 100644 index 0000000..40de27c Binary files /dev/null and b/puart2/uart_tx.qar differ diff --git a/puart2/uart_tx.qarlog b/puart2/uart_tx.qarlog new file mode 100644 index 0000000..e37136c --- /dev/null +++ b/puart2/uart_tx.qarlog @@ -0,0 +1,62 @@ +Quartus Prime Archive log -- E:/FPGA/SPItransfer/20240726/uart_tx.qarlog + +Archive: E:/FPGA/SPItransfer/20240726/uart_tx.qar +Date: Sat Sep 21 09:52:33 2024 +Quartus Prime 17.1.0 Build 590 10/25/2017 SJ Lite Edition + + =========== Files Selected: =========== +E:/FPGA/SPItransfer/20240726/clk_gen.ppf +E:/FPGA/SPItransfer/20240726/clk_gen.qip +E:/FPGA/SPItransfer/20240726/clk_gen.v +E:/FPGA/SPItransfer/20240726/clk_gen_bb.v +E:/FPGA/SPItransfer/20240726/clk_gen_inst.v +E:/FPGA/SPItransfer/20240726/clkgen.ppf +E:/FPGA/SPItransfer/20240726/clkgen.qip +E:/FPGA/SPItransfer/20240726/clkgen.v +E:/FPGA/SPItransfer/20240726/clkgen_bb.v +E:/FPGA/SPItransfer/20240726/clkgen_inst.v +E:/FPGA/SPItransfer/20240726/ddr_ctrl.v +E:/FPGA/SPItransfer/20240726/ddr_ctrl_tb.v +E:/FPGA/SPItransfer/20240726/intan_m10.qpf +E:/FPGA/SPItransfer/20240726/intan_m10.qsf +E:/FPGA/SPItransfer/20240726/intan_m10.v +E:/FPGA/SPItransfer/20240726/intan_m10_assignment_defaults.qdf +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.asm.rpt +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.cdf +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.done +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.eda.rpt +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.fit.rpt +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.fit.smsg +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.fit.summary +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.flow.rpt +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.jdi +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.map.rpt +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.map.smsg +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.map.summary +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.pin +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.pof +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.pow.rpt +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.pow.summary +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.sld +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.sof +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.sta.rpt +E:/FPGA/SPItransfer/20240726/output_files/intan_m10.sta.summary +E:/FPGA/SPItransfer/20240726/spi_master_2164.v +E:/FPGA/SPItransfer/20240726/spi_master_esp32.v +e:/quartuslite/quartus/bin64/assignment_defaults.qdf + ======= Total: 39 files to archive ======= + + ================ Status: =============== +All files archived successfully. + + +******* Archived project restoration attempt on Sat Dec 6 15:37:39 2025 +Source archive file: E:/FPGA/20240726/uart_tx.qar +Archive was extracted into E:/FPGA/20240726/uart_tx_restored/ + - successfully. + + +******* Archived project restoration attempt on Sat Dec 6 15:42:13 2025 +Source archive file: E:/FPGA/20240726/uart_tx.qar +Archive was extracted into E:/FPGA/20240726/uart_tx_restored/ + - successfully. diff --git a/puart2/uart_tx.v b/puart2/uart_tx.v new file mode 100644 index 0000000..82c1eb5 --- /dev/null +++ b/puart2/uart_tx.v @@ -0,0 +1,83 @@ +module uart_tx ( + input wire clk, // 时钟信号 + input wire rst, // 复位信号 + input wire tx_start, // 开始发送信号 + input wire [15:0] tx_data, // 顶层输入的16位待发送数据 + output wire tx, // 串行输出信号 + output reg tx_done // 发送完成信号 +); + +parameter BAUD_RATE = 115200; +parameter CLOCK_FREQ = 115200; // 12 MHz时钟 + +localparam integer BAUD_TICK = CLOCK_FREQ / BAUD_RATE; // 波特率计数，计算出每个比特的时钟周期数 + +// 波特率计数器 +reg [15:0] baud_counter; +reg [7:0] data_to_send; // 用于存储当前要发送的8位数据 +reg [1:0] byte_select; // 控制发送高8位还是低8位数据 + +// 发送状态机定义 +reg [3:0] tx_state; +reg [9:0] tx_shift_reg; // 10位移位寄存器（8位数据 + 起始位 + 停止位） +reg [3:0] tx_bit_counter; // 用于计数8位数据发送的每一位 + +// 波特率计数器更新 +always @(posedge clk or negedge rst) begin + if (!rst) + baud_counter <= 0; + else if (baud_counter == BAUD_TICK - 1) + baud_counter <= 0; + else + baud_counter <= baud_counter + 1; +end + +// UART发送逻辑 +always @(posedge clk or negedge rst) begin + if (!rst) begin + tx_state <= 0; + tx_done <= 0; + byte_select <= 0; + tx_shift_reg <= 10'b1111111111; // 空闲状态（全1表示停止位） + end + else if (baud_counter == BAUD_TICK - 1) begin + case (tx_state) + 0: begin + if (tx_start) begin + // 根据 byte_select 选择发送高8位或低8位数据 + if (byte_select == 0) + data_to_send <= tx_data[15:8]; // 发送低8位 + else + data_to_send <= tx_data[7:0]; // 发送高8位 + + // 将要发送的8位数据加上起始位（0）和停止位（1） + tx_shift_reg <= {1'b1, data_to_send, 1'b0}; // 1位停止位，8位数据，1位起始位 + + tx_state <= 1; + tx_done <= 0; + end + end + 1: begin + // 每个波特率时钟周期发送一位 + if (tx_bit_counter == 9) begin // 所有位发送完成后回到空闲状态 + if (byte_select == 0) + byte_select <= 1; // 切换到发送高8位 + else begin + byte_select <= 0; // 重置为低8位 + tx_done <= 1; // 完成整个16位数据的发送 + end + tx_state <= 0; + tx_bit_counter<= 0; + end + else begin + tx_shift_reg <= {1'b1, tx_shift_reg[9:1]}; // 右移移位寄存器 + tx_bit_counter <= tx_bit_counter + 1; + end + end + endcase + end +end + +assign tx = tx_shift_reg[0]; // 串行输出当前最低位 + +endmodule \ No newline at end of file diff --git a/puart2/uart_tx.v.bak b/puart2/uart_tx.v.bak new file mode 100644 index 0000000..b825663 --- /dev/null +++ b/puart2/uart_tx.v.bak @@ -0,0 +1,82 @@ +module uart_tx ( + input wire clk, // 时钟信号 + input wire rst, // 复位信号 + input wire tx_start, // 开始发送信号 + input wire [15:0] tx_data, // 顶层输入的16位待发送数据 + output wire tx, // 串行输出信号 + output reg tx_done // 发送完成信号 +); + +parameter BAUD_RATE = 115200; +parameter CLOCK_FREQ = 12000000; // 12 MHz时钟 + +localparam integer BAUD_TICK = CLOCK_FREQ / BAUD_RATE; // 波特率计数，计算出每个比特的时钟周期数 + +// 波特率计数器 +reg [15:0] baud_counter; +reg [7:0] data_to_send; // 用于存储当前要发送的8位数据 +reg [1:0] byte_select; // 控制发送高8位还是低8位数据 + +// 发送状态机定义 +reg [3:0] tx_state; +reg [9:0] tx_shift_reg; // 10位移位寄存器（8位数据 + 起始位 + 停止位） +reg [3:0] tx_bit_counter; // 用于计数8位数据发送的每一位 + +// 波特率计数器更新 +always @(posedge clk or posedge rst) begin + if (!rst) + baud_counter <= 0; + else if (baud_counter == BAUD_TICK - 1) + baud_counter <= 0; + else + baud_counter <= baud_counter + 1; +end + +// UART发送逻辑 +always @(posedge clk or posedge rst) begin + if (!rst) begin + tx_state <= 0; + tx_done <= 0; + byte_select <= 0; + tx_shift_reg <= 10'b1111111111; // 空闲状态（全1表示停止位） + end + else if (baud_counter == BAUD_TICK - 1) begin + case (tx_state) + 0: begin + if (tx_start) begin + // 根据 byte_select 选择发送高8位或低8位数据 + if (byte_select == 0) + data_to_send <= tx_data[15:8]; // 发送低8位 + else + data_to_send <= tx_data[7:0]; // 发送高8位 + + // 将要发送的8位数据加上起始位（0）和停止位（1） + tx_shift_reg <= {1'b1, data_to_send, 1'b0}; // 1位停止位，8位数据，1位起始位 + tx_bit_counter <= 0; + tx_state <= 1; + tx_done <= 0; + end + end + 1: begin + // 每个波特率时钟周期发送一位 + if (tx_bit_counter == 9) begin // 所有位发送完成后回到空闲状态 + if (byte_select == 0) + byte_select <= 1; // 切换到发送高8位 + else begin + byte_select <= 0; // 重置为低8位 + tx_done <= 1; // 完成整个16位数据的发送 + end + tx_state <= 0; + end + else begin + tx_shift_reg <= {1'b1, tx_shift_reg[9:1]}; // 右移移位寄存器 + tx_bit_counter <= tx_bit_counter + 1; + end + end + endcase + end +end + +assign tx = tx_shift_reg[0]; // 串行输出当前最低位 + +endmodule \ No newline at end of file diff --git a/puart2/uart_tx_restored/Verilog1.v b/puart2/uart_tx_restored/Verilog1.v new file mode 100644 index 0000000..18d4115 --- /dev/null +++ b/puart2/uart_tx_restored/Verilog1.v @@ -0,0 +1,82 @@ +module uart_tx ( + input wire clk, // 时钟信号 + input wire rst, // 复位信号 + input wire tx_start, // 开始发送信号 + input wire [15:0] tx_data, // 顶层输入的16位待发送数据 + output wire tx, // 串行输出信号 + output reg tx_done // 发送完成信号 +); + +parameter BAUD_RATE = 115200; +parameter CLOCK_FREQ = 12000000; // 12 MHz时钟 + +localparam integer BAUD_TICK = CLOCK_FREQ / BAUD_RATE; // 波特率计数，计算出每个比特的时钟周期数 + +// 波特率计数器 +reg [15:0] baud_counter; +reg [7:0] data_to_send; // 用于存储当前要发送的8位数据 +reg [1:0] byte_select; // 控制发送高8位还是低8位数据 + +// 发送状态机定义 +reg [3:0] tx_state; +reg [9:0] tx_shift_reg; // 10位移位寄存器（8位数据 + 起始位 + 停止位） +reg [3:0] tx_bit_counter; // 用于计数8位数据发送的每一位 + +// 波特率计数器更新 +always @(posedge clk or negedge rst) begin + if (!rst) + baud_counter <= 0; + else if (baud_counter == BAUD_TICK - 1) + baud_counter <= 0; + else + baud_counter <= baud_counter + 1; +end + +// UART发送逻辑 +always @(posedge clk or negedge rst) begin + if (!rst) begin + tx_state <= 0; + tx_done <= 0; + byte_select <= 0; + tx_shift_reg <= 10'b1111111111; // 空闲状态（全1表示停止位） + end + else if (baud_counter == BAUD_TICK - 1) begin + case (tx_state) + 0: begin + if (tx_start) begin + // 根据 byte_select 选择发送高8位或低8位数据 + if (byte_select == 0) + data_to_send <= tx_data[15:8]; // 发送低8位 + else + data_to_send <= tx_data[7:0]; // 发送高8位 + + // 将要发送的8位数据加上起始位（0）和停止位（1） + tx_shift_reg <= {1'b1, data_to_send, 1'b0}; // 1位停止位，8位数据，1位起始位 + tx_bit_counter <= 0; + tx_state <= 1; + tx_done <= 0; + end + end + 1: begin + // 每个波特率时钟周期发送一位 + if (tx_bit_counter == 9) begin // 所有位发送完成后回到空闲状态 + if (byte_select == 0) + byte_select <= 1; // 切换到发送高8位 + else begin + byte_select <= 0; // 重置为低8位 + tx_done <= 1; // 完成整个16位数据的发送 + end + tx_state <= 0; + end + else begin + tx_shift_reg <= {1'b1, tx_shift_reg[9:1]}; // 右移移位寄存器 + tx_bit_counter <= tx_bit_counter + 1; + end + end + endcase + end +end + +assign tx = tx_shift_reg[0]; // 串行输出当前最低位 + +endmodule \ No newline at end of file diff --git a/puart2/uart_tx_restored/assignment_defaults.qdf b/puart2/uart_tx_restored/assignment_defaults.qdf new file mode 100644 index 0000000..67fe186 --- /dev/null +++ b/puart2/uart_tx_restored/assignment_defaults.qdf @@ -0,0 +1,812 @@ +# Default value changes +# +# In 16.1, the default value of assignment OCP_HW_EVAL has changed to "Enable" +# In 15.0, the default value of assignment FAMILY has changed to "Cyclone V" +# In 10.0, the default value of assignment OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING has changed to "Normal" +# In 9.1, the default value of assignment PARALLEL_SYNTHESIS has changed to "On" +# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Arria II GZ" +# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Cyclone 10 LP" +# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Cyclone IV GX" +# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Stratix IV" +# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Cyclone IV E" +# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Arria II GX" +# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Arria II GZ" +# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Cyclone 10 LP" +# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Cyclone IV GX" +# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Stratix IV" +# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Cyclone IV E" +# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Arria II GX" +# In 9.0, the default value of assignment ENABLE_BENEFICIAL_SKEW_OPTIMIZATION has changed to "On" +# In 8.1, the default value of assignment OPTIMIZE_HOLD_TIMING has changed to "All Paths" for device family "Arria II GZ" +# In 8.1, the default value of assignment OPTIMIZE_HOLD_TIMING has changed to "All Paths" for device family "Cyclone 10 LP" +# In 8.1, the default value of assignment OPTIMIZE_HOLD_TIMING has changed to "All Paths" for device family "Cyclone IV GX" +# In 8.1, the default value of assignment OPTIMIZE_HOLD_TIMING has changed to "All Paths" for device family "Stratix IV" +# In 8.1, the default value of assignment OPTIMIZE_HOLD_TIMING has changed to "All Paths" for device family "Cyclone IV E" +# In 8.1, the default value of assignment OPTIMIZE_HOLD_TIMING has changed to "All Paths" for device family "Arria II GX" +# In 8.0, the default value of assignment USE_CONFIGURATION_DEVICE has changed to "Off" for device family "Cyclone 10 LP" +# In 8.0, the default value of assignment USE_CONFIGURATION_DEVICE has changed to "Off" for device family "Cyclone IV E" +# In 8.0, the default value of assignment USE_CONFIGURATION_DEVICE has changed to "Off" for device family "Cyclone IV GX" +# In 7.2, the default value of assignment POWER_REPORT_SIGNAL_ACTIVITY has changed to "Off" +# In 7.2, the default value of assignment POWER_REPORT_POWER_DISSIPATION has changed to "Off" +# In 5.1, the default value of assignment ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS has changed to "On" +# In 5.1, the default value of assignment STRATIXII_MRAM_COMPATIBILITY has changed to "Off" +# In 5.0, the default value of assignment SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF has changed to "On" +# In 4.1, the default value of assignment FITTER_EFFORT has changed to "Auto Fit" + + +set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off +set_global_assignment -name IP_COMPONENT_INTERNAL Off +set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On +set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off +set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off +set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db +set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off +set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off +set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off +set_global_assignment -name HC_OUTPUT_DIR hc_output +set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off +set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off +set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" +set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On +set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On +set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off +set_global_assignment -name REVISION_TYPE Base -family "Arria V" +set_global_assignment -name REVISION_TYPE Base -family "Stratix V" +set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ" +set_global_assignment -name REVISION_TYPE Base -family "Cyclone V" +set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" +set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On +set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On +set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On +set_global_assignment -name DO_COMBINED_ANALYSIS Off +set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off +set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off +set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off +set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off +set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On +set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "MAX 10" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria 10" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V" +set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V" +set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100 +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone 10 LP" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "MAX 10" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria 10" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V" +set_global_assignment -name OPTIMIZATION_MODE Balanced +set_global_assignment -name ALLOW_REGISTER_MERGING On +set_global_assignment -name ALLOW_REGISTER_DUPLICATION On +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V" +set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Cyclone 10 LP" +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX 10" +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix IV" +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV E" +set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Arria 10" +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX V" +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix V" +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V GZ" +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX II" +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GX" +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GZ" +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV GX" +set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone V" +set_global_assignment -name MUX_RESTRUCTURE Auto +set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off +set_global_assignment -name ENABLE_IP_DEBUG Off +set_global_assignment -name SAVE_DISK_SPACE On +set_global_assignment -name OCP_HW_EVAL Enable +set_global_assignment -name DEVICE_FILTER_PACKAGE Any +set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name TRUE_WYSIWYG_FLOW Off +set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off +set_global_assignment -name STATE_MACHINE_PROCESSING Auto +set_global_assignment -name SAFE_STATE_MACHINE Off +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On +set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On +set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off +set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 +set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 +set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On +set_global_assignment -name PARALLEL_SYNTHESIS On +set_global_assignment -name DSP_BLOCK_BALANCING Auto +set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" +set_global_assignment -name NOT_GATE_PUSH_BACK On +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On +set_global_assignment -name IGNORE_CARRY_BUFFERS Off +set_global_assignment -name IGNORE_CASCADE_BUFFERS Off +set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_LCELL_BUFFERS Off +set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO +set_global_assignment -name IGNORE_SOFT_BUFFERS On +set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off +set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off +set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On +set_global_assignment -name AUTO_GLOBAL_OE_MAX On +set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off +set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut +set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name ALLOW_XOR_GATE_USAGE On +set_global_assignment -name AUTO_LCELL_INSERTION On +set_global_assignment -name CARRY_CHAIN_LENGTH 48 +set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 +set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name CASCADE_CHAIN_LENGTH 2 +set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 +set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 +set_global_assignment -name AUTO_CARRY_CHAINS On +set_global_assignment -name AUTO_CASCADE_CHAINS On +set_global_assignment -name AUTO_PARALLEL_EXPANDERS On +set_global_assignment -name AUTO_OPEN_DRAIN_PINS On +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off +set_global_assignment -name AUTO_ROM_RECOGNITION On +set_global_assignment -name AUTO_RAM_RECOGNITION On +set_global_assignment -name AUTO_DSP_RECOGNITION On +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto +set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On +set_global_assignment -name STRICT_RAM_RECOGNITION Off +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On +set_global_assignment -name FORCE_SYNCH_CLEAR Off +set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On +set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off +set_global_assignment -name AUTO_RESOURCE_SHARING Off +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off +set_global_assignment -name MAX7000_FANIN_PER_CELL 100 +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On +set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" +set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off +set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" +set_global_assignment -name REPORT_PARAMETER_SETTINGS On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On +set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100 +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 +set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000 +set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off +set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" +set_global_assignment -name MAX_LABS "-1 (Unlimited)" +set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On +set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" +set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On +set_global_assignment -name PRPOF_ID Off +set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off +set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On +set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name TXPMA_SLEW_RATE Low +set_global_assignment -name ADCE_ENABLED Auto +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name SPECTRAQ_PHYSICAL_SYNTHESIS Off +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name ENABLE_NCEO_OUTPUT Off +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image" +set_global_assignment -name CVP_MODE Off +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V" +set_global_assignment -name VID_OPERATION_MODE "PMBus Slave" +set_global_assignment -name USE_CONF_DONE AUTO +set_global_assignment -name USE_PWRMGT_SCL AUTO +set_global_assignment -name USE_PWRMGT_SDA AUTO +set_global_assignment -name USE_PWRMGT_ALERT AUTO +set_global_assignment -name USE_INIT_DONE AUTO +set_global_assignment -name USE_CVP_CONFDONE AUTO +set_global_assignment -name USE_SEU_ERROR AUTO +set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off +set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On +set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name INIT_DONE_OPEN_DRAIN On +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name ENABLE_CONFIGURATION_PINS On +set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off +set_global_assignment -name ENABLE_NCE_PIN Off +set_global_assignment -name ENABLE_BOOT_SEL_PIN On +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name INTERNAL_SCRUBBING Off +set_global_assignment -name PR_ERROR_OPEN_DRAIN On +set_global_assignment -name PR_READY_OPEN_DRAIN On +set_global_assignment -name ENABLE_CVP_CONFDONE Off +set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On +set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ" +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF +set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto +set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V" +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto +set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" +set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off +set_global_assignment -name PR_DONE_OPEN_DRAIN On +set_global_assignment -name NCEO_OPEN_DRAIN On +set_global_assignment -name ENABLE_CRC_ERROR_PIN Off +set_global_assignment -name ENABLE_PR_PINS Off +set_global_assignment -name RESERVE_PR_PINS Off +set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off +set_global_assignment -name PR_PINS_OPEN_DRAIN Off +set_global_assignment -name CLAMPING_DIODE Off +set_global_assignment -name TRI_STATE_SPI_PINS Off +set_global_assignment -name UNUSED_TSD_PINS_GND Off +set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off +set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V" +set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0 +set_global_assignment -name SEU_FIT_REPORT Off +set_global_assignment -name HYPER_RETIMER Off -family "Arria 10" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE On +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130" +set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000 +set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery" +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0 +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP" +set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V" +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF +set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off +set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off +set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off +set_global_assignment -name POR_SCHEME "Instant ON" +set_global_assignment -name EN_USER_IO_WEAK_PULLUP On +set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On +set_global_assignment -name POF_VERIFY_PROTECT Off +set_global_assignment -name ENABLE_SPI_MODE_CHECK Off +set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On +set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0 +set_global_assignment -name GENERATE_PMSF_FILES On +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off +set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO +set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name DRC_GATED_CLOCK_FEED 30 +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name ENABLE_DRC_SETTINGS Off +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 +set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 +set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 +set_global_assignment -name MERGE_HEX_FILE Off +set_global_assignment -name GENERATE_SVF_FILE Off +set_global_assignment -name GENERATE_ISC_FILE Off +set_global_assignment -name GENERATE_JAM_FILE Off +set_global_assignment -name GENERATE_JBC_FILE Off +set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off +set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off +set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" +set_global_assignment -name HPS_EARLY_IO_RELEASE Off +set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off +set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name POWER_HPS_ENABLE Off +set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 +set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off +set_global_assignment -name IGNORE_PARTITIONS Off +set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off +set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On +set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" +set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On +set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On +set_global_assignment -name RTLV_GROUP_RELATED_NODES On +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off +set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On +set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On +set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On +set_global_assignment -name EQC_BBOX_MERGE On +set_global_assignment -name EQC_LVDS_MERGE On +set_global_assignment -name EQC_RAM_UNMERGING On +set_global_assignment -name EQC_DFF_SS_EMULATION On +set_global_assignment -name EQC_RAM_REGISTER_UNPACK On +set_global_assignment -name EQC_MAC_REGISTER_UNPACK On +set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? +set_global_assignment -name EDA_EXTRA_ELAB_OPTION "\"\"" -section_id ? +set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? +set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? +set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? +set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? +set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? +set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? +set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? +set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? +set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ? diff --git a/puart2/uart_tx_restored/clk_gen.ppf b/puart2/uart_tx_restored/clk_gen.ppf new file mode 100644 index 0000000..36a1b80 --- /dev/null +++ b/puart2/uart_tx_restored/clk_gen.ppf @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/puart2/uart_tx_restored/clk_gen.qip b/puart2/uart_tx_restored/clk_gen.qip new file mode 100644 index 0000000..3cf5e33 --- /dev/null +++ b/puart2/uart_tx_restored/clk_gen.qip @@ -0,0 +1,7 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "23.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "clk_gen.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clk_gen_inst.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clk_gen_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clk_gen.ppf"] diff --git a/puart2/uart_tx_restored/clk_gen.v b/puart2/uart_tx_restored/clk_gen.v new file mode 100644 index 0000000..c627ebd --- /dev/null +++ b/puart2/uart_tx_restored/clk_gen.v @@ -0,0 +1,332 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: clk_gen.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 23.1std.1 Build 993 05/14/2024 SC Lite Edition +// ************************************************************ + + +//Copyright (C) 2024 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details, at +//https://fpgasoftware.intel.com/eula. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module clk_gen ( + inclk0, + c0, + c1); + + input inclk0; + output c0; + output c1; + + wire [0:0] sub_wire2 = 1'h0; + wire [4:0] sub_wire3; + wire sub_wire0 = inclk0; + wire [1:0] sub_wire1 = {sub_wire2, sub_wire0}; + wire [1:1] sub_wire5 = sub_wire3[1:1]; + wire [0:0] sub_wire4 = sub_wire3[0:0]; + wire c0 = sub_wire4; + wire c1 = sub_wire5; + + altpll altpll_component ( + .inclk (sub_wire1), + .clk (sub_wire3), + .activeclock (), + .areset (1'b0), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .locked (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 625, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 6, + altpll_component.clk0_phase_shift = "0", + altpll_component.clk1_divide_by = 625, + altpll_component.clk1_duty_cycle = 50, + altpll_component.clk1_multiply_by = 12, + altpll_component.clk1_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 83333, + altpll_component.intended_device_family = "MAX 10", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=clk_gen", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_UNUSED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_UNUSED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_USED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "104" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "52" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.115200" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "0.230400" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "12.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.11520000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "0.23040000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clk_gen.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK2 STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK3 STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK4 STRING "0" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "625" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "6" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "625" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "12" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "83333" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_bb.v TRUE +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/puart2/uart_tx_restored/clk_gen_bb.v b/puart2/uart_tx_restored/clk_gen_bb.v new file mode 100644 index 0000000..18ccdf1 --- /dev/null +++ b/puart2/uart_tx_restored/clk_gen_bb.v @@ -0,0 +1,219 @@ +// megafunction wizard: %ALTPLL%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: clk_gen.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 23.1std.1 Build 993 05/14/2024 SC Lite Edition +// ************************************************************ + +//Copyright (C) 2024 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details, at +//https://fpgasoftware.intel.com/eula. + +module clk_gen ( + inclk0, + c0, + c1); + + input inclk0; + output c0; + output c1; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "104" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "52" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.115200" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "0.230400" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "12.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.11520000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "0.23040000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clk_gen.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK2 STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK3 STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK4 STRING "0" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "625" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "6" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "625" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "12" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "83333" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_bb.v TRUE +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/puart2/uart_tx_restored/clk_gen_inst.v b/puart2/uart_tx_restored/clk_gen_inst.v new file mode 100644 index 0000000..29c749f --- /dev/null +++ b/puart2/uart_tx_restored/clk_gen_inst.v @@ -0,0 +1,5 @@ +clk_gen clk_gen_inst ( + .inclk0 ( inclk0_sig ), + .c0 ( c0_sig ), + .c1 ( c1_sig ) + ); diff --git a/puart2/uart_tx_restored/clkgen.ppf b/puart2/uart_tx_restored/clkgen.ppf new file mode 100644 index 0000000..69051ed --- /dev/null +++ b/puart2/uart_tx_restored/clkgen.ppf @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/puart2/uart_tx_restored/clkgen.qip b/puart2/uart_tx_restored/clkgen.qip new file mode 100644 index 0000000..15da83f --- /dev/null +++ b/puart2/uart_tx_restored/clkgen.qip @@ -0,0 +1,7 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "17.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "clkgen.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clkgen_inst.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clkgen_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clkgen.ppf"] diff --git a/puart2/uart_tx_restored/clkgen.v b/puart2/uart_tx_restored/clkgen.v new file mode 100644 index 0000000..997fbeb --- /dev/null +++ b/puart2/uart_tx_restored/clkgen.v @@ -0,0 +1,305 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: clkgen.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 17.1.0 Build 590 10/25/2017 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2017 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module clkgen ( + inclk0, + c0); + + input inclk0; + output c0; + + wire [0:0] sub_wire2 = 1'h0; + wire [4:0] sub_wire3; + wire sub_wire0 = inclk0; + wire [1:0] sub_wire1 = {sub_wire2, sub_wire0}; + wire [0:0] sub_wire4 = sub_wire3[0:0]; + wire c0 = sub_wire4; + + altpll altpll_component ( + .inclk (sub_wire1), + .clk (sub_wire3), + .activeclock (), + .areset (1'b0), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .locked (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 6, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 1, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 83333, + altpll_component.intended_device_family = "MAX 10", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=clkgen", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_UNUSED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_UNUSED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "6" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "2.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "12.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clkgen.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK2 STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK3 STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK4 STRING "0" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "6" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "83333" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/puart2/uart_tx_restored/clkgen_bb.v b/puart2/uart_tx_restored/clkgen_bb.v new file mode 100644 index 0000000..ceb2bf8 --- /dev/null +++ b/puart2/uart_tx_restored/clkgen_bb.v @@ -0,0 +1,198 @@ +// megafunction wizard: %ALTPLL%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: clkgen.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 17.1.0 Build 590 10/25/2017 SJ Lite Edition +// ************************************************************ + +//Copyright (C) 2017 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + +module clkgen ( + inclk0, + c0); + + input inclk0; + output c0; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "6" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "2.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "12.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clkgen.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK2 STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK3 STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK4 STRING "0" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "6" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "83333" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/puart2/uart_tx_restored/clkgen_inst.v b/puart2/uart_tx_restored/clkgen_inst.v new file mode 100644 index 0000000..75f6166 --- /dev/null +++ b/puart2/uart_tx_restored/clkgen_inst.v @@ -0,0 +1,4 @@ +clkgen clkgen_inst ( + .inclk0 ( inclk0_sig ), + .c0 ( c0_sig ) + ); diff --git a/puart2/uart_tx_restored/db/.cmp.kpt b/puart2/uart_tx_restored/db/.cmp.kpt new file mode 100644 index 0000000..cbcf883 Binary files /dev/null and b/puart2/uart_tx_restored/db/.cmp.kpt differ diff --git a/puart2/uart_tx_restored/db/.ipregen.qmsg b/puart2/uart_tx_restored/db/.ipregen.qmsg new file mode 100644 index 0000000..6920e37 --- /dev/null +++ b/puart2/uart_tx_restored/db/.ipregen.qmsg @@ -0,0 +1,5 @@ +{ "Info" "IIPMAN_IPRGEN_BACKUP_FILE" "clk_gen.v clk_gen.BAK.v " "Backing up file \"clk_gen.v\" to \"clk_gen.BAK.v\"" { } { } 0 11902 "Backing up file \"%1!s!\" to \"%2!s!\"" 0 0 "Shell" 0 -1 1765006761527 ""} +{ "Info" "IIPMAN_IPRGEN_START" "ALTPLL clk_gen.v " "Started upgrading IP component ALTPLL with file \"clk_gen.v\"" { } { } 0 11837 "Started upgrading IP component %1!s! with file \"%2!s!\"" 0 0 "Shell" 0 -1 1765006761528 ""} +{ "Info" "IIPMAN_IPRGEN_SUCCESSFUL" "ALTPLL clk_gen.v " "Completed upgrading IP component ALTPLL with file \"clk_gen.v\"" { } { } 0 11131 "Completed upgrading IP component %1!s! with file \"%2!s!\"" 0 0 "Shell" 0 -1 1765006763502 ""} +{ "Info" "IQEXE_TCL_SCRIPT_STATUS" "f:/quartus_prime_lite/quartus/common/tcl/internal/ip_regen/ip_regen.tcl " "Evaluation of Tcl script f:/quartus_prime_lite/quartus/common/tcl/internal/ip_regen/ip_regen.tcl was successful" { } { } 0 23030 "Evaluation of Tcl script %1!s! was successful" 0 0 "Shell" 0 -1 1765006763533 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Shell 0 s 0 s Quartus Prime " "Quartus Prime Shell was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4867 " "Peak virtual memory: 4867 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1765006763533 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 6 15:39:23 2025 " "Processing ended: Sat Dec 6 15:39:23 2025" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1765006763533 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1765006763533 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1765006763533 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Shell" 0 -1 1765006763533 ""} diff --git a/puart2/uart_tx_restored/db/clk_gen_altpll.v b/puart2/uart_tx_restored/db/clk_gen_altpll.v new file mode 100644 index 0000000..4fe9a44 --- /dev/null +++ b/puart2/uart_tx_restored/db/clk_gen_altpll.v @@ -0,0 +1,97 @@ +//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=625 clk0_duty_cycle=50 clk0_multiply_by=6 clk0_phase_shift="0" clk1_divide_by=625 clk1_duty_cycle=50 clk1_multiply_by=12 clk1_phase_shift="0" compensate_clock="CLK0" device_family="MAX 10" inclk0_input_frequency=83333 intended_device_family="MAX 10" lpm_hint="CBX_MODULE_PREFIX=clk_gen" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 clk inclk CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +//VERSION_BEGIN 23.1 cbx_altclkbuf 2024:05:14:17:57:37:SC cbx_altiobuf_bidir 2024:05:14:17:57:38:SC cbx_altiobuf_in 2024:05:14:17:57:38:SC cbx_altiobuf_out 2024:05:14:17:57:38:SC cbx_altpll 2024:05:14:17:57:38:SC cbx_cycloneii 2024:05:14:17:57:38:SC cbx_lpm_add_sub 2024:05:14:17:57:38:SC cbx_lpm_compare 2024:05:14:17:57:38:SC cbx_lpm_counter 2024:05:14:17:57:37:SC cbx_lpm_decode 2024:05:14:17:57:37:SC cbx_lpm_mux 2024:05:14:17:57:37:SC cbx_mgl 2024:05:14:17:57:46:SC cbx_nadder 2024:05:14:17:57:38:SC cbx_stratix 2024:05:14:17:57:38:SC cbx_stratixii 2024:05:14:17:57:38:SC cbx_stratixiii 2024:05:14:17:57:38:SC cbx_stratixv 2024:05:14:17:57:38:SC cbx_util_mgl 2024:05:14:17:57:38:SC VERSION_END +//CBXI_INSTANCE_NAME="ddr_ctrl_clk_gen_clk_gen_inst_altpll_altpll_component" +// synthesis VERILOG_INPUT_VERSION VERILOG_2001 +// altera message_off 10463 + + + +// Copyright (C) 2024 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and any partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details, at +// https://fpgasoftware.intel.com/eula. + + + +//synthesis_resources = fiftyfivenm_pll 1 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module clk_gen_altpll + ( + clk, + inclk) /* synthesis synthesis_clearbox=1 */; + output [4:0] clk; + input [1:0] inclk; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 [1:0] inclk; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [4:0] wire_pll1_clk; + wire wire_pll1_fbout; + + fiftyfivenm_pll pll1 + ( + .activeclock(), + .clk(wire_pll1_clk), + .clkbad(), + .fbin(wire_pll1_fbout), + .fbout(wire_pll1_fbout), + .inclk(inclk), + .locked(), + .phasedone(), + .scandataout(), + .scandone(), + .vcooverrange(), + .vcounderrange() + `ifndef FORMAL_VERIFICATION + // synopsys translate_off + `endif + , + .areset(1'b0), + .clkswitch(1'b0), + .configupdate(1'b0), + .pfdena(1'b1), + .phasecounterselect({3{1'b0}}), + .phasestep(1'b0), + .phaseupdown(1'b0), + .scanclk(1'b0), + .scanclkena(1'b1), + .scandata(1'b0) + `ifndef FORMAL_VERIFICATION + // synopsys translate_on + `endif + ); + defparam + pll1.bandwidth_type = "auto", + pll1.clk0_divide_by = 625, + pll1.clk0_duty_cycle = 50, + pll1.clk0_multiply_by = 6, + pll1.clk0_phase_shift = "0", + pll1.clk1_divide_by = 625, + pll1.clk1_duty_cycle = 50, + pll1.clk1_multiply_by = 12, + pll1.clk1_phase_shift = "0", + pll1.compensate_clock = "clk0", + pll1.inclk0_input_frequency = 83333, + pll1.operation_mode = "normal", + pll1.pll_type = "auto", + pll1.lpm_type = "fiftyfivenm_pll"; + assign + clk = {wire_pll1_clk[4:0]}; +endmodule //clk_gen_altpll +//VALID FILE diff --git a/puart2/uart_tx_restored/db/intan_m10.(0).cnf.cdb b/puart2/uart_tx_restored/db/intan_m10.(0).cnf.cdb new file mode 100644 index 0000000..6e824e4 Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.(0).cnf.cdb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.(0).cnf.hdb b/puart2/uart_tx_restored/db/intan_m10.(0).cnf.hdb new file mode 100644 index 0000000..64cc0e7 Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.(0).cnf.hdb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.(1).cnf.cdb b/puart2/uart_tx_restored/db/intan_m10.(1).cnf.cdb new file mode 100644 index 0000000..3cea06c Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.(1).cnf.cdb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.(1).cnf.hdb b/puart2/uart_tx_restored/db/intan_m10.(1).cnf.hdb new file mode 100644 index 0000000..10459a0 Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.(1).cnf.hdb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.(2).cnf.cdb b/puart2/uart_tx_restored/db/intan_m10.(2).cnf.cdb new file mode 100644 index 0000000..521aaa1 Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.(2).cnf.cdb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.(2).cnf.hdb b/puart2/uart_tx_restored/db/intan_m10.(2).cnf.hdb new file mode 100644 index 0000000..035768d Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.(2).cnf.hdb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.(3).cnf.cdb b/puart2/uart_tx_restored/db/intan_m10.(3).cnf.cdb new file mode 100644 index 0000000..9b970a1 Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.(3).cnf.cdb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.(3).cnf.hdb b/puart2/uart_tx_restored/db/intan_m10.(3).cnf.hdb new file mode 100644 index 0000000..eb69bc5 Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.(3).cnf.hdb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.(4).cnf.cdb b/puart2/uart_tx_restored/db/intan_m10.(4).cnf.cdb new file mode 100644 index 0000000..58eb7f1 Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.(4).cnf.cdb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.(4).cnf.hdb b/puart2/uart_tx_restored/db/intan_m10.(4).cnf.hdb new file mode 100644 index 0000000..e4fb84d Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.(4).cnf.hdb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.(5).cnf.cdb b/puart2/uart_tx_restored/db/intan_m10.(5).cnf.cdb new file mode 100644 index 0000000..0a0f2d5 Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.(5).cnf.cdb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.(5).cnf.hdb b/puart2/uart_tx_restored/db/intan_m10.(5).cnf.hdb new file mode 100644 index 0000000..635832d Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.(5).cnf.hdb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.(6).cnf.cdb b/puart2/uart_tx_restored/db/intan_m10.(6).cnf.cdb new file mode 100644 index 0000000..4934742 Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.(6).cnf.cdb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.(6).cnf.hdb b/puart2/uart_tx_restored/db/intan_m10.(6).cnf.hdb new file mode 100644 index 0000000..2b5da03 Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.(6).cnf.hdb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.asm.qmsg b/puart2/uart_tx_restored/db/intan_m10.asm.qmsg new file mode 100644 index 0000000..182d499 --- /dev/null +++ b/puart2/uart_tx_restored/db/intan_m10.asm.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1765010718841 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition " "Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1765010718841 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 6 16:45:18 2025 " "Processing started: Sat Dec 6 16:45:18 2025" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1765010718841 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1765010718841 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1765010718841 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1765010719500 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1765010719525 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4687 " "Peak virtual memory: 4687 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1765010719804 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 6 16:45:19 2025 " "Processing ended: Sat Dec 6 16:45:19 2025" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1765010719804 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1765010719804 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1765010719804 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1765010719804 ""} diff --git a/puart2/uart_tx_restored/db/intan_m10.asm.rdb b/puart2/uart_tx_restored/db/intan_m10.asm.rdb new file mode 100644 index 0000000..7816b83 Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.asm.rdb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.asm_labs.ddb b/puart2/uart_tx_restored/db/intan_m10.asm_labs.ddb new file mode 100644 index 0000000..9fee1ed Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.asm_labs.ddb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.cmp.bpm b/puart2/uart_tx_restored/db/intan_m10.cmp.bpm new file mode 100644 index 0000000..3e44083 Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.cmp.bpm differ diff --git a/puart2/uart_tx_restored/db/intan_m10.cmp.cdb b/puart2/uart_tx_restored/db/intan_m10.cmp.cdb new file mode 100644 index 0000000..4d2fbc6 Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.cmp.cdb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.cmp.hdb b/puart2/uart_tx_restored/db/intan_m10.cmp.hdb new file mode 100644 index 0000000..701069c Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.cmp.hdb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.cmp.idb b/puart2/uart_tx_restored/db/intan_m10.cmp.idb new file mode 100644 index 0000000..3be3e3e Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.cmp.idb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.cmp.logdb b/puart2/uart_tx_restored/db/intan_m10.cmp.logdb new file mode 100644 index 0000000..bca67c6 --- /dev/null +++ b/puart2/uart_tx_restored/db/intan_m10.cmp.logdb @@ -0,0 +1,55 @@ +v1 +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, +IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os.,Critical,0 such failures found.,,I/O,, +IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, +IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, +IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042, +IO_RULES_MATRIX,Total Pass,13;0;13;0;0;13;13;0;13;13;0;3;0;0;4;0;3;4;0;0;0;3;0;0;0;0;0;13;0;0, +IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Total Inapplicable,0;13;0;13;13;0;0;13;0;0;13;10;13;13;9;13;10;9;13;13;13;10;13;13;13;13;13;0;13;13, +IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,miso,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,mosi,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,cs_n,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,sclk,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,MOSI_ESP32,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,cs_ESP32,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,sclk_ESP32,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,tx,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,test_flag_led,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,convert_flag_led,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,test_flag,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,rst_n,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,sys_clk,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_SUMMARY,Total I/O Rules,30, +IO_RULES_SUMMARY,Number of I/O Rules Passed,12, +IO_RULES_SUMMARY,Number of I/O Rules Failed,0, +IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18, diff --git a/puart2/uart_tx_restored/db/intan_m10.cmp.rdb b/puart2/uart_tx_restored/db/intan_m10.cmp.rdb new file mode 100644 index 0000000..0f1ea65 Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.cmp.rdb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.cmp_merge.kpt b/puart2/uart_tx_restored/db/intan_m10.cmp_merge.kpt new file mode 100644 index 0000000..055a456 Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.cmp_merge.kpt differ diff --git a/puart2/uart_tx_restored/db/intan_m10.db_info b/puart2/uart_tx_restored/db/intan_m10.db_info new file mode 100644 index 0000000..bd697e1 --- /dev/null +++ b/puart2/uart_tx_restored/db/intan_m10.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition +Version_Index = 570679552 +Creation_Time = Sat Dec 6 15:42:15 2025 diff --git a/puart2/uart_tx_restored/db/intan_m10.fit.qmsg b/puart2/uart_tx_restored/db/intan_m10.fit.qmsg new file mode 100644 index 0000000..630f191 --- /dev/null +++ b/puart2/uart_tx_restored/db/intan_m10.fit.qmsg @@ -0,0 +1,56 @@ +{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "4 " "Parallel compilation is enabled and will use up to 4 processors" { } { } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Fitter" 0 -1 1765010713366 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "intan_m10 10M08SAM153C8G " "Selected device 10M08SAM153C8G for design \"intan_m10\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1765010713373 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1765010713403 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1765010713403 ""} +{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|pll1 MAX 10 PLL " "Implemented PLL \"clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|pll1\" as MAX 10 PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] 6 625 0 0 " "Implementing clock multiplication of 6, clock division of 625, and phase shift of 0 degrees (0 ps) for clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/clk_gen_altpll.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/db/clk_gen_altpll.v" 44 -1 0 } } { "" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 84 14177 15141 0 0 "" 0 "" "" } } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Design Software" 0 -1 1765010713448 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] 12 625 0 0 " "Implementing clock multiplication of 12, clock division of 625, and phase shift of 0 degrees (0 ps) for clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] port" { } { { "db/clk_gen_altpll.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/db/clk_gen_altpll.v" 44 -1 0 } } { "" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 85 14177 15141 0 0 "" 0 "" "" } } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Design Software" 0 -1 1765010713448 ""} } { { "db/clk_gen_altpll.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/db/clk_gen_altpll.v" 44 -1 0 } } { "" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 84 14177 15141 0 0 "" 0 "" "" } } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1765010713448 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1765010713496 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1765010713504 ""} +{ "Critical Warning" "WFCUDA_FCUDA_SPS_DEVICE_POWER_LIMITATION" "" "Review the Power Analyzer report file (.pow.rpt) to ensure your design is within the maximum power utilization limit of the single power-supply target device and to avoid functional failures." { } { } 1 16562 "Review the Power Analyzer report file (.pow.rpt) to ensure your design is within the maximum power utilization limit of the single power-supply target device and to avoid functional failures." 0 0 "Fitter" 0 -1 1765010713567 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M08SAM153C8GES " "Device 10M08SAM153C8GES is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1765010713577 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M04SAM153C8G " "Device 10M04SAM153C8G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1765010713577 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1765010713577 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "8 " "Fitter converted 8 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TMS~ G1 " "Pin ~ALTERA_TMS~ is reserved at location G1" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { ~ALTERA_TMS~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 326 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765010713578 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TCK~ J1 " "Pin ~ALTERA_TCK~ is reserved at location J1" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { ~ALTERA_TCK~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 328 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765010713578 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDI~ H5 " "Pin ~ALTERA_TDI~ is reserved at location H5" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDI~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 330 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765010713578 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDO~ H4 " "Pin ~ALTERA_TDO~ is reserved at location H4" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDO~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 332 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765010713578 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONFIG_SEL~ D8 " "Pin ~ALTERA_CONFIG_SEL~ is reserved at location D8" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONFIG_SEL~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 334 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765010713578 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCONFIG~ E8 " "Pin ~ALTERA_nCONFIG~ is reserved at location E8" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCONFIG~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 336 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765010713578 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nSTATUS~ D6 " "Pin ~ALTERA_nSTATUS~ is reserved at location D6" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { ~ALTERA_nSTATUS~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 338 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765010713578 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONF_DONE~ E6 " "Pin ~ALTERA_CONF_DONE~ is reserved at location E6" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONF_DONE~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 340 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765010713578 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1765010713578 ""} +{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" { } { } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1765010713579 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1765010713579 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1765010713579 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1765010713579 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1765010713579 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "intan_m10.sdc " "Synopsys Design Constraints File file not found: 'intan_m10.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1765010714019 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "generated clocks " "No user constrained generated clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1765010714020 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1765010714020 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1765010714022 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1765010714022 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1765010714023 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C1 of PLL_1) " "Automatically promoted node clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C1 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1765010714038 ""} } { { "db/clk_gen_altpll.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/db/clk_gen_altpll.v" 78 -1 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 84 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1765010714038 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C3 of PLL_1) " "Automatically promoted node clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C3 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1765010714038 ""} } { { "db/clk_gen_altpll.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/db/clk_gen_altpll.v" 78 -1 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 84 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1765010714038 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "spi_master_2164:u_spi_master_2164\|cs_n " "Automatically promoted node spi_master_2164:u_spi_master_2164\|cs_n " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1765010714038 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "cs_n~output " "Destination node cs_n~output" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 9 0 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 307 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1765010714038 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1765010714038 ""} } { { "spi_master_2164.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/spi_master_2164.v" 11 -1 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 81 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1765010714038 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1765010714309 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1765010714309 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1765010714310 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1765010714310 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1765010714311 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1765010714311 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1765010714311 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1765010714311 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1765010714322 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1765010714323 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1765010714323 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_tx " "Node \"UART_tx\" is assigned to location or region, but does not exist in design" { } { { "f:/quartus_prime_lite/quartus/bin64/Assignment Editor.qase" "" { Assignment "f:/quartus_prime_lite/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_tx" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1765010714344 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1765010714344 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1765010714344 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1765010714347 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1765010714788 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1765010714827 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1765010714838 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1765010715223 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1765010715223 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1765010715586 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X21_Y0 X31_Y12 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X21_Y0 to location X31_Y12" { } { { "loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X21_Y0 to location X31_Y12"} { { 12 { 0 ""} 21 0 11 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1765010715945 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1765010715945 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1765010716265 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1765010716265 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1765010716268 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.21 " "Total time spent on timing analysis during the Fitter is 0.21 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1765010716415 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1765010716423 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1765010716604 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1765010716605 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1765010716881 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1765010717319 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1765010717431 ""} +{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "4 MAX 10 " "4 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing MAX 10 Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "miso 3.3-V LVCMOS R3 " "Pin miso uses I/O standard 3.3-V LVCMOS at R3" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { miso } } } { "f:/quartus_prime_lite/quartus/bin64/Assignment Editor.qase" "" { Assignment "f:/quartus_prime_lite/quartus/bin64/Assignment Editor.qase" 1 { { 0 "miso" } } } } { "ddr_ctrl.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 7 0 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 12 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1765010717433 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "test_flag 3.3-V LVCMOS J12 " "Pin test_flag uses I/O standard 3.3-V LVCMOS at J12" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { test_flag } } } { "f:/quartus_prime_lite/quartus/bin64/Assignment Editor.qase" "" { Assignment "f:/quartus_prime_lite/quartus/bin64/Assignment Editor.qase" 1 { { 0 "test_flag" } } } } { "ddr_ctrl.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 4 0 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 11 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1765010717433 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "rst_n 3.3-V LVCMOS J14 " "Pin rst_n uses I/O standard 3.3-V LVCMOS at J14" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { rst_n } } } { "f:/quartus_prime_lite/quartus/bin64/Assignment Editor.qase" "" { Assignment "f:/quartus_prime_lite/quartus/bin64/Assignment Editor.qase" 1 { { 0 "rst_n" } } } } { "ddr_ctrl.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 3 0 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 10 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1765010717433 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "sys_clk 3.3-V LVCMOS J5 " "Pin sys_clk uses I/O standard 3.3-V LVCMOS at J5" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { sys_clk } } } { "f:/quartus_prime_lite/quartus/bin64/Assignment Editor.qase" "" { Assignment "f:/quartus_prime_lite/quartus/bin64/Assignment Editor.qase" 1 { { 0 "sys_clk" } } } } { "ddr_ctrl.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 2 0 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 9 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1765010717433 ""} } { } 0 169177 "%1!d! pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1765010717433 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/FPGA/20240726/uart_tx_restored/output_files/intan_m10.fit.smsg " "Generated suppressed messages file E:/FPGA/20240726/uart_tx_restored/output_files/intan_m10.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1765010717473 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 8 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5534 " "Peak virtual memory: 5534 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1765010717809 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 6 16:45:17 2025 " "Processing ended: Sat Dec 6 16:45:17 2025" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1765010717809 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1765010717809 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1765010717809 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1765010717809 ""} diff --git a/puart2/uart_tx_restored/db/intan_m10.hier_info b/puart2/uart_tx_restored/db/intan_m10.hier_info new file mode 100644 index 0000000..2b418ba --- /dev/null +++ b/puart2/uart_tx_restored/db/intan_m10.hier_info @@ -0,0 +1,471 @@ +|ddr_ctrl +sys_clk => sys_clk.IN1 +rst_n => rst_n.IN2 +test_flag => Selector7.IN4 +test_flag => test_flag_led.DATAIN +test_flag => convert_flag_led.DATAIN +miso => miso.IN1 +mosi <= spi_master_2164:u_spi_master_2164.mosi +cs_n <= spi_master_2164:u_spi_master_2164.cs_n +sclk <= spi_master_2164:u_spi_master_2164.sclk +MOSI_ESP32 <= spi_master_esp32:tranfer.mosi +cs_ESP32 <= spi_master_esp32:tranfer.cs +sclk_ESP32 <= spi_master_esp32:tranfer.sclk +tx <= uart_tx:u_uart_pc.tx +test_flag_led <= test_flag.DB_MAX_OUTPUT_PORT_TYPE +convert_flag_led <= test_flag.DB_MAX_OUTPUT_PORT_TYPE + + +|ddr_ctrl|clk_gen:clk_gen_inst +inclk0 => sub_wire1[0].IN1 +c0 <= altpll:altpll_component.clk +c1 <= altpll:altpll_component.clk + + +|ddr_ctrl|clk_gen:clk_gen_inst|altpll:altpll_component +inclk[0] => clk_gen_altpll:auto_generated.inclk[0] +inclk[1] => clk_gen_altpll:auto_generated.inclk[1] +fbin => ~NO_FANOUT~ +pllena => ~NO_FANOUT~ +clkswitch => ~NO_FANOUT~ +areset => ~NO_FANOUT~ +pfdena => ~NO_FANOUT~ +clkena[0] => ~NO_FANOUT~ +clkena[1] => ~NO_FANOUT~ +clkena[2] => ~NO_FANOUT~ +clkena[3] => ~NO_FANOUT~ +clkena[4] => ~NO_FANOUT~ +clkena[5] => ~NO_FANOUT~ +extclkena[0] => ~NO_FANOUT~ +extclkena[1] => ~NO_FANOUT~ +extclkena[2] => ~NO_FANOUT~ +extclkena[3] => ~NO_FANOUT~ +scanclk => ~NO_FANOUT~ +scanclkena => ~NO_FANOUT~ +scanaclr => ~NO_FANOUT~ +scanread => ~NO_FANOUT~ +scanwrite => ~NO_FANOUT~ +scandata => ~NO_FANOUT~ +phasecounterselect[0] => ~NO_FANOUT~ +phasecounterselect[1] => ~NO_FANOUT~ +phasecounterselect[2] => ~NO_FANOUT~ +phasecounterselect[3] => ~NO_FANOUT~ +phaseupdown => ~NO_FANOUT~ +phasestep => ~NO_FANOUT~ +configupdate => ~NO_FANOUT~ +fbmimicbidir <> +clk[0] <= clk[0].DB_MAX_OUTPUT_PORT_TYPE +clk[1] <= clk[1].DB_MAX_OUTPUT_PORT_TYPE +clk[2] <= clk[2].DB_MAX_OUTPUT_PORT_TYPE +clk[3] <= clk[3].DB_MAX_OUTPUT_PORT_TYPE +clk[4] <= clk[4].DB_MAX_OUTPUT_PORT_TYPE +extclk[0] <= +extclk[1] <= +extclk[2] <= +extclk[3] <= +clkbad[0] <= +clkbad[1] <= +enable1 <= +enable0 <= +activeclock <= +clkloss <= +locked <= +scandataout <= +scandone <= +sclkout0 <= +sclkout1 <= +phasedone <= +vcooverrange <= +vcounderrange <= +fbout <= +fref <= +icdrclk <= + + +|ddr_ctrl|clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated +clk[0] <= pll1.CLK +clk[1] <= pll1.CLK1 +clk[2] <= pll1.CLK2 +clk[3] <= pll1.CLK3 +clk[4] <= pll1.CLK4 +inclk[0] => pll1.CLK +inclk[1] => pll1.CLK1 + + +|ddr_ctrl|spi_master_2164:u_spi_master_2164 +sys_clk => dout[0]~reg0.CLK +sys_clk => dout[1]~reg0.CLK +sys_clk => dout[2]~reg0.CLK +sys_clk => dout[3]~reg0.CLK +sys_clk => dout[4]~reg0.CLK +sys_clk => dout[5]~reg0.CLK +sys_clk => dout[6]~reg0.CLK +sys_clk => dout[7]~reg0.CLK +sys_clk => dout[8]~reg0.CLK +sys_clk => dout[9]~reg0.CLK +sys_clk => dout[10]~reg0.CLK +sys_clk => dout[11]~reg0.CLK +sys_clk => dout[12]~reg0.CLK +sys_clk => dout[13]~reg0.CLK +sys_clk => dout[14]~reg0.CLK +sys_clk => dout[15]~reg0.CLK +sys_clk => done~reg0.CLK +sys_clk => dout_r[0].CLK +sys_clk => dout_r[1].CLK +sys_clk => dout_r[2].CLK +sys_clk => dout_r[3].CLK +sys_clk => dout_r[4].CLK +sys_clk => dout_r[5].CLK +sys_clk => dout_r[6].CLK +sys_clk => dout_r[7].CLK +sys_clk => dout_r[8].CLK +sys_clk => dout_r[9].CLK +sys_clk => dout_r[10].CLK +sys_clk => dout_r[11].CLK +sys_clk => dout_r[12].CLK +sys_clk => dout_r[13].CLK +sys_clk => dout_r[14].CLK +sys_clk => dout_r[15].CLK +sys_clk => mosi~reg0.CLK +sys_clk => cs_n~reg0.CLK +sys_clk => sclk~reg0.CLK +sys_clk => cnt[0]~reg0.CLK +sys_clk => cnt[1]~reg0.CLK +sys_clk => cnt[2]~reg0.CLK +sys_clk => cnt[3]~reg0.CLK +sys_clk => cnt[4]~reg0.CLK +sys_clk => cnt[5]~reg0.CLK +sys_clk => cnt[6]~reg0.CLK +rst_n => mosi~reg0.ACLR +rst_n => cs_n~reg0.PRESET +rst_n => sclk~reg0.ACLR +rst_n => dout[0]~reg0.ACLR +rst_n => dout[1]~reg0.ACLR +rst_n => dout[2]~reg0.ACLR +rst_n => dout[3]~reg0.ACLR +rst_n => dout[4]~reg0.ACLR +rst_n => dout[5]~reg0.ACLR +rst_n => dout[6]~reg0.ACLR +rst_n => dout[7]~reg0.ACLR +rst_n => dout[8]~reg0.ACLR +rst_n => dout[9]~reg0.ACLR +rst_n => dout[10]~reg0.ACLR +rst_n => dout[11]~reg0.ACLR +rst_n => dout[12]~reg0.ACLR +rst_n => dout[13]~reg0.ACLR +rst_n => dout[14]~reg0.ACLR +rst_n => dout[15]~reg0.ACLR +rst_n => done~reg0.ACLR +rst_n => cnt[0]~reg0.ACLR +rst_n => cnt[1]~reg0.ACLR +rst_n => cnt[2]~reg0.ACLR +rst_n => cnt[3]~reg0.ACLR +rst_n => cnt[4]~reg0.ACLR +rst_n => cnt[5]~reg0.ACLR +rst_n => cnt[6]~reg0.ACLR +rst_n => dout_r[15].ENA +rst_n => dout_r[14].ENA +rst_n => dout_r[13].ENA +rst_n => dout_r[12].ENA +rst_n => dout_r[11].ENA +rst_n => dout_r[10].ENA +rst_n => dout_r[9].ENA +rst_n => dout_r[8].ENA +rst_n => dout_r[7].ENA +rst_n => dout_r[6].ENA +rst_n => dout_r[5].ENA +rst_n => dout_r[4].ENA +rst_n => dout_r[3].ENA +rst_n => dout_r[2].ENA +rst_n => dout_r[1].ENA +rst_n => dout_r[0].ENA +din[0] => Selector0.IN33 +din[1] => Selector0.IN32 +din[2] => Selector0.IN31 +din[3] => Selector0.IN30 +din[4] => Selector0.IN29 +din[5] => Selector0.IN28 +din[6] => Selector0.IN27 +din[7] => Selector0.IN26 +din[8] => Selector0.IN25 +din[9] => Selector0.IN24 +din[10] => Selector0.IN23 +din[11] => Selector0.IN22 +din[12] => Selector0.IN21 +din[13] => Selector0.IN20 +din[14] => Selector0.IN19 +din[15] => Selector0.IN18 +start => dout_r.OUTPUTSELECT +start => dout_r.OUTPUTSELECT +start => dout_r.OUTPUTSELECT +start => dout_r.OUTPUTSELECT +start => dout_r.OUTPUTSELECT +start => dout_r.OUTPUTSELECT +start => dout_r.OUTPUTSELECT +start => dout_r.OUTPUTSELECT +start => dout_r.OUTPUTSELECT +start => dout_r.OUTPUTSELECT +start => dout_r.OUTPUTSELECT +start => dout_r.OUTPUTSELECT +start => dout_r.OUTPUTSELECT +start => dout_r.OUTPUTSELECT +start => dout_r.OUTPUTSELECT +start => dout_r.OUTPUTSELECT +start => sclk~reg0.ENA +start => cs_n~reg0.ENA +start => mosi~reg0.ENA +dout[0] <= dout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dout[1] <= dout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dout[2] <= dout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dout[3] <= dout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dout[4] <= dout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dout[5] <= dout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dout[6] <= dout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dout[7] <= dout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dout[8] <= dout[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dout[9] <= dout[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dout[10] <= dout[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dout[11] <= dout[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dout[12] <= dout[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dout[13] <= dout[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dout[14] <= dout[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dout[15] <= dout[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +done <= done~reg0.DB_MAX_OUTPUT_PORT_TYPE +sclk <= sclk~reg0.DB_MAX_OUTPUT_PORT_TYPE +cs_n <= cs_n~reg0.DB_MAX_OUTPUT_PORT_TYPE +mosi <= mosi~reg0.DB_MAX_OUTPUT_PORT_TYPE +miso => dout_r.DATAB +cnt[0] <= cnt[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +cnt[1] <= cnt[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +cnt[2] <= cnt[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +cnt[3] <= cnt[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +cnt[4] <= cnt[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +cnt[5] <= cnt[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +cnt[6] <= cnt[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|ddr_ctrl|spi_master_esp32:tranfer +clk => done~reg0.CLK +clk => shift_reg[0].CLK +clk => shift_reg[1].CLK +clk => shift_reg[2].CLK +clk => shift_reg[3].CLK +clk => shift_reg[4].CLK +clk => shift_reg[5].CLK +clk => shift_reg[6].CLK +clk => shift_reg[7].CLK +clk => shift_reg[8].CLK +clk => shift_reg[9].CLK +clk => shift_reg[10].CLK +clk => shift_reg[11].CLK +clk => shift_reg[12].CLK +clk => shift_reg[13].CLK +clk => shift_reg[14].CLK +clk => shift_reg[15].CLK +clk => bit_cnt[0].CLK +clk => bit_cnt[1].CLK +clk => bit_cnt[2].CLK +clk => bit_cnt[3].CLK +clk => sclk_reg.CLK +clk => cs~reg0.CLK +clk => state~4.DATAIN +rst_n => done~reg0.ACLR +rst_n => shift_reg[0].ACLR +rst_n => shift_reg[1].ACLR +rst_n => shift_reg[2].ACLR +rst_n => shift_reg[3].ACLR +rst_n => shift_reg[4].ACLR +rst_n => shift_reg[5].ACLR +rst_n => shift_reg[6].ACLR +rst_n => shift_reg[7].ACLR +rst_n => shift_reg[8].ACLR +rst_n => shift_reg[9].ACLR +rst_n => shift_reg[10].ACLR +rst_n => shift_reg[11].ACLR +rst_n => shift_reg[12].ACLR +rst_n => shift_reg[13].ACLR +rst_n => shift_reg[14].ACLR +rst_n => shift_reg[15].ACLR +rst_n => bit_cnt[0].ACLR +rst_n => bit_cnt[1].ACLR +rst_n => bit_cnt[2].ACLR +rst_n => bit_cnt[3].ACLR +rst_n => sclk_reg.ACLR +rst_n => cs~reg0.PRESET +rst_n => state~6.DATAIN +start => state.OUTPUTSELECT +start => state.OUTPUTSELECT +start => state.OUTPUTSELECT +start => done~reg0.ENA +start => cs~reg0.ENA +start => sclk_reg.ENA +start => bit_cnt[3].ENA +start => bit_cnt[2].ENA +start => bit_cnt[1].ENA +start => bit_cnt[0].ENA +start => shift_reg[15].ENA +start => shift_reg[14].ENA +start => shift_reg[13].ENA +start => shift_reg[12].ENA +start => shift_reg[11].ENA +start => shift_reg[10].ENA +start => shift_reg[9].ENA +start => shift_reg[8].ENA +start => shift_reg[7].ENA +start => shift_reg[6].ENA +start => shift_reg[5].ENA +start => shift_reg[4].ENA +start => shift_reg[3].ENA +start => shift_reg[2].ENA +start => shift_reg[1].ENA +start => shift_reg[0].ENA +din[0] => Selector18.IN1 +din[1] => Selector17.IN1 +din[2] => Selector16.IN1 +din[3] => Selector15.IN1 +din[4] => Selector14.IN1 +din[5] => Selector13.IN1 +din[6] => Selector12.IN1 +din[7] => Selector11.IN1 +din[8] => Selector10.IN1 +din[9] => Selector9.IN1 +din[10] => Selector8.IN1 +din[11] => Selector7.IN1 +din[12] => Selector6.IN1 +din[13] => Selector5.IN1 +din[14] => Selector4.IN1 +din[15] => Selector3.IN1 +done <= done~reg0.DB_MAX_OUTPUT_PORT_TYPE +sclk <= sclk_reg.DB_MAX_OUTPUT_PORT_TYPE +mosi <= shift_reg[15].DB_MAX_OUTPUT_PORT_TYPE +cs <= cs~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|ddr_ctrl|uart_tx:u_uart_pc +clk => tx_bit_counter[0].CLK +clk => tx_bit_counter[1].CLK +clk => tx_bit_counter[2].CLK +clk => tx_bit_counter[3].CLK +clk => data_to_send[0].CLK +clk => data_to_send[1].CLK +clk => data_to_send[2].CLK +clk => data_to_send[3].CLK +clk => data_to_send[4].CLK +clk => data_to_send[5].CLK +clk => data_to_send[6].CLK +clk => data_to_send[7].CLK +clk => tx_shift_reg[0].CLK +clk => tx_shift_reg[1].CLK +clk => tx_shift_reg[2].CLK +clk => tx_shift_reg[3].CLK +clk => tx_shift_reg[4].CLK +clk => tx_shift_reg[5].CLK +clk => tx_shift_reg[6].CLK +clk => tx_shift_reg[7].CLK +clk => tx_shift_reg[8].CLK +clk => tx_shift_reg[9].CLK +clk => tx_done~reg0.CLK +clk => baud_counter[0].CLK +clk => baud_counter[1].CLK +clk => baud_counter[2].CLK +clk => baud_counter[3].CLK +clk => baud_counter[4].CLK +clk => baud_counter[5].CLK +clk => baud_counter[6].CLK +clk => baud_counter[7].CLK +clk => baud_counter[8].CLK +clk => baud_counter[9].CLK +clk => baud_counter[10].CLK +clk => baud_counter[11].CLK +clk => baud_counter[12].CLK +clk => baud_counter[13].CLK +clk => baud_counter[14].CLK +clk => baud_counter[15].CLK +clk => byte_select~2.DATAIN +clk => tx_state~3.DATAIN +rst => tx_shift_reg[0].PRESET +rst => tx_shift_reg[1].PRESET +rst => tx_shift_reg[2].PRESET +rst => tx_shift_reg[3].PRESET +rst => tx_shift_reg[4].PRESET +rst => tx_shift_reg[5].PRESET +rst => tx_shift_reg[6].PRESET +rst => tx_shift_reg[7].PRESET +rst => tx_shift_reg[8].PRESET +rst => tx_shift_reg[9].PRESET +rst => tx_done~reg0.ACLR +rst => baud_counter[0].ACLR +rst => baud_counter[1].ACLR +rst => baud_counter[2].ACLR +rst => baud_counter[3].ACLR +rst => baud_counter[4].ACLR +rst => baud_counter[5].ACLR +rst => baud_counter[6].ACLR +rst => baud_counter[7].ACLR +rst => baud_counter[8].ACLR +rst => baud_counter[9].ACLR +rst => baud_counter[10].ACLR +rst => baud_counter[11].ACLR +rst => baud_counter[12].ACLR +rst => baud_counter[13].ACLR +rst => baud_counter[14].ACLR +rst => baud_counter[15].ACLR +rst => byte_select~4.DATAIN +rst => tx_state~5.DATAIN +rst => tx_bit_counter[0].ENA +rst => data_to_send[7].ENA +rst => data_to_send[6].ENA +rst => data_to_send[5].ENA +rst => data_to_send[4].ENA +rst => data_to_send[3].ENA +rst => data_to_send[2].ENA +rst => data_to_send[1].ENA +rst => data_to_send[0].ENA +rst => tx_bit_counter[3].ENA +rst => tx_bit_counter[2].ENA +rst => tx_bit_counter[1].ENA +tx_start => data_to_send.OUTPUTSELECT +tx_start => data_to_send.OUTPUTSELECT +tx_start => data_to_send.OUTPUTSELECT +tx_start => data_to_send.OUTPUTSELECT +tx_start => data_to_send.OUTPUTSELECT +tx_start => data_to_send.OUTPUTSELECT +tx_start => data_to_send.OUTPUTSELECT +tx_start => data_to_send.OUTPUTSELECT +tx_start => tx_shift_reg.OUTPUTSELECT +tx_start => tx_shift_reg.OUTPUTSELECT +tx_start => tx_shift_reg.OUTPUTSELECT +tx_start => tx_shift_reg.OUTPUTSELECT +tx_start => tx_shift_reg.OUTPUTSELECT +tx_start => tx_shift_reg.OUTPUTSELECT +tx_start => tx_shift_reg.OUTPUTSELECT +tx_start => tx_shift_reg.OUTPUTSELECT +tx_start => tx_shift_reg.OUTPUTSELECT +tx_start => tx_shift_reg.OUTPUTSELECT +tx_start => tx_bit_counter.OUTPUTSELECT +tx_start => tx_bit_counter.OUTPUTSELECT +tx_start => tx_bit_counter.OUTPUTSELECT +tx_start => tx_bit_counter.OUTPUTSELECT +tx_start => tx_state.OUTPUTSELECT +tx_start => tx_state.OUTPUTSELECT +tx_start => tx_done.OUTPUTSELECT +tx_data[0] => data_to_send.DATAA +tx_data[1] => data_to_send.DATAA +tx_data[2] => data_to_send.DATAA +tx_data[3] => data_to_send.DATAA +tx_data[4] => data_to_send.DATAA +tx_data[5] => data_to_send.DATAA +tx_data[6] => data_to_send.DATAA +tx_data[7] => data_to_send.DATAA +tx_data[8] => data_to_send.DATAB +tx_data[9] => data_to_send.DATAB +tx_data[10] => data_to_send.DATAB +tx_data[11] => data_to_send.DATAB +tx_data[12] => data_to_send.DATAB +tx_data[13] => data_to_send.DATAB +tx_data[14] => data_to_send.DATAB +tx_data[15] => data_to_send.DATAB +tx <= tx_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE +tx_done <= tx_done~reg0.DB_MAX_OUTPUT_PORT_TYPE + + diff --git a/puart2/uart_tx_restored/db/intan_m10.hif b/puart2/uart_tx_restored/db/intan_m10.hif new file mode 100644 index 0000000..00f13d7 Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.hif differ diff --git a/puart2/uart_tx_restored/db/intan_m10.lpc.html b/puart2/uart_tx_restored/db/intan_m10.lpc.html new file mode 100644 index 0000000..f00e4e0 --- /dev/null +++ b/puart2/uart_tx_restored/db/intan_m10.lpc.html @@ -0,0 +1,98 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
u_uart_pc19000200000000
tranfer19000400000000
u_spi_master_2164200002000000000
clk_gen_inst|altpll_component|auto_generated2000500000000
clk_gen_inst1000200000000
diff --git a/puart2/uart_tx_restored/db/intan_m10.lpc.rdb b/puart2/uart_tx_restored/db/intan_m10.lpc.rdb new file mode 100644 index 0000000..d37f13c Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.lpc.rdb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.lpc.txt b/puart2/uart_tx_restored/db/intan_m10.lpc.txt new file mode 100644 index 0000000..f4822c3 --- /dev/null +++ b/puart2/uart_tx_restored/db/intan_m10.lpc.txt @@ -0,0 +1,11 @@ ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++----------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++----------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; u_uart_pc ; 19 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; tranfer ; 19 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; u_spi_master_2164 ; 20 ; 0 ; 0 ; 0 ; 20 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; clk_gen_inst|altpll_component|auto_generated ; 2 ; 0 ; 0 ; 0 ; 5 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; clk_gen_inst ; 1 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ++----------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/puart2/uart_tx_restored/db/intan_m10.map.ammdb b/puart2/uart_tx_restored/db/intan_m10.map.ammdb new file mode 100644 index 0000000..295dbe4 Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.map.ammdb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.map.bpm b/puart2/uart_tx_restored/db/intan_m10.map.bpm new file mode 100644 index 0000000..63f8b21 Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.map.bpm differ diff --git a/puart2/uart_tx_restored/db/intan_m10.map.cdb b/puart2/uart_tx_restored/db/intan_m10.map.cdb new file mode 100644 index 0000000..2d7cb3f Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.map.cdb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.map.hdb b/puart2/uart_tx_restored/db/intan_m10.map.hdb new file mode 100644 index 0000000..cce6c0b Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.map.hdb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.map.kpt b/puart2/uart_tx_restored/db/intan_m10.map.kpt new file mode 100644 index 0000000..2bad48d Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.map.kpt differ diff --git a/puart2/uart_tx_restored/db/intan_m10.map.logdb b/puart2/uart_tx_restored/db/intan_m10.map.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/puart2/uart_tx_restored/db/intan_m10.map.logdb @@ -0,0 +1 @@ +v1 diff --git a/puart2/uart_tx_restored/db/intan_m10.map.qmsg b/puart2/uart_tx_restored/db/intan_m10.map.qmsg new file mode 100644 index 0000000..1c86445 --- /dev/null +++ b/puart2/uart_tx_restored/db/intan_m10.map.qmsg @@ -0,0 +1,37 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1765010702752 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition " "Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1765010702753 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 6 16:45:02 2025 " "Processing started: Sat Dec 6 16:45:02 2025" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1765010702753 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765010702753 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off intan_m10 -c intan_m10 " "Command: quartus_map --read_settings_files=on --write_settings_files=off intan_m10 -c intan_m10" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765010702753 ""} +{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "4 " "Parallel compilation is enabled and will use up to 4 processors" { } { } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Analysis & Synthesis" 0 -1 1765010703178 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spi_master_2164.v 1 1 " "Found 1 design units, including 1 entities, in source file spi_master_2164.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi_master_2164 " "Found entity 1: spi_master_2164" { } { { "spi_master_2164.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/spi_master_2164.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1765010710816 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765010710816 ""} +{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "ddr_ctrl.v(151) " "Verilog HDL information at ddr_ctrl.v(151): always construct contains both blocking and non-blocking assignments" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 151 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1765010710818 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr_ctrl.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr_ctrl.v" { { "Info" "ISGN_ENTITY_NAME" "1 ddr_ctrl " "Found entity 1: ddr_ctrl" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1765010710818 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765010710818 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clk_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file clk_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_gen " "Found entity 1: clk_gen" { } { { "clk_gen.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/clk_gen.v" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1765010710821 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765010710821 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "done DONE spi_master_esp32.v(6) " "Verilog HDL Declaration information at spi_master_esp32.v(6): object \"done\" differs only in case from object \"DONE\" in the same scope" { } { { "spi_master_esp32.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/spi_master_esp32.v" 6 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1765010710822 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spi_master_esp32.v 1 1 " "Found 1 design units, including 1 entities, in source file spi_master_esp32.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi_master_esp32 " "Found entity 1: spi_master_esp32" { } { { "spi_master_esp32.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/spi_master_esp32.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1765010710823 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765010710823 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "intan_m10.v 1 1 " "Found 1 design units, including 1 entities, in source file intan_m10.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart_tx " "Found entity 1: uart_tx" { } { { "intan_m10.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/intan_m10.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1765010710824 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765010710824 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "ddr_ctrl " "Elaborating entity \"ddr_ctrl\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1765010710856 ""} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "received_data ddr_ctrl.v(71) " "Verilog HDL or VHDL warning at ddr_ctrl.v(71): object \"received_data\" assigned a value but never read" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 71 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1765010710857 "|ddr_ctrl"} +{ "Warning" "WVRFX_L2_VERI_ASSUMED_INCOMPLETE_CASE" "ddr_ctrl.v(153) " "Verilog HDL warning at ddr_ctrl.v(153): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 153 0 0 } } } 0 10763 "Verilog HDL warning at %1!s!: case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness" 0 0 "Analysis & Synthesis" 0 -1 1765010710859 "|ddr_ctrl"} +{ "Warning" "WVRFX_L2_VERI_FULL_CASE_DIRECTIVE_EFFECTIVE" "ddr_ctrl.v(153) " "Verilog HDL Case Statement warning at ddr_ctrl.v(153): honored full_case synthesis attribute - differences between design synthesis and simulation may occur" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 153 0 0 } } } 0 10208 "Verilog HDL Case Statement warning at %1!s!: honored full_case synthesis attribute - differences between design synthesis and simulation may occur" 0 0 "Analysis & Synthesis" 0 -1 1765010710859 "|ddr_ctrl"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_gen clk_gen:clk_gen_inst " "Elaborating entity \"clk_gen\" for hierarchy \"clk_gen:clk_gen_inst\"" { } { { "ddr_ctrl.v" "clk_gen_inst" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 204 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765010710873 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll clk_gen:clk_gen_inst\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"clk_gen:clk_gen_inst\|altpll:altpll_component\"" { } { { "clk_gen.v" "altpll_component" { Text "E:/FPGA/20240726/uart_tx_restored/clk_gen.v" 95 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765010710911 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "clk_gen:clk_gen_inst\|altpll:altpll_component " "Elaborated megafunction instantiation \"clk_gen:clk_gen_inst\|altpll:altpll_component\"" { } { { "clk_gen.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/clk_gen.v" 95 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765010710914 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "clk_gen:clk_gen_inst\|altpll:altpll_component " "Instantiated megafunction \"clk_gen:clk_gen_inst\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 625 " "Parameter \"clk0_divide_by\" = \"625\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 6 " "Parameter \"clk0_multiply_by\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 625 " "Parameter \"clk1_divide_by\" = \"625\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 12 " "Parameter \"clk1_multiply_by\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 0 " "Parameter \"clk1_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 83333 " "Parameter \"inclk0_input_frequency\" = \"83333\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family MAX 10 " "Parameter \"intended_device_family\" = \"MAX 10\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=clk_gen " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=clk_gen\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_UNUSED " "Parameter \"port_locked\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Parameter \"port_clk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010710914 ""} } { { "clk_gen.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/clk_gen.v" 95 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1765010710914 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/clk_gen_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/clk_gen_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_gen_altpll " "Found entity 1: clk_gen_altpll" { } { { "db/clk_gen_altpll.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/db/clk_gen_altpll.v" 30 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1765010710965 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765010710965 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_gen_altpll clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated " "Elaborating entity \"clk_gen_altpll\" for hierarchy \"clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "f:/quartus_prime_lite/quartus/libraries/megafunctions/altpll.tdf" 898 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765010710966 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi_master_2164 spi_master_2164:u_spi_master_2164 " "Elaborating entity \"spi_master_2164\" for hierarchy \"spi_master_2164:u_spi_master_2164\"" { } { { "ddr_ctrl.v" "u_spi_master_2164" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 221 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765010710968 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi_master_esp32 spi_master_esp32:tranfer " "Elaborating entity \"spi_master_esp32\" for hierarchy \"spi_master_esp32:tranfer\"" { } { { "ddr_ctrl.v" "tranfer" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 234 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765010710969 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 spi_master_esp32.v(49) " "Verilog HDL assignment warning at spi_master_esp32.v(49): truncated value with size 32 to match size of target (4)" { } { { "spi_master_esp32.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/spi_master_esp32.v" 49 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1765010710970 "|ddr_ctrl|spi_master_esp32:tranfer"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_tx uart_tx:u_uart_pc " "Elaborating entity \"uart_tx\" for hierarchy \"uart_tx:u_uart_pc\"" { } { { "ddr_ctrl.v" "u_uart_pc" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 243 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765010710970 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 intan_m10.v(33) " "Verilog HDL assignment warning at intan_m10.v(33): truncated value with size 32 to match size of target (16)" { } { { "intan_m10.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/intan_m10.v" 33 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1765010710971 "|ddr_ctrl|uart_tx:u_uart_pc"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 intan_m10.v(74) " "Verilog HDL assignment warning at intan_m10.v(74): truncated value with size 32 to match size of target (4)" { } { { "intan_m10.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/intan_m10.v" 74 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1765010710971 "|ddr_ctrl|uart_tx:u_uart_pc"} +{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "spi_master_2164.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/spi_master_2164.v" 11 -1 0 } } { "intan_m10.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/intan_m10.v" 44 -1 0 } } { "ddr_ctrl.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 146 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 -1 1765010711318 ""} +{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Analysis & Synthesis" 0 -1 1765010711318 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "MOSI_ESP32 GND " "Pin \"MOSI_ESP32\" is stuck at GND" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 12 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1765010711356 "|ddr_ctrl|MOSI_ESP32"} { "Warning" "WMLS_MLS_STUCK_PIN" "cs_ESP32 VCC " "Pin \"cs_ESP32\" is stuck at VCC" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 13 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1765010711356 "|ddr_ctrl|cs_ESP32"} { "Warning" "WMLS_MLS_STUCK_PIN" "sclk_ESP32 GND " "Pin \"sclk_ESP32\" is stuck at GND" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 14 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1765010711356 "|ddr_ctrl|sclk_ESP32"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1765010711356 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1765010711400 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "6 " "6 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1765010711787 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/FPGA/20240726/uart_tx_restored/output_files/intan_m10.map.smsg " "Generated suppressed messages file E:/FPGA/20240726/uart_tx_restored/output_files/intan_m10.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765010711830 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "1 0 1 0 0 " "Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1765010711917 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765010711917 ""} +{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "miso " "No output dependent on input pin \"miso\"" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 7 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1765010711953 "|ddr_ctrl|miso"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1765010711953 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "154 " "Implemented 154 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Implemented 4 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1765010711953 ""} { "Info" "ICUT_CUT_TM_OPINS" "9 " "Implemented 9 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1765010711953 ""} { "Info" "ICUT_CUT_TM_LCELLS" "140 " "Implemented 140 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1765010711953 ""} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Implemented 1 PLLs" { } { } 0 21065 "Implemented %1!d! PLLs" 0 0 "Design Software" 0 -1 1765010711953 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1765010711953 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4777 " "Peak virtual memory: 4777 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1765010711971 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 6 16:45:11 2025 " "Processing ended: Sat Dec 6 16:45:11 2025" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1765010711971 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1765010711971 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1765010711971 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1765010711971 ""} diff --git a/puart2/uart_tx_restored/db/intan_m10.map.rdb b/puart2/uart_tx_restored/db/intan_m10.map.rdb new file mode 100644 index 0000000..550e7e4 Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.map.rdb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.map_bb.cdb b/puart2/uart_tx_restored/db/intan_m10.map_bb.cdb new file mode 100644 index 0000000..e30e27c Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.map_bb.cdb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.map_bb.hdb b/puart2/uart_tx_restored/db/intan_m10.map_bb.hdb new file mode 100644 index 0000000..8fde84b Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.map_bb.hdb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.map_bb.logdb b/puart2/uart_tx_restored/db/intan_m10.map_bb.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/puart2/uart_tx_restored/db/intan_m10.map_bb.logdb @@ -0,0 +1 @@ +v1 diff --git a/puart2/uart_tx_restored/db/intan_m10.pow.qmsg b/puart2/uart_tx_restored/db/intan_m10.pow.qmsg new file mode 100644 index 0000000..b7db352 --- /dev/null +++ b/puart2/uart_tx_restored/db/intan_m10.pow.qmsg @@ -0,0 +1,19 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1765010725981 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Power Analyzer Quartus Prime " "Running Quartus Prime Power Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition " "Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1765010725981 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 6 16:45:25 2025 " "Processing started: Sat Dec 6 16:45:25 2025" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1765010725981 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Power Analyzer" 0 -1 1765010725981 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_pow --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10 " "Command: quartus_pow --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10" { } { } 0 0 "Command: %1!s!" 0 0 "Power Analyzer" 0 -1 1765010725981 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Power Analyzer" 0 -1 1765010726325 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Power Analyzer" 0 -1 1765010726325 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "intan_m10.sdc " "Synopsys Design Constraints File file not found: 'intan_m10.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Power Analyzer" 0 -1 1765010726566 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "sys_clk " "Node: sys_clk was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi_master_2164:u_spi_master_2164\|cnt\[0\] sys_clk " "Register spi_master_2164:u_spi_master_2164\|cnt\[0\] is being clocked by sys_clk" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1765010726567 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Power Analyzer" 0 -1 1765010726567 "|ddr_ctrl|sys_clk"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi_master_2164:u_spi_master_2164\|cs_n " "Node: spi_master_2164:u_spi_master_2164\|cs_n was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register state\[7\] spi_master_2164:u_spi_master_2164\|cs_n " "Register state\[7\] is being clocked by spi_master_2164:u_spi_master_2164\|cs_n" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1765010726567 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Power Analyzer" 0 -1 1765010726567 "|ddr_ctrl|spi_master_2164:u_spi_master_2164|cs_n"} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Power Analyzer" 0 -1 1765010726567 ""} +{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Node: clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 83.333 " "Node: clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 83.333" { } { } 0 332056 "%1!s!" 0 0 "Design Software" 0 -1 1765010726569 ""} { "Warning" "WSTA_GENERIC_WARNING" "Node: clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] was found missing 1 generated clock that corresponds to a base clock with a period of: 83.333 " "Node: clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] was found missing 1 generated clock that corresponds to a base clock with a period of: 83.333" { } { } 0 332056 "%1!s!" 0 0 "Design Software" 0 -1 1765010726569 ""} } { } 0 332056 "%1!s!" 0 0 "Power Analyzer" 0 -1 1765010726569 ""} +{ "Info" "IPVA_PVA_START_CALCULATION" "" "Starting Vectorless Power Activity Estimation" { } { } 0 223000 "Starting Vectorless Power Activity Estimation" 0 0 "Power Analyzer" 0 -1 1765010726573 ""} +{ "Warning" "WPUTIL_PUTIL_NO_CLK_DOMAINS_FOUND" "" "Relative toggle rates could not be calculated because no clock domain could be identified for some nodes" { } { } 0 222013 "Relative toggle rates could not be calculated because no clock domain could be identified for some nodes" 0 0 "Power Analyzer" 0 -1 1765010726574 ""} +{ "Info" "IPVA_PVA_END_CALCULATION" "" "Completed Vectorless Power Activity Estimation" { } { } 0 223001 "Completed Vectorless Power Activity Estimation" 0 0 "Power Analyzer" 0 -1 1765010726577 ""} +{ "Info" "IPATFAM_USING_ADVANCED_IO_POWER" "" "Using Advanced I/O Power to simulate I/O buffers with the specified board trace model" { } { } 0 218000 "Using Advanced I/O Power to simulate I/O buffers with the specified board trace model" 0 0 "Power Analyzer" 0 -1 1765010726758 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Power Analyzer" 0 -1 1765010726790 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Power Analyzer" 0 -1 1765010727104 ""} +{ "Info" "IPAN_AVG_TOGGLE_RATE_PER_DESIGN" "0.000 millions of transitions / sec " "Average toggle rate for this design is 0.000 millions of transitions / sec" { } { } 0 215049 "Average toggle rate for this design is %1!s!" 0 0 "Power Analyzer" 0 -1 1765010727308 ""} +{ "Info" "IPAN_PAN_TOTAL_POWER_ESTIMATION" "144.69 mW " "Total thermal power estimate for the design is 144.69 mW" { } { { "f:/quartus_prime_lite/quartus/bin64/Report_Window_01.qrpt" "" { Report "f:/quartus_prime_lite/quartus/bin64/Report_Window_01.qrpt" "Compiler" "" "" "" "" { } "PowerPlay Power Analyzer Summary" } } } 0 215031 "Total thermal power estimate for the design is %1!s!" 0 0 "Power Analyzer" 0 -1 1765010727374 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Power Analyzer 0 s 8 s Quartus Prime " "Quartus Prime Power Analyzer was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4814 " "Peak virtual memory: 4814 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1765010727559 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 6 16:45:27 2025 " "Processing ended: Sat Dec 6 16:45:27 2025" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1765010727559 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1765010727559 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1765010727559 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Power Analyzer" 0 -1 1765010727559 ""} diff --git a/puart2/uart_tx_restored/db/intan_m10.pplq.rdb b/puart2/uart_tx_restored/db/intan_m10.pplq.rdb new file mode 100644 index 0000000..9ff733e Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.pplq.rdb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.pre_map.hdb b/puart2/uart_tx_restored/db/intan_m10.pre_map.hdb new file mode 100644 index 0000000..3a0cebe Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.pre_map.hdb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.restore.qmsg b/puart2/uart_tx_restored/db/intan_m10.restore.qmsg new file mode 100644 index 0000000..11b0da8 --- /dev/null +++ b/puart2/uart_tx_restored/db/intan_m10.restore.qmsg @@ -0,0 +1,4 @@ +{ "Info" "0" "" "Successfully restored 'E:/FPGA/20240726/uart_tx.qar' into the 'E:/FPGA/20240726/uart_tx_restored/' directory" { } { } 0 0 "Successfully restored 'E:/FPGA/20240726/uart_tx.qar' into the 'E:/FPGA/20240726/uart_tx_restored/' directory" 0 0 "Shell" 0 0 1765006933692 ""} +{ "Info" "0" "" "Generated report 'intan_m10.restore.rpt'" { } { } 0 0 "Generated report 'intan_m10.restore.rpt'" 0 0 "Shell" 0 0 1765006933693 ""} +{ "Info" "IQEXE_TCL_SCRIPT_STATUS" "f:/quartus_prime_lite/quartus/common/tcl/apps/qpm/qar.tcl " "Evaluation of Tcl script f:/quartus_prime_lite/quartus/common/tcl/apps/qpm/qar.tcl was successful" { } { } 0 23030 "Evaluation of Tcl script %1!s! was successful" 0 0 "Shell" 0 -1 1765006933705 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Shell 0 s 41 s Quartus Prime " "Quartus Prime Shell was successful. 0 errors, 41 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4822 " "Peak virtual memory: 4822 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1765006933705 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 6 15:42:13 2025 " "Processing ended: Sat Dec 6 15:42:13 2025" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1765006933705 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1765006933705 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1765006933705 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Shell" 0 -1 1765006933705 ""} diff --git a/puart2/uart_tx_restored/db/intan_m10.root_partition.map.reg_db.cdb b/puart2/uart_tx_restored/db/intan_m10.root_partition.map.reg_db.cdb new file mode 100644 index 0000000..ef5f5c4 Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.root_partition.map.reg_db.cdb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.routing.rdb b/puart2/uart_tx_restored/db/intan_m10.routing.rdb new file mode 100644 index 0000000..8555238 Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.routing.rdb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.rtlv.hdb b/puart2/uart_tx_restored/db/intan_m10.rtlv.hdb new file mode 100644 index 0000000..e4b56d1 Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.rtlv.hdb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.rtlv_sg.cdb b/puart2/uart_tx_restored/db/intan_m10.rtlv_sg.cdb new file mode 100644 index 0000000..d390fe2 Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.rtlv_sg.cdb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.rtlv_sg_swap.cdb b/puart2/uart_tx_restored/db/intan_m10.rtlv_sg_swap.cdb new file mode 100644 index 0000000..46b31a1 Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.rtlv_sg_swap.cdb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.sld_design_entry.sci b/puart2/uart_tx_restored/db/intan_m10.sld_design_entry.sci new file mode 100644 index 0000000..adb011c Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.sld_design_entry.sci differ diff --git a/puart2/uart_tx_restored/db/intan_m10.sld_design_entry_dsc.sci b/puart2/uart_tx_restored/db/intan_m10.sld_design_entry_dsc.sci new file mode 100644 index 0000000..adb011c Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.sld_design_entry_dsc.sci differ diff --git a/puart2/uart_tx_restored/db/intan_m10.smart_action.txt b/puart2/uart_tx_restored/db/intan_m10.smart_action.txt new file mode 100644 index 0000000..c8e8a13 --- /dev/null +++ b/puart2/uart_tx_restored/db/intan_m10.smart_action.txt @@ -0,0 +1 @@ +DONE diff --git a/puart2/uart_tx_restored/db/intan_m10.smp_dump.txt b/puart2/uart_tx_restored/db/intan_m10.smp_dump.txt new file mode 100644 index 0000000..a2a52d9 --- /dev/null +++ b/puart2/uart_tx_restored/db/intan_m10.smp_dump.txt @@ -0,0 +1,23 @@ + +State Machine - |ddr_ctrl|state_top +Name state_top.SEND3 state_top.SEND2 state_top.SEND1 state_top.IDLE +state_top.IDLE 0 0 0 0 +state_top.SEND1 0 0 1 1 +state_top.SEND2 0 1 0 1 +state_top.SEND3 1 0 0 1 + +State Machine - |ddr_ctrl|uart_tx:u_uart_pc|byte_select +Name byte_select.01 +byte_select.00 0 +byte_select.01 1 + +State Machine - |ddr_ctrl|uart_tx:u_uart_pc|tx_state +Name tx_state.0001 +tx_state.0000 0 +tx_state.0001 1 + +State Machine - |ddr_ctrl|spi_master_esp32:tranfer|state +Name state.IDLE state.DONE state.TRANSFER +state.IDLE 0 0 0 +state.TRANSFER 1 0 1 +state.DONE 1 1 0 diff --git a/puart2/uart_tx_restored/db/intan_m10.sta.qmsg b/puart2/uart_tx_restored/db/intan_m10.sta.qmsg new file mode 100644 index 0000000..5597d9f --- /dev/null +++ b/puart2/uart_tx_restored/db/intan_m10.sta.qmsg @@ -0,0 +1,44 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1765010728861 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition " "Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1765010728861 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 6 16:45:28 2025 " "Processing started: Sat Dec 6 16:45:28 2025" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1765010728861 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1765010728861 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta intan_m10 -c intan_m10 " "Command: quartus_sta intan_m10 -c intan_m10" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1765010728861 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1765010728984 ""} +{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "4 " "Parallel compilation is enabled and will use up to 4 processors" { } { } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Timing Analyzer" 0 -1 1765010729129 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1765010729160 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1765010729160 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "intan_m10.sdc " "Synopsys Design Constraints File file not found: 'intan_m10.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1765010729265 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "generated clocks \"derive_pll_clocks -create_base_clocks\" " "No user constrained generated clocks found in the design. Calling \"derive_pll_clocks -create_base_clocks\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1765010729265 ""} +{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_clock -period 83.333 -waveform \{0.000 41.666\} -name sys_clk sys_clk " "create_clock -period 83.333 -waveform \{0.000 41.666\} -name sys_clk sys_clk" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1765010729266 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 625 -multiply_by 6 -duty_cycle 50.00 -name \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 625 -multiply_by 6 -duty_cycle 50.00 -name \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1765010729266 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 625 -multiply_by 12 -duty_cycle 50.00 -name \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 625 -multiply_by 12 -duty_cycle 50.00 -name \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1765010729266 ""} } { } 0 332110 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1765010729266 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1765010729266 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name spi_master_2164:u_spi_master_2164\|cs_n spi_master_2164:u_spi_master_2164\|cs_n " "create_clock -period 1.000 -name spi_master_2164:u_spi_master_2164\|cs_n spi_master_2164:u_spi_master_2164\|cs_n" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1765010729266 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1765010729266 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1765010729267 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1765010729268 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1765010729268 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1765010729275 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1765010729278 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1765010729280 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -6.111 " "Worst-case setup slack is -6.111" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729287 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729287 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.111 -6.111 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -6.111 -6.111 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729287 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.600 -7.693 spi_master_2164:u_spi_master_2164\|cs_n " " -0.600 -7.693 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729287 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4335.838 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4335.838 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729287 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1765010729287 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.362 " "Worst-case hold slack is 0.362" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.362 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.362 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.362 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.362 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.362 0.000 spi_master_2164:u_spi_master_2164\|cs_n " " 0.362 0.000 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729292 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1765010729292 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1765010729301 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1765010729306 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.487 " "Worst-case minimum pulse width slack is -1.487" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729315 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729315 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.487 -46.097 spi_master_2164:u_spi_master_2164\|cs_n " " -1.487 -46.097 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729315 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 41.541 0.000 sys_clk " " 41.541 0.000 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729315 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2169.851 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 2169.851 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729315 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4339.991 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4339.991 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729315 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1765010729315 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1765010729325 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1765010729347 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1765010729661 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1765010729716 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1765010729722 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -5.633 " "Worst-case setup slack is -5.633" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729735 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729735 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.633 -5.633 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -5.633 -5.633 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729735 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.518 -5.401 spi_master_2164:u_spi_master_2164\|cs_n " " -0.518 -5.401 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729735 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4336.023 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4336.023 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729735 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1765010729735 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.324 " "Worst-case hold slack is 0.324" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729738 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729738 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.324 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.324 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729738 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.324 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.324 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729738 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.324 0.000 spi_master_2164:u_spi_master_2164\|cs_n " " 0.324 0.000 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729738 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1765010729738 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1765010729751 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1765010729754 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.487 " "Worst-case minimum pulse width slack is -1.487" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729764 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729764 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.487 -46.097 spi_master_2164:u_spi_master_2164\|cs_n " " -1.487 -46.097 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729764 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 41.545 0.000 sys_clk " " 41.545 0.000 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729764 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2169.828 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 2169.828 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729764 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4340.001 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4340.001 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729764 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1765010729764 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1765010729774 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1765010729916 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1765010729917 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.102 " "Worst-case setup slack is -2.102" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729918 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729918 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.102 -2.102 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.102 -2.102 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729918 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.320 0.000 spi_master_2164:u_spi_master_2164\|cs_n " " 0.320 0.000 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729918 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4338.451 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4338.451 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729918 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1765010729918 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.150 " "Worst-case hold slack is 0.150" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729930 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729930 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.150 0.000 spi_master_2164:u_spi_master_2164\|cs_n " " 0.150 0.000 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729930 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.152 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.152 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729930 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.152 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.152 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729930 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1765010729930 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1765010729932 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1765010729942 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.000 " "Worst-case minimum pulse width slack is -1.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729951 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729951 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.000 -31.000 spi_master_2164:u_spi_master_2164\|cs_n " " -1.000 -31.000 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729951 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 41.170 0.000 sys_clk " " 41.170 0.000 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729951 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2169.891 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 2169.891 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729951 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4340.042 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4340.042 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729951 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1765010729951 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1765010730630 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1765010730630 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 4 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4783 " "Peak virtual memory: 4783 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1765010730715 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 6 16:45:30 2025 " "Processing ended: Sat Dec 6 16:45:30 2025" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1765010730715 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1765010730715 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1765010730715 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1765010730715 ""} diff --git a/puart2/uart_tx_restored/db/intan_m10.sta.rdb b/puart2/uart_tx_restored/db/intan_m10.sta.rdb new file mode 100644 index 0000000..0d75fd4 Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.sta.rdb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.sta_cmp.8_slow_1200mv_85c.tdb b/puart2/uart_tx_restored/db/intan_m10.sta_cmp.8_slow_1200mv_85c.tdb new file mode 100644 index 0000000..a747910 Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.sta_cmp.8_slow_1200mv_85c.tdb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.tis_db_list.ddb b/puart2/uart_tx_restored/db/intan_m10.tis_db_list.ddb new file mode 100644 index 0000000..99fefa7 Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.tis_db_list.ddb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.tiscmp.fast_1200mv_0c.ddb b/puart2/uart_tx_restored/db/intan_m10.tiscmp.fast_1200mv_0c.ddb new file mode 100644 index 0000000..8d6023e Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.tiscmp.fast_1200mv_0c.ddb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.tiscmp.fastest_slow_1200mv_0c.ddb b/puart2/uart_tx_restored/db/intan_m10.tiscmp.fastest_slow_1200mv_0c.ddb new file mode 100644 index 0000000..2a05624 Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.tiscmp.fastest_slow_1200mv_0c.ddb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.tiscmp.fastest_slow_1200mv_85c.ddb b/puart2/uart_tx_restored/db/intan_m10.tiscmp.fastest_slow_1200mv_85c.ddb new file mode 100644 index 0000000..d22e760 Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.tiscmp.fastest_slow_1200mv_85c.ddb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.tiscmp.slow_1200mv_0c.ddb b/puart2/uart_tx_restored/db/intan_m10.tiscmp.slow_1200mv_0c.ddb new file mode 100644 index 0000000..a2c5e2a Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.tiscmp.slow_1200mv_0c.ddb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.tiscmp.slow_1200mv_85c.ddb b/puart2/uart_tx_restored/db/intan_m10.tiscmp.slow_1200mv_85c.ddb new file mode 100644 index 0000000..20e0e52 Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.tiscmp.slow_1200mv_85c.ddb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.tmw_info b/puart2/uart_tx_restored/db/intan_m10.tmw_info new file mode 100644 index 0000000..72d79e8 --- /dev/null +++ b/puart2/uart_tx_restored/db/intan_m10.tmw_info @@ -0,0 +1,6 @@ +start_full_compilation:s:00:00:29 +start_analysis_synthesis:s:00:00:10-start_full_compilation +start_analysis_elaboration:s-start_full_compilation +start_fitter:s:00:00:06-start_full_compilation +start_assembler:s:00:00:07-start_full_compilation +start_timing_analyzer:s:00:00:03-start_full_compilation diff --git a/puart2/uart_tx_restored/db/intan_m10.vpr.ammdb b/puart2/uart_tx_restored/db/intan_m10.vpr.ammdb new file mode 100644 index 0000000..359e9f8 Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.vpr.ammdb differ diff --git a/puart2/uart_tx_restored/db/intan_m10.zippleback_io_sim_cache.ff_0c_fast.hsd b/puart2/uart_tx_restored/db/intan_m10.zippleback_io_sim_cache.ff_0c_fast.hsd new file mode 100644 index 0000000..783c904 Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.zippleback_io_sim_cache.ff_0c_fast.hsd differ diff --git a/puart2/uart_tx_restored/db/intan_m10.zippleback_io_sim_cache.ss_0c_slow.hsd b/puart2/uart_tx_restored/db/intan_m10.zippleback_io_sim_cache.ss_0c_slow.hsd new file mode 100644 index 0000000..8bdd3a3 Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.zippleback_io_sim_cache.ss_0c_slow.hsd differ diff --git a/puart2/uart_tx_restored/db/intan_m10.zippleback_io_sim_cache.ss_85c_slow.hsd b/puart2/uart_tx_restored/db/intan_m10.zippleback_io_sim_cache.ss_85c_slow.hsd new file mode 100644 index 0000000..ba57d93 Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.zippleback_io_sim_cache.ss_85c_slow.hsd differ diff --git a/puart2/uart_tx_restored/db/intan_m10.zippleback_io_sim_cache.tt_85c_nom.hsd b/puart2/uart_tx_restored/db/intan_m10.zippleback_io_sim_cache.tt_85c_nom.hsd new file mode 100644 index 0000000..e2fa020 Binary files /dev/null and b/puart2/uart_tx_restored/db/intan_m10.zippleback_io_sim_cache.tt_85c_nom.hsd differ diff --git a/puart2/uart_tx_restored/db/intan_m10_partition_pins.json b/puart2/uart_tx_restored/db/intan_m10_partition_pins.json new file mode 100644 index 0000000..b0dd515 --- /dev/null +++ b/puart2/uart_tx_restored/db/intan_m10_partition_pins.json @@ -0,0 +1,41 @@ +{ + "partitions" : [ + { + "name" : "Top", + "pins" : [ + { + "name" : "mosi", + "strict" : false + }, + { + "name" : "cs_n", + "strict" : false + }, + { + "name" : "sclk", + "strict" : false + }, + { + "name" : "tx", + "strict" : false + }, + { + "name" : "test_flag_led", + "strict" : false + }, + { + "name" : "convert_flag_led", + "strict" : false + }, + { + "name" : "test_flag", + "strict" : false + }, + { + "name" : "rst_n", + "strict" : false + } + ] + } + ] +} \ No newline at end of file diff --git a/puart2/uart_tx_restored/db/prev_cmp_intan_m10.qmsg b/puart2/uart_tx_restored/db/prev_cmp_intan_m10.qmsg new file mode 100644 index 0000000..df6d7ab --- /dev/null +++ b/puart2/uart_tx_restored/db/prev_cmp_intan_m10.qmsg @@ -0,0 +1,168 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1765010259643 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition " "Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1765010259644 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 6 16:37:39 2025 " "Processing started: Sat Dec 6 16:37:39 2025" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1765010259644 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765010259644 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off intan_m10 -c intan_m10 " "Command: quartus_map --read_settings_files=on --write_settings_files=off intan_m10 -c intan_m10" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765010259644 ""} +{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "4 " "Parallel compilation is enabled and will use up to 4 processors" { } { } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Analysis & Synthesis" 0 -1 1765010259999 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spi_master_2164.v 1 1 " "Found 1 design units, including 1 entities, in source file spi_master_2164.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi_master_2164 " "Found entity 1: spi_master_2164" { } { { "spi_master_2164.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/spi_master_2164.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1765010267722 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765010267722 ""} +{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "ddr_ctrl.v(151) " "Verilog HDL information at ddr_ctrl.v(151): always construct contains both blocking and non-blocking assignments" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 151 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1765010267723 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr_ctrl.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr_ctrl.v" { { "Info" "ISGN_ENTITY_NAME" "1 ddr_ctrl " "Found entity 1: ddr_ctrl" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1765010267724 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765010267724 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clk_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file clk_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_gen " "Found entity 1: clk_gen" { } { { "clk_gen.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/clk_gen.v" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1765010267726 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765010267726 ""} +{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "done DONE spi_master_esp32.v(6) " "Verilog HDL Declaration information at spi_master_esp32.v(6): object \"done\" differs only in case from object \"DONE\" in the same scope" { } { { "spi_master_esp32.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/spi_master_esp32.v" 6 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1765010267727 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spi_master_esp32.v 1 1 " "Found 1 design units, including 1 entities, in source file spi_master_esp32.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi_master_esp32 " "Found entity 1: spi_master_esp32" { } { { "spi_master_esp32.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/spi_master_esp32.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1765010267727 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765010267727 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "intan_m10.v 1 1 " "Found 1 design units, including 1 entities, in source file intan_m10.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart_tx " "Found entity 1: uart_tx" { } { { "intan_m10.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/intan_m10.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1765010267729 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765010267729 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "ddr_ctrl " "Elaborating entity \"ddr_ctrl\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1765010267763 ""} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "received_data ddr_ctrl.v(71) " "Verilog HDL or VHDL warning at ddr_ctrl.v(71): object \"received_data\" assigned a value but never read" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 71 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1765010267764 "|ddr_ctrl"} +{ "Warning" "WVRFX_L2_VERI_ASSUMED_INCOMPLETE_CASE" "ddr_ctrl.v(153) " "Verilog HDL warning at ddr_ctrl.v(153): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 153 0 0 } } } 0 10763 "Verilog HDL warning at %1!s!: case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness" 0 0 "Analysis & Synthesis" 0 -1 1765010267764 "|ddr_ctrl"} +{ "Warning" "WVRFX_L2_VERI_FULL_CASE_DIRECTIVE_EFFECTIVE" "ddr_ctrl.v(153) " "Verilog HDL Case Statement warning at ddr_ctrl.v(153): honored full_case synthesis attribute - differences between design synthesis and simulation may occur" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 153 0 0 } } } 0 10208 "Verilog HDL Case Statement warning at %1!s!: honored full_case synthesis attribute - differences between design synthesis and simulation may occur" 0 0 "Analysis & Synthesis" 0 -1 1765010267764 "|ddr_ctrl"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_gen clk_gen:clk_gen_inst " "Elaborating entity \"clk_gen\" for hierarchy \"clk_gen:clk_gen_inst\"" { } { { "ddr_ctrl.v" "clk_gen_inst" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 204 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765010267769 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll clk_gen:clk_gen_inst\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"clk_gen:clk_gen_inst\|altpll:altpll_component\"" { } { { "clk_gen.v" "altpll_component" { Text "E:/FPGA/20240726/uart_tx_restored/clk_gen.v" 95 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765010267806 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "clk_gen:clk_gen_inst\|altpll:altpll_component " "Elaborated megafunction instantiation \"clk_gen:clk_gen_inst\|altpll:altpll_component\"" { } { { "clk_gen.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/clk_gen.v" 95 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765010267808 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "clk_gen:clk_gen_inst\|altpll:altpll_component " "Instantiated megafunction \"clk_gen:clk_gen_inst\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 625 " "Parameter \"clk0_divide_by\" = \"625\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 6 " "Parameter \"clk0_multiply_by\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 625 " "Parameter \"clk1_divide_by\" = \"625\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 12 " "Parameter \"clk1_multiply_by\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 0 " "Parameter \"clk1_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 83333 " "Parameter \"inclk0_input_frequency\" = \"83333\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family MAX 10 " "Parameter \"intended_device_family\" = \"MAX 10\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=clk_gen " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=clk_gen\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_UNUSED " "Parameter \"port_locked\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Parameter \"port_clk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765010267808 ""} } { { "clk_gen.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/clk_gen.v" 95 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1765010267808 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/clk_gen_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/clk_gen_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_gen_altpll " "Found entity 1: clk_gen_altpll" { } { { "db/clk_gen_altpll.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/db/clk_gen_altpll.v" 30 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1765010267849 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765010267849 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_gen_altpll clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated " "Elaborating entity \"clk_gen_altpll\" for hierarchy \"clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "f:/quartus_prime_lite/quartus/libraries/megafunctions/altpll.tdf" 898 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765010267849 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi_master_2164 spi_master_2164:u_spi_master_2164 " "Elaborating entity \"spi_master_2164\" for hierarchy \"spi_master_2164:u_spi_master_2164\"" { } { { "ddr_ctrl.v" "u_spi_master_2164" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 221 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765010267852 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi_master_esp32 spi_master_esp32:tranfer " "Elaborating entity \"spi_master_esp32\" for hierarchy \"spi_master_esp32:tranfer\"" { } { { "ddr_ctrl.v" "tranfer" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 234 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765010267853 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 spi_master_esp32.v(49) " "Verilog HDL assignment warning at spi_master_esp32.v(49): truncated value with size 32 to match size of target (4)" { } { { "spi_master_esp32.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/spi_master_esp32.v" 49 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1765010267854 "|ddr_ctrl|spi_master_esp32:tranfer"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_tx uart_tx:u_uart_pc " "Elaborating entity \"uart_tx\" for hierarchy \"uart_tx:u_uart_pc\"" { } { { "ddr_ctrl.v" "u_uart_pc" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 243 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765010267855 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 intan_m10.v(33) " "Verilog HDL assignment warning at intan_m10.v(33): truncated value with size 32 to match size of target (16)" { } { { "intan_m10.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/intan_m10.v" 33 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1765010267855 "|ddr_ctrl|uart_tx:u_uart_pc"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 intan_m10.v(74) " "Verilog HDL assignment warning at intan_m10.v(74): truncated value with size 32 to match size of target (4)" { } { { "intan_m10.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/intan_m10.v" 74 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1765010267856 "|ddr_ctrl|uart_tx:u_uart_pc"} +{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "spi_master_2164.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/spi_master_2164.v" 11 -1 0 } } { "spi_master_esp32.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/spi_master_esp32.v" 10 -1 0 } } { "intan_m10.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/intan_m10.v" 44 -1 0 } } { "ddr_ctrl.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 146 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 -1 1765010268221 ""} +{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Analysis & Synthesis" 0 -1 1765010268221 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1765010268323 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "6 " "6 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1765010268733 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/FPGA/20240726/uart_tx_restored/output_files/intan_m10.map.smsg " "Generated suppressed messages file E:/FPGA/20240726/uart_tx_restored/output_files/intan_m10.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765010268774 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "1 0 1 0 0 " "Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1765010268869 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765010268869 ""} +{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "miso " "No output dependent on input pin \"miso\"" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 7 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1765010268906 "|ddr_ctrl|miso"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1765010268906 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "188 " "Implemented 188 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Implemented 4 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1765010268906 ""} { "Info" "ICUT_CUT_TM_OPINS" "9 " "Implemented 9 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1765010268906 ""} { "Info" "ICUT_CUT_TM_LCELLS" "174 " "Implemented 174 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1765010268906 ""} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Implemented 1 PLLs" { } { } 0 21065 "Implemented %1!d! PLLs" 0 0 "Design Software" 0 -1 1765010268906 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1765010268906 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 8 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4793 " "Peak virtual memory: 4793 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1765010268921 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 6 16:37:48 2025 " "Processing ended: Sat Dec 6 16:37:48 2025" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1765010268921 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1765010268921 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1765010268921 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1765010268921 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1765010270172 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition " "Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1765010270173 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 6 16:37:49 2025 " "Processing started: Sat Dec 6 16:37:49 2025" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1765010270173 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1765010270173 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10 " "Command: quartus_fit --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1765010270173 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1765010270298 ""} +{ "Info" "0" "" "Project = intan_m10" { } { } 0 0 "Project = intan_m10" 0 0 "Fitter" 0 0 1765010270299 ""} +{ "Info" "0" "" "Revision = intan_m10" { } { } 0 0 "Revision = intan_m10" 0 0 "Fitter" 0 0 1765010270299 ""} +{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "4 " "Parallel compilation is enabled and will use up to 4 processors" { } { } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Fitter" 0 -1 1765010270392 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "intan_m10 10M08SAM153C8G " "Selected device 10M08SAM153C8G for design \"intan_m10\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1765010270403 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1765010270430 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1765010270430 ""} +{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|pll1 MAX 10 PLL " "Implemented PLL \"clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|pll1\" as MAX 10 PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] 6 625 0 0 " "Implementing clock multiplication of 6, clock division of 625, and phase shift of 0 degrees (0 ps) for clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/clk_gen_altpll.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/db/clk_gen_altpll.v" 44 -1 0 } } { "" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 133 14177 15141 0 0 "" 0 "" "" } } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Design Software" 0 -1 1765010270482 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] 12 625 0 0 " "Implementing clock multiplication of 12, clock division of 625, and phase shift of 0 degrees (0 ps) for clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] port" { } { { "db/clk_gen_altpll.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/db/clk_gen_altpll.v" 44 -1 0 } } { "" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 134 14177 15141 0 0 "" 0 "" "" } } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Design Software" 0 -1 1765010270482 ""} } { { "db/clk_gen_altpll.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/db/clk_gen_altpll.v" 44 -1 0 } } { "" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 133 14177 15141 0 0 "" 0 "" "" } } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1765010270482 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1765010270528 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1765010270534 ""} +{ "Critical Warning" "WFCUDA_FCUDA_SPS_DEVICE_POWER_LIMITATION" "" "Review the Power Analyzer report file (.pow.rpt) to ensure your design is within the maximum power utilization limit of the single power-supply target device and to avoid functional failures." { } { } 1 16562 "Review the Power Analyzer report file (.pow.rpt) to ensure your design is within the maximum power utilization limit of the single power-supply target device and to avoid functional failures." 0 0 "Fitter" 0 -1 1765010270598 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M08SAM153C8GES " "Device 10M08SAM153C8GES is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1765010270608 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M04SAM153C8G " "Device 10M04SAM153C8G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1765010270608 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1765010270608 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "8 " "Fitter converted 8 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TMS~ G1 " "Pin ~ALTERA_TMS~ is reserved at location G1" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { ~ALTERA_TMS~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 415 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765010270610 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TCK~ J1 " "Pin ~ALTERA_TCK~ is reserved at location J1" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { ~ALTERA_TCK~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 417 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765010270610 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDI~ H5 " "Pin ~ALTERA_TDI~ is reserved at location H5" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDI~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 419 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765010270610 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDO~ H4 " "Pin ~ALTERA_TDO~ is reserved at location H4" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDO~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 421 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765010270610 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONFIG_SEL~ D8 " "Pin ~ALTERA_CONFIG_SEL~ is reserved at location D8" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONFIG_SEL~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 423 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765010270610 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCONFIG~ E8 " "Pin ~ALTERA_nCONFIG~ is reserved at location E8" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCONFIG~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 425 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765010270610 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nSTATUS~ D6 " "Pin ~ALTERA_nSTATUS~ is reserved at location D6" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { ~ALTERA_nSTATUS~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 427 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765010270610 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONF_DONE~ E6 " "Pin ~ALTERA_CONF_DONE~ is reserved at location E6" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONF_DONE~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 429 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765010270610 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1765010270610 ""} +{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" { } { } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1765010270610 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1765010270610 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1765010270610 ""} +{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1765010270610 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1765010270610 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "intan_m10.sdc " "Synopsys Design Constraints File file not found: 'intan_m10.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1765010271026 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "generated clocks " "No user constrained generated clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1765010271026 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1765010271027 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1765010271029 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1765010271029 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1765010271030 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C1 of PLL_1) " "Automatically promoted node clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C1 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1765010271045 ""} } { { "db/clk_gen_altpll.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/db/clk_gen_altpll.v" 78 -1 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 133 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1765010271045 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C3 of PLL_1) " "Automatically promoted node clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C3 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1765010271045 ""} } { { "db/clk_gen_altpll.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/db/clk_gen_altpll.v" 78 -1 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 133 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1765010271045 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "spi_master_2164:u_spi_master_2164\|cs_n " "Automatically promoted node spi_master_2164:u_spi_master_2164\|cs_n " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1765010271045 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "cs_n~output " "Destination node cs_n~output" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 9 0 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 396 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1765010271045 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1765010271045 ""} } { { "spi_master_2164.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/spi_master_2164.v" 11 -1 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 130 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1765010271045 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1765010271328 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1765010271329 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1765010271329 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1765010271330 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1765010271331 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1765010271332 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1765010271332 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1765010271332 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1765010271348 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1765010271349 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1765010271349 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_tx " "Node \"UART_tx\" is assigned to location or region, but does not exist in design" { } { { "f:/quartus_prime_lite/quartus/bin64/Assignment Editor.qase" "" { Assignment "f:/quartus_prime_lite/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_tx" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1765010271369 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1765010271369 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1765010271369 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1765010271372 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1765010271806 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1765010271865 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1765010271874 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1765010272321 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1765010272322 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1765010272682 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X21_Y0 X31_Y12 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X21_Y0 to location X31_Y12" { } { { "loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X21_Y0 to location X31_Y12"} { { 12 { 0 ""} 21 0 11 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1765010273108 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1765010273108 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1765010273411 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1765010273411 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1765010273414 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.24 " "Total time spent on timing analysis during the Fitter is 0.24 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1765010273552 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1765010273563 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1765010273749 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1765010273749 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1765010274033 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1765010274475 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1765010274600 ""} +{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "4 MAX 10 " "4 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing MAX 10 Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "miso 3.3-V LVCMOS R3 " "Pin miso uses I/O standard 3.3-V LVCMOS at R3" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { miso } } } { "f:/quartus_prime_lite/quartus/bin64/Assignment Editor.qase" "" { Assignment "f:/quartus_prime_lite/quartus/bin64/Assignment Editor.qase" 1 { { 0 "miso" } } } } { "ddr_ctrl.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 7 0 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 12 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1765010274604 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "test_flag 3.3-V LVCMOS J12 " "Pin test_flag uses I/O standard 3.3-V LVCMOS at J12" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { test_flag } } } { "f:/quartus_prime_lite/quartus/bin64/Assignment Editor.qase" "" { Assignment "f:/quartus_prime_lite/quartus/bin64/Assignment Editor.qase" 1 { { 0 "test_flag" } } } } { "ddr_ctrl.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 4 0 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 11 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1765010274604 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "rst_n 3.3-V LVCMOS J14 " "Pin rst_n uses I/O standard 3.3-V LVCMOS at J14" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { rst_n } } } { "f:/quartus_prime_lite/quartus/bin64/Assignment Editor.qase" "" { Assignment "f:/quartus_prime_lite/quartus/bin64/Assignment Editor.qase" 1 { { 0 "rst_n" } } } } { "ddr_ctrl.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 3 0 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 10 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1765010274604 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "sys_clk 3.3-V LVCMOS J5 " "Pin sys_clk uses I/O standard 3.3-V LVCMOS at J5" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { sys_clk } } } { "f:/quartus_prime_lite/quartus/bin64/Assignment Editor.qase" "" { Assignment "f:/quartus_prime_lite/quartus/bin64/Assignment Editor.qase" 1 { { 0 "sys_clk" } } } } { "ddr_ctrl.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 2 0 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 9 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1765010274604 ""} } { } 0 169177 "%1!d! pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1765010274604 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/FPGA/20240726/uart_tx_restored/output_files/intan_m10.fit.smsg " "Generated suppressed messages file E:/FPGA/20240726/uart_tx_restored/output_files/intan_m10.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1765010274651 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 8 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5536 " "Peak virtual memory: 5536 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1765010275001 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 6 16:37:55 2025 " "Processing ended: Sat Dec 6 16:37:55 2025" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1765010275001 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1765010275001 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1765010275001 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1765010275001 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1765010275988 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition " "Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1765010275988 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 6 16:37:55 2025 " "Processing started: Sat Dec 6 16:37:55 2025" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1765010275988 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1765010275988 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1765010275988 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1765010276607 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1765010276636 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4684 " "Peak virtual memory: 4684 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1765010276894 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 6 16:37:56 2025 " "Processing ended: Sat Dec 6 16:37:56 2025" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1765010276894 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1765010276894 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1765010276894 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1765010276894 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1765010277872 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Power Analyzer Quartus Prime " "Running Quartus Prime Power Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition " "Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1765010277872 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 6 16:37:57 2025 " "Processing started: Sat Dec 6 16:37:57 2025" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1765010277872 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Power Analyzer" 0 -1 1765010277872 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_pow --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10 " "Command: quartus_pow --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10" { } { } 0 0 "Command: %1!s!" 0 0 "Power Analyzer" 0 -1 1765010277872 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Power Analyzer" 0 -1 1765010278175 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Power Analyzer" 0 -1 1765010278175 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "intan_m10.sdc " "Synopsys Design Constraints File file not found: 'intan_m10.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Power Analyzer" 0 -1 1765010278406 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "sys_clk " "Node: sys_clk was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi_master_2164:u_spi_master_2164\|cnt\[0\] sys_clk " "Register spi_master_2164:u_spi_master_2164\|cnt\[0\] is being clocked by sys_clk" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1765010278406 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Power Analyzer" 0 -1 1765010278406 "|ddr_ctrl|sys_clk"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi_master_2164:u_spi_master_2164\|cs_n " "Node: spi_master_2164:u_spi_master_2164\|cs_n was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register state\[3\] spi_master_2164:u_spi_master_2164\|cs_n " "Register state\[3\] is being clocked by spi_master_2164:u_spi_master_2164\|cs_n" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1765010278407 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Power Analyzer" 0 -1 1765010278407 "|ddr_ctrl|spi_master_2164:u_spi_master_2164|cs_n"} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Power Analyzer" 0 -1 1765010278407 ""} +{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Node: clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 83.333 " "Node: clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 83.333" { } { } 0 332056 "%1!s!" 0 0 "Design Software" 0 -1 1765010278408 ""} { "Warning" "WSTA_GENERIC_WARNING" "Node: clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] was found missing 1 generated clock that corresponds to a base clock with a period of: 83.333 " "Node: clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] was found missing 1 generated clock that corresponds to a base clock with a period of: 83.333" { } { } 0 332056 "%1!s!" 0 0 "Design Software" 0 -1 1765010278408 ""} } { } 0 332056 "%1!s!" 0 0 "Power Analyzer" 0 -1 1765010278408 ""} +{ "Info" "IPVA_PVA_START_CALCULATION" "" "Starting Vectorless Power Activity Estimation" { } { } 0 223000 "Starting Vectorless Power Activity Estimation" 0 0 "Power Analyzer" 0 -1 1765010278412 ""} +{ "Warning" "WPUTIL_PUTIL_NO_CLK_DOMAINS_FOUND" "" "Relative toggle rates could not be calculated because no clock domain could be identified for some nodes" { } { } 0 222013 "Relative toggle rates could not be calculated because no clock domain could be identified for some nodes" 0 0 "Power Analyzer" 0 -1 1765010278412 ""} +{ "Info" "IPVA_PVA_END_CALCULATION" "" "Completed Vectorless Power Activity Estimation" { } { } 0 223001 "Completed Vectorless Power Activity Estimation" 0 0 "Power Analyzer" 0 -1 1765010278414 ""} +{ "Info" "IPATFAM_USING_ADVANCED_IO_POWER" "" "Using Advanced I/O Power to simulate I/O buffers with the specified board trace model" { } { } 0 218000 "Using Advanced I/O Power to simulate I/O buffers with the specified board trace model" 0 0 "Power Analyzer" 0 -1 1765010278547 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Power Analyzer" 0 -1 1765010278576 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Power Analyzer" 0 -1 1765010278894 ""} +{ "Info" "IPAN_AVG_TOGGLE_RATE_PER_DESIGN" "0.000 millions of transitions / sec " "Average toggle rate for this design is 0.000 millions of transitions / sec" { } { } 0 215049 "Average toggle rate for this design is %1!s!" 0 0 "Power Analyzer" 0 -1 1765010279091 ""} +{ "Info" "IPAN_PAN_TOTAL_POWER_ESTIMATION" "144.69 mW " "Total thermal power estimate for the design is 144.69 mW" { } { { "f:/quartus_prime_lite/quartus/bin64/Report_Window_01.qrpt" "" { Report "f:/quartus_prime_lite/quartus/bin64/Report_Window_01.qrpt" "Compiler" "" "" "" "" { } "PowerPlay Power Analyzer Summary" } } } 0 215031 "Total thermal power estimate for the design is %1!s!" 0 0 "Power Analyzer" 0 -1 1765010279150 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Power Analyzer 0 s 8 s Quartus Prime " "Quartus Prime Power Analyzer was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4815 " "Peak virtual memory: 4815 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1765010279312 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 6 16:37:59 2025 " "Processing ended: Sat Dec 6 16:37:59 2025" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1765010279312 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1765010279312 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1765010279312 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Power Analyzer" 0 -1 1765010279312 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Power Analyzer" 0 -1 1765010280587 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition " "Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1765010280587 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 6 16:38:00 2025 " "Processing started: Sat Dec 6 16:38:00 2025" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1765010280587 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1765010280587 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta intan_m10 -c intan_m10 " "Command: quartus_sta intan_m10 -c intan_m10" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1765010280587 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1765010280700 ""} +{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "4 " "Parallel compilation is enabled and will use up to 4 processors" { } { } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Timing Analyzer" 0 -1 1765010280841 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1765010280867 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1765010280867 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "intan_m10.sdc " "Synopsys Design Constraints File file not found: 'intan_m10.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1765010280974 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "generated clocks \"derive_pll_clocks -create_base_clocks\" " "No user constrained generated clocks found in the design. Calling \"derive_pll_clocks -create_base_clocks\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1765010280975 ""} +{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_clock -period 83.333 -waveform \{0.000 41.666\} -name sys_clk sys_clk " "create_clock -period 83.333 -waveform \{0.000 41.666\} -name sys_clk sys_clk" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1765010280976 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 625 -multiply_by 6 -duty_cycle 50.00 -name \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 625 -multiply_by 6 -duty_cycle 50.00 -name \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1765010280976 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 625 -multiply_by 12 -duty_cycle 50.00 -name \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 625 -multiply_by 12 -duty_cycle 50.00 -name \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1765010280976 ""} } { } 0 332110 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1765010280976 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1765010280976 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name spi_master_2164:u_spi_master_2164\|cs_n spi_master_2164:u_spi_master_2164\|cs_n " "create_clock -period 1.000 -name spi_master_2164:u_spi_master_2164\|cs_n spi_master_2164:u_spi_master_2164\|cs_n" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1765010280976 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1765010280976 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1765010280978 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1765010280979 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1765010280980 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1765010280987 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1765010280991 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1765010280992 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -6.955 " "Worst-case setup slack is -6.955" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010280994 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010280994 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.955 -6.955 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -6.955 -6.955 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010280994 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.678 -7.152 spi_master_2164:u_spi_master_2164\|cs_n " " -0.678 -7.152 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010280994 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4336.388 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4336.388 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010280994 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1765010280994 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.360 " "Worst-case hold slack is 0.360" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010280998 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010280998 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.360 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.360 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010280998 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.362 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.362 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010280998 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.363 0.000 spi_master_2164:u_spi_master_2164\|cs_n " " 0.363 0.000 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010280998 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1765010280998 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1765010281000 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1765010281003 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.487 " "Worst-case minimum pulse width slack is -1.487" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010281004 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010281004 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.487 -46.097 spi_master_2164:u_spi_master_2164\|cs_n " " -1.487 -46.097 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010281004 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 41.541 0.000 sys_clk " " 41.541 0.000 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010281004 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2169.841 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 2169.841 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010281004 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4339.991 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4339.991 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010281004 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1765010281004 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1765010281014 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1765010281033 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1765010281359 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1765010281409 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1765010281413 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -6.381 " "Worst-case setup slack is -6.381" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010281415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010281415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.381 -6.381 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -6.381 -6.381 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010281415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.584 -5.152 spi_master_2164:u_spi_master_2164\|cs_n " " -0.584 -5.152 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010281415 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4336.557 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4336.557 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010281415 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1765010281415 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.322 " "Worst-case hold slack is 0.322" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010281418 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010281418 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.322 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.322 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010281418 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.324 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.324 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010281418 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.324 0.000 spi_master_2164:u_spi_master_2164\|cs_n " " 0.324 0.000 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010281418 ""} } { } 0 332146 "Worst-case %1!s! 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Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1765010281553 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1765010281554 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.409 " "Worst-case setup slack is -2.409" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010281556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010281556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.409 -2.409 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.409 -2.409 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convert data + + // 2132 + input miso, + output mosi, + output cs_n, + output sclk, + //esp32 + output MOSI_ESP32, + output cs_ESP32, + output sclk_ESP32, + //uart + output wire tx, // 串行输出信号 + + + + output test_flag_led, + output convert_flag_led + + // for simulation +// output reg [25:0] state, +// output reg [25:0] next, + + //output [15:0] dout +); + + reg start1, start2,start_uart; + wire done1,done2,done_uart; + + localparam [4:0] s0 = 0, + s1 = 1, + s2 = 2, + s3 = 3, + s4 = 4, + s5 = 5, + s6 = 6, + s7 = 7, + s8 = 8, + s9 = 9, + s10 = 10, + s11 = 11, + s12 = 12, + s13 = 13, + s14 = 14, + s15 = 15, + s16 = 16, + s17 = 17, + s18 = 18, + s19 = 19, + s20 = 20, + s21 = 21, + s22 = 22, + s23 = 23, + s24 = 24, + s25 = 25, + s26 = 26, + s27 = 27, + s28 = 28, + s29 = 29, + s30 = 30; + + + reg [30:0] state, next; + + reg [15:0] din_r; + wire [15:0] din; + + reg [15:0] received_data; // 存储从从机1接收到的数据 + reg [15:0] sent_data; // 要发送到从机2的数据 + + + + assign din = din_r; + + + assign test_flag_led = test_flag; + assign convert_flag_led = ~test_flag; + + // 定义状态编码 +parameter IDLE = 2'b00, + SEND1 = 2'b01, + SEND2 = 2'b10, + SEND3 = 2'b11; + +// 定义状态变量 +reg [1:0] state_top; + + //状态机，用于控制两个SPI模块的启动 + always @(posedge clk_230400 or negedge rst_n) begin + if (!rst_n) begin + start1 <= 0; + start2 <= 0; + state_top <= IDLE; + end + else begin + case (state_top) + IDLE: begin + start1 <= 1; // 启动SPI主机1 + start2 <= 0; + state_top <= SEND1; + end + + SEND1: begin + // if (done1) begin // SPI主机1完成接收 + start1 <= 0; + received_data <= {2'b00,6'd00,8'h01}; // dout1存储接收到的数据 + sent_data <={2'b00,6'd00,8'h01} ; //dout1 将接收到的数据准备好发送 + start_uart <= 1; // 启动SPI主机2，发送数据给从机2 + state_top <= SEND3; + //end + end + + SEND3: begin + if (done_uart) begin // uart完成发送 + start_uart <= 0; + //start2 <= 1; + state_top <= SEND1; // SEND2; + end + end + + SEND2: begin + if (done2) begin // SPI主机2完成发送 + start2 <= 0; + state_top <= IDLE; // 回到初始状态，等待下一轮传输 + end + end + + default: state_top <= IDLE; + endcase + end + end + + + + + //时序逻辑加组合逻辑完成din命令的有序发送 + + always @ (posedge cs_n or negedge rst_n) begin + if(!rst_n) begin + state <= 31'd0; + state[s0] <= 1'b1; + end + else state <= next; + end + + + always @ (*) begin + next = 31'd0; + din_r = {2'b11,6'd63,8'h00}; + case(1'b1) // synthesis parallel_case full_case + state[s0]: begin din_r<={2'b11,6'd63,8'h00}; next[s1] = 1'b1; end + state[s1]: begin din_r<={2'b11,6'd63,8'h00}; next[s2] = 1'b1; end + state[s2]: begin din_r<={2'b10,6'd0,8'hDE}; next[s3] = 1'b1; end + state[s3]: begin din_r<={2'b10,6'd1,8'h20}; next[s4] = 1'b1; end //8'h20 + state[s4]: begin din_r<={2'b10,6'd2,8'h28}; next[s5] = 1'b1; end //8'h28 + state[s5]: begin din_r<={2'b10,6'd3,8'h00}; next[s6] = 1'b1; end + state[s6]: begin din_r<={2'b10,6'd4,8'hD6}; next[s7] = 1'b1; end + state[s7]: begin din_r<={2'b10,6'd5,8'h00}; next[s8] = 1'b1; end + state[s8]: begin din_r<={2'b10,6'd6,8'h80}; next[s9] = 1'b1; end + state[s9]: begin din_r<={2'b10,6'd7,8'h00}; next[s10] = 1'b1; end + state[s10]: begin din_r<={2'b10,6'd8,8'h16}; next[s11] = 1'b1; end + state[s11]: begin din_r<={2'b10,6'd9,8'h80}; next[s12] = 1'b1; end + state[s12]: begin din_r<={2'b10,6'd10,8'h17}; next[s13] = 1'b1; end + state[s13]: begin din_r<={2'b10,6'd11,8'h80}; next[s14] = 1'b1; end + state[s14]: begin din_r<={2'b10,6'd12,8'h2C}; next[s15] = 1'b1; end + state[s15]: begin din_r<={2'b10,6'd13,8'h86}; next[s16] = 1'b1; end + state[s16]: begin din_r<={2'b10,6'd14,8'hFF}; next[s17] = 1'b1; end + state[s17]: begin din_r<={2'b10,6'd15,8'hFF}; next[s18] = 1'b1; end + state[s18]: begin din_r<={2'b10,6'd16,8'hFF}; next[s19] = 1'b1; end + state[s19]: begin din_r<={2'b10,6'd17,8'hFF}; next[s20] = 1'b1; end + state[s20]: begin din_r<={2'b01,6'd21,8'h00}; next[s21] = 1'b1; end // CALIBRATE, {01,010101,8h00} + state[s21]: begin din_r<={2'b11,6'd63,8'h00}; next[s22] = 1'b1; end // dummy 1 + state[s22]: begin din_r<={2'b11,6'd63,8'h00}; next[s23] = 1'b1; end // dummy 2 + state[s23]: begin din_r<={2'b11,6'd63,8'h00}; next[s24] = 1'b1; end // dummy 3 + state[s24]: begin din_r<={2'b11,6'd63,8'h00}; next[s25] = 1'b1; end // dummy 4 + state[s25]: begin din_r<={2'b11,6'd63,8'h00}; next[s26] = 1'b1; end // dummy 5 + state[s26]: begin din_r<={2'b11,6'd63,8'h00}; next[s27] = 1'b1; end // dummy 6 + state[s27]: begin din_r<={2'b11,6'd63,8'h00}; next[s28] = 1'b1; end // dummy 7 + state[s28]: begin din_r<={2'b11,6'd63,8'h00}; next[s29] = 1'b1; end // dummy 8 + state[s29]: begin din_r<={2'b11,6'd62,8'h00}; next[s30] = 1'b1; end // dummy 9 + state[s30]: begin + if (test_flag) begin din_r<={2'b11,6'd63,8'h00}; end // read(63) + else begin din_r<={2'b11,6'd62,8'h00}; end // convert(3) din_r<={2'b00,6'd3,8'h00}; + next[s30] = 1'b1; + end + endcase + end + + + + + + + wire clk_115200; + wire clk_230400; + + clk_gen clk_gen_inst ( + .inclk0 ( sys_clk ), + .c0 ( clk_115200 ), + .c1 ( clk_230400 ) + ); + + + wire [15:0] dout1; + + spi_master_2164 u_spi_master_2164( + .sys_clk(clk_230400), + .rst_n(rst_n), + .din(din), + .start(start1), + .dout(dout1), + .done(done1), + .sclk(sclk), + .cs_n(cs_n), + .mosi(mosi), + .miso(miso), + .cnt() + ); + + spi_master_esp32 tranfer( + + .clk(clk_230400), + .rst_n(rst_n), + .start(start2), + .din(sent_data), + .done(done2), + .sclk(sclk_ESP32), + .mosi(MOSI_ESP32), + .cs(cs_ESP32) + + ); + + uart_tx u_uart_pc( + .clk(clk_115200), // 时钟信号 + .rst(~rst_n), // 复位信号 + .tx_start(start_uart), // 开始发送信号 + .tx_data(sent_data), // 顶层输入的16位待发送数据 + .tx(tx), // 串行输出信号 + .tx_done(done_uart) // 发送完成信号 + ); + + + +endmodule diff --git a/puart2/uart_tx_restored/ddr_ctrl.v.bak b/puart2/uart_tx_restored/ddr_ctrl.v.bak new file mode 100644 index 0000000..26629c8 --- /dev/null +++ b/puart2/uart_tx_restored/ddr_ctrl.v.bak @@ -0,0 +1,247 @@ +module ddr_ctrl( + input sys_clk, // 12M on-board oscillator + input rst_n, + input test_flag, // 1: read register, 0: start convert data + + // 2132 + input miso, + output mosi, + output cs_n, + output sclk, + //esp32 + output MOSI_ESP32, + output cs_ESP32, + output sclk_ESP32, + //uart + output wire tx, // 串行输出信号 + + + + output test_flag_led, + output convert_flag_led + + // for simulation +// output reg [25:0] state, +// output reg [25:0] next, + + //output [15:0] dout +); + + reg start1, start2,start_uart; + wire done1,done2,done_uart; + + localparam [4:0] s0 = 0, + s1 = 1, + s2 = 2, + s3 = 3, + s4 = 4, + s5 = 5, + s6 = 6, + s7 = 7, + s8 = 8, + s9 = 9, + s10 = 10, + s11 = 11, + s12 = 12, + s13 = 13, + s14 = 14, + s15 = 15, + s16 = 16, + s17 = 17, + s18 = 18, + s19 = 19, + s20 = 20, + s21 = 21, + s22 = 22, + s23 = 23, + s24 = 24, + s25 = 25, + s26 = 26, + s27 = 27, + s28 = 28, + s29 = 29, + s30 = 30; + + + reg [30:0] state, next; + + reg [15:0] din_r; + wire [15:0] din; + + reg [15:0] received_data; // 存储从从机1接收到的数据 + reg [15:0] sent_data; // 要发送到从机2的数据 + + + + assign din = din_r; + + + assign test_flag_led = test_flag; + assign convert_flag_led = ~test_flag; + + // 定义状态编码 +parameter IDLE = 2'b00, + SEND1 = 2'b01, + SEND2 = 2'b10, + SEND_uart =2'b11; + +// 定义状态变量 +reg [1:0] state_top; + + //状态机，用于控制两个SPI模块的启动 + always @(posedge clk_230400 or negedge rst_n) begin + if (!rst_n) begin + start1 <= 0; + start2 <= 0; + state_top <= IDLE; + end + else begin + case (state_top) + IDLE: begin + start1 <= 1; // 启动SPI主机1 + start2 <= 0; + state_top <= SEND1; + end + + SEND1: begin + if (done1) begin // SPI主机1完成接收 + start1 <= 0; + received_data <= dout1; // 存储接收到的数据 + sent_data <= dout1; // 将接收到的数据准备好发送 + start_uart <= 1; // 启动SPI主机2，发送数据给从机2 + state_top <= SEND_uart; + end + end + + SEND_uart: begin + if (done_uart) begin // uart完成发送 + start_uart <= 0; + start2 <= 1; + state_top <= SEND2; + end + end + + SEND2: begin + if (done2) begin // SPI主机2完成发送 + start2 <= 0; + state_top <= IDLE; // 回到初始状态，等待下一轮传输 + end + end + + default: state_top <= IDLE; + endcase + end + end + + + + + //时序逻辑加组合逻辑完成din命令的有序发送 + + always @ (posedge cs_n or negedge rst_n) begin + if(!rst_n) begin + state <= 31'd0; + state[s0] <= 1'b1; + end + else state <= next; + end + + + always @ (*) begin + next = 31'd0; + din_r = {2'b11,6'd63,8'h00}; + case(1'b1) // synthesis parallel_case full_case + state[s0]: begin din_r<={2'b11,6'd63,8'h00}; next[s1] = 1'b1; end + state[s1]: begin din_r<={2'b11,6'd63,8'h00}; next[s2] = 1'b1; end + state[s2]: begin din_r<={2'b10,6'd0,8'hDE}; next[s3] = 1'b1; end + state[s3]: begin din_r<={2'b10,6'd1,8'h20}; next[s4] = 1'b1; end //8'h20 + state[s4]: begin din_r<={2'b10,6'd2,8'h28}; next[s5] = 1'b1; end //8'h28 + state[s5]: begin din_r<={2'b10,6'd3,8'h00}; next[s6] = 1'b1; end + state[s6]: begin din_r<={2'b10,6'd4,8'hD6}; next[s7] = 1'b1; end + state[s7]: begin din_r<={2'b10,6'd5,8'h00}; next[s8] = 1'b1; end + state[s8]: begin din_r<={2'b10,6'd6,8'h80}; next[s9] = 1'b1; end + state[s9]: begin din_r<={2'b10,6'd7,8'h00}; next[s10] = 1'b1; end + state[s10]: begin din_r<={2'b10,6'd8,8'h16}; next[s11] = 1'b1; end + state[s11]: begin din_r<={2'b10,6'd9,8'h80}; next[s12] = 1'b1; end + state[s12]: begin din_r<={2'b10,6'd10,8'h17}; next[s13] = 1'b1; end + state[s13]: begin din_r<={2'b10,6'd11,8'h80}; next[s14] = 1'b1; end + state[s14]: begin din_r<={2'b10,6'd12,8'h2C}; next[s15] = 1'b1; end + state[s15]: begin din_r<={2'b10,6'd13,8'h86}; next[s16] = 1'b1; end + state[s16]: begin din_r<={2'b10,6'd14,8'hFF}; next[s17] = 1'b1; end + state[s17]: begin din_r<={2'b10,6'd15,8'hFF}; next[s18] = 1'b1; end + state[s18]: begin din_r<={2'b10,6'd16,8'hFF}; next[s19] = 1'b1; end + state[s19]: begin din_r<={2'b10,6'd17,8'hFF}; next[s20] = 1'b1; end + state[s20]: begin din_r<={2'b01,6'd21,8'h00}; next[s21] = 1'b1; end // CALIBRATE, {01,010101,8h00} + state[s21]: begin din_r<={2'b11,6'd63,8'h00}; next[s22] = 1'b1; end // dummy 1 + state[s22]: begin din_r<={2'b11,6'd63,8'h00}; next[s23] = 1'b1; end // dummy 2 + state[s23]: begin din_r<={2'b11,6'd63,8'h00}; next[s24] = 1'b1; end // dummy 3 + state[s24]: begin din_r<={2'b11,6'd63,8'h00}; next[s25] = 1'b1; end // dummy 4 + state[s25]: begin din_r<={2'b11,6'd63,8'h00}; next[s26] = 1'b1; end // dummy 5 + state[s26]: begin din_r<={2'b11,6'd63,8'h00}; next[s27] = 1'b1; end // dummy 6 + state[s27]: begin din_r<={2'b11,6'd63,8'h00}; next[s28] = 1'b1; end // dummy 7 + state[s28]: begin din_r<={2'b11,6'd63,8'h00}; next[s29] = 1'b1; end // dummy 8 + state[s29]: begin din_r<={2'b11,6'd62,8'h00}; next[s30] = 1'b1; end // dummy 9 + state[s30]: begin + if (test_flag) begin din_r<={2'b11,6'd63,8'h00}; end // read(63) + else begin din_r<={2'b11,6'd62,8'h00}; end // convert(3) din_r<={2'b00,6'd3,8'h00}; + next[s30] = 1'b1; + end + endcase + end + + + + + + + wire clk_115200; + wire clk_230400; + + clk_gen clk_gen_inst ( + .inclk0 ( sys_clk ), + .c0 ( clk_115200 ), + .c1 ( clk_230400 ) + ); + + + wire [15:0] dout1; + + spi_master_2164 u_spi_master_2164( + .sys_clk(clk_230400), + .rst_n(rst_n), + .din(din), + .start(start1), + .dout(dout1), + .done(done1), + .sclk(sclk), + .cs_n(cs_n), + .mosi(mosi), + .miso(miso), + .cnt() + ); + + spi_master_esp32 tranfer( + + .clk(clk_230400), + .rst_n(rst_n), + .start(start2), + .din(sent_data), + .done(done2), + .sclk(sclk_ESP32), + .mosi(MOSI_ESP32), + .cs(cs_ESP32) + + ); + + uart_tx u_uart_pc( + .clk(sys_clk), // 时钟信号 + .rst(rst_n), // 复位信号 + .tx_start(start_uart), // 开始发送信号 + .tx_data(sent_data), // 顶层输入的16位待发送数据 + .tx(tx), // 串行输出信号 + .tx_done(done_uart) // 发送完成信号 + ); + + + +endmodule diff --git a/puart2/uart_tx_restored/ddr_ctrl_tb.v b/puart2/uart_tx_restored/ddr_ctrl_tb.v new file mode 100644 index 0000000..e91277c --- /dev/null +++ b/puart2/uart_tx_restored/ddr_ctrl_tb.v @@ -0,0 +1,66 @@ +module ddr_ctrl_tb(); + +reg sys_clk; +reg rst_n; +reg miso; + +wire mosi; +wire cs_n; +wire sclk; + +wire [24:0] state; +wire [24:0] next; +wire [31:0] dout; + + + +ddr_ctrl uut( + .sys_clk(sys_clk), + .rst_n(rst_n), + .miso(miso), + .mosi(mosi), + .cs_n(cs_n), + .sclk(sclk), + .state(state), + .next(next), + .dout(dout) +); + + + +initial +begin + rst_n = 0; + miso = 0; + #50 rst_n = 1; + #12000 $finish; +end + + + +initial begin + forever begin + #5 sys_clk = 0; + #5 sys_clk = 1; + end +end + + + +initial begin + forever begin + #50 miso = 0; + #50 miso = 1; + end +end + + +initial begin + $fsdbDumpfile("ddr_ctrl.fsdb"); + $fsdbDumpvars(); +end + + + + +endmodule diff --git a/puart2/uart_tx_restored/greybox_tmp/cbx_args.txt b/puart2/uart_tx_restored/greybox_tmp/cbx_args.txt new file mode 100644 index 0000000..ba166fc --- /dev/null +++ b/puart2/uart_tx_restored/greybox_tmp/cbx_args.txt @@ -0,0 +1,63 @@ +BANDWIDTH_TYPE=AUTO +CLK0_DIVIDE_BY=625 +CLK0_DUTY_CYCLE=50 +CLK0_MULTIPLY_BY=6 +CLK0_PHASE_SHIFT=0 +CLK1_DIVIDE_BY=625 +CLK1_DUTY_CYCLE=50 +CLK1_MULTIPLY_BY=12 +CLK1_PHASE_SHIFT=0 +COMPENSATE_CLOCK=CLK0 +INCLK0_INPUT_FREQUENCY=83333 +INTENDED_DEVICE_FAMILY="MAX 10" +LPM_TYPE=altpll +OPERATION_MODE=NORMAL +PLL_TYPE=AUTO +PORT_ACTIVECLOCK=PORT_UNUSED +PORT_ARESET=PORT_UNUSED +PORT_CLKBAD0=PORT_UNUSED +PORT_CLKBAD1=PORT_UNUSED +PORT_CLKLOSS=PORT_UNUSED +PORT_CLKSWITCH=PORT_UNUSED +PORT_CONFIGUPDATE=PORT_UNUSED +PORT_FBIN=PORT_UNUSED +PORT_INCLK0=PORT_USED +PORT_INCLK1=PORT_UNUSED +PORT_LOCKED=PORT_UNUSED +PORT_PFDENA=PORT_UNUSED +PORT_PHASECOUNTERSELECT=PORT_UNUSED +PORT_PHASEDONE=PORT_UNUSED +PORT_PHASESTEP=PORT_UNUSED +PORT_PHASEUPDOWN=PORT_UNUSED +PORT_PLLENA=PORT_UNUSED +PORT_SCANACLR=PORT_UNUSED +PORT_SCANCLK=PORT_UNUSED +PORT_SCANCLKENA=PORT_UNUSED +PORT_SCANDATA=PORT_UNUSED +PORT_SCANDATAOUT=PORT_UNUSED +PORT_SCANDONE=PORT_UNUSED +PORT_SCANREAD=PORT_UNUSED +PORT_SCANWRITE=PORT_UNUSED +PORT_clk0=PORT_USED +PORT_clk1=PORT_USED +PORT_clk2=PORT_UNUSED +PORT_clk3=PORT_UNUSED +PORT_clk4=PORT_UNUSED +PORT_clk5=PORT_UNUSED +PORT_clkena0=PORT_UNUSED +PORT_clkena1=PORT_UNUSED +PORT_clkena2=PORT_UNUSED +PORT_clkena3=PORT_UNUSED +PORT_clkena4=PORT_UNUSED +PORT_clkena5=PORT_UNUSED +PORT_extclk0=PORT_UNUSED +PORT_extclk1=PORT_UNUSED +PORT_extclk2=PORT_UNUSED +PORT_extclk3=PORT_UNUSED +WIDTH_CLOCK=5 +DEVICE_FAMILY="MAX 10" +CBX_AUTO_BLACKBOX=ALL +inclk +inclk +clk +clk diff --git a/puart2/uart_tx_restored/incremental_db/README b/puart2/uart_tx_restored/incremental_db/README new file mode 100644 index 0000000..9f62dcd --- /dev/null +++ b/puart2/uart_tx_restored/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.db_info b/puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.db_info new file mode 100644 index 0000000..a057859 --- /dev/null +++ b/puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition +Version_Index = 570679552 +Creation_Time = Sat Dec 6 15:50:23 2025 diff --git a/puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.ammdb b/puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.ammdb new file mode 100644 index 0000000..7845ae8 Binary files /dev/null and b/puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.ammdb differ diff --git a/puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.cdb b/puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.cdb new file mode 100644 index 0000000..3de5884 Binary files /dev/null and b/puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.cdb differ diff --git a/puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.dfp b/puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.dfp new file mode 100644 index 0000000..b1c67d6 Binary files /dev/null and b/puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.dfp differ diff --git a/puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.hdb b/puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.hdb new file mode 100644 index 0000000..06e3316 Binary files /dev/null and b/puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.hdb differ diff --git a/puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.logdb b/puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.logdb @@ -0,0 +1 @@ +v1 diff --git a/puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.rcfdb b/puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.rcfdb new file mode 100644 index 0000000..a77fbbc Binary files /dev/null and b/puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.rcfdb differ diff --git a/puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.map.cdb b/puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.map.cdb new file mode 100644 index 0000000..ccafd37 Binary files /dev/null and b/puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.map.cdb differ diff --git a/puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.map.dpi b/puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.map.dpi new file mode 100644 index 0000000..58fbe54 Binary files /dev/null and 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b/puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.map.hbdb.hdb new file mode 100644 index 0000000..9dcbd6e Binary files /dev/null and b/puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.map.hbdb.hdb differ diff --git a/puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.map.hbdb.sig b/puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.map.hbdb.sig new file mode 100644 index 0000000..fb59e3a --- /dev/null +++ b/puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.map.hbdb.sig @@ -0,0 +1 @@ +65b372b164d8b90535660a0689c25bd1 \ No newline at end of file diff --git a/puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.map.hdb b/puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.map.hdb new file mode 100644 index 0000000..1a5cbea Binary files /dev/null and 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b/puart2/uart_tx_restored/intan_m10.ipregen.rpt @@ -0,0 +1,69 @@ +IP Upgrade report for intan_m10 +Sat Dec 6 15:39:23 2025 +Quartus Prime Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. IP Upgrade Summary + 3. Successfully Upgraded IP Components + 4. IP Upgrade Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2024 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++-------------------------------------------------------------------------------+ +; IP Upgrade Summary ; ++------------------------------+------------------------------------------------+ +; IP Components Upgrade Status ; Passed - Sat Dec 6 15:39:23 2025 ; +; Quartus Prime Version ; 23.1std.1 Build 993 05/14/2024 SC Lite Edition ; +; Revision Name ; intan_m10 ; +; Top-level Entity Name ; ddr_ctrl ; +; Family ; MAX 10 ; ++------------------------------+------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------+ +; Successfully Upgraded IP Components ; ++-------------+----------------+---------+----------------------+----------------------+-----------------+---------+ +; Entity Name ; Component Name ; Version ; Original Source File ; Generation File Path ; New Source File ; Message ; ++-------------+----------------+---------+----------------------+----------------------+-----------------+---------+ +; clk_gen ; ALTPLL ; 17.1 ; clk_gen.qip ; clk_gen.v ; clk_gen.qip ; ; ++-------------+----------------+---------+----------------------+----------------------+-----------------+---------+ + + ++---------------------+ +; IP Upgrade Messages ; ++---------------------+ +Info (11902): Backing up file "clk_gen.v" to "clk_gen.BAK.v" +Info (11837): Started upgrading IP component ALTPLL with file "clk_gen.v" +Info (11131): Completed upgrading IP component ALTPLL with file "clk_gen.v" +Info (23030): Evaluation of Tcl script f:/quartus_prime_lite/quartus/common/tcl/internal/ip_regen/ip_regen.tcl was successful +Info: Quartus Prime Shell was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 4867 megabytes + Info: Processing ended: Sat Dec 6 15:39:23 2025 + Info: Elapsed time: 00:00:10 + Info: Total CPU time (on all processors): 00:00:22 + + diff --git a/puart2/uart_tx_restored/intan_m10.qpf b/puart2/uart_tx_restored/intan_m10.qpf new file mode 100644 index 0000000..908ab5d --- /dev/null +++ b/puart2/uart_tx_restored/intan_m10.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition +# Date created = 20:28:17 April 12, 2024 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.1" +DATE = "20:28:17 April 12, 2024" + +# Revisions + +PROJECT_REVISION = "intan_m10" diff --git a/puart2/uart_tx_restored/intan_m10.qsf b/puart2/uart_tx_restored/intan_m10.qsf new file mode 100644 index 0000000..20a4173 --- /dev/null +++ b/puart2/uart_tx_restored/intan_m10.qsf @@ -0,0 +1,86 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition +# Date created = 20:28:17 April 12, 2024 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# intan_m10_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M08SAM153C8G +set_global_assignment -name TOP_LEVEL_ENTITY ddr_ctrl +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:28:17 APRIL 12, 2024" +set_global_assignment -name LAST_QUARTUS_VERSION "23.1std.1 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %" +set_location_assignment PIN_J5 -to sys_clk +set_location_assignment PIN_P6 -to cs_n +set_location_assignment PIN_R3 -to miso +set_location_assignment PIN_M5 -to mosi +set_location_assignment PIN_J14 -to rst_n +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cs_n +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to miso +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to mosi +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to rst_n +set_location_assignment PIN_P3 -to sclk +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sclk +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sys_clk +set_location_assignment PIN_J12 -to test_flag +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to test_flag +set_location_assignment PIN_N15 -to test_flag_led +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to test_flag_led +set_location_assignment PIN_M12 -to convert_flag_led +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to convert_flag_led +set_global_assignment -name NUM_PARALLEL_PROCESSORS 4 +set_location_assignment PIN_A5 -to UART_tx +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_B14 -to sclk_ESP32 +set_location_assignment PIN_B13 -to cs_ESP32 +set_location_assignment PIN_A14 -to MOSI_ESP32 +set_global_assignment -name VERILOG_FILE spi_master_2164.v +set_global_assignment -name VERILOG_FILE ddr_ctrl.v +set_global_assignment -name QIP_FILE clk_gen.qip +set_global_assignment -name VERILOG_FILE spi_master_esp32.v +set_global_assignment -name VERILOG_FILE intan_m10.v +set_location_assignment PIN_P15 -to tx +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to tx +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/puart2/uart_tx_restored/intan_m10.qws b/puart2/uart_tx_restored/intan_m10.qws new file mode 100644 index 0000000..436f088 Binary files /dev/null and b/puart2/uart_tx_restored/intan_m10.qws differ diff --git a/puart2/uart_tx_restored/intan_m10.restore.rpt b/puart2/uart_tx_restored/intan_m10.restore.rpt new file mode 100644 index 0000000..6c916aa --- /dev/null +++ b/puart2/uart_tx_restored/intan_m10.restore.rpt @@ -0,0 +1,114 @@ +Restore Archived Project report for intan_m10 +Sat Dec 6 15:42:13 2025 +Quartus Prime Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Restore Archived Project Summary + 3. Restore Archived Project Messages + 4. Files Restored + 5. Files Not Restored + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2024 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++-------------------------------------------------------------------------+ +; Restore Archived Project Summary ; ++---------------------------------+---------------------------------------+ +; Restore Archived Project Status ; Successful - Sat Dec 6 15:42:13 2025 ; +; Revision Name ; intan_m10 ; +; Top-level Entity Name ; ddr_ctrl ; +; Family ; MAX 10 ; ++---------------------------------+---------------------------------------+ + + ++-----------------------------------+ +; Restore Archived Project Messages ; ++-----------------------------------+ +Info: Successfully restored 'E:/FPGA/20240726/uart_tx.qar' into the 'E:/FPGA/20240726/uart_tx_restored/' directory +Info: Generated report 'intan_m10.restore.rpt' +Info (23030): Evaluation of Tcl script f:/quartus_prime_lite/quartus/common/tcl/apps/qpm/qar.tcl was successful +Info: Quartus Prime Shell was successful. 0 errors, 41 warnings + Info: Peak virtual memory: 4822 megabytes + Info: Processing ended: Sat Dec 6 15:42:13 2025 + Info: Elapsed time: 00:00:00 + Info: Total CPU time (on all processors): 00:00:01 + + ++----------------+ +; Files Restored ; ++----------------+ +; File Name ; ++----------------+ + + ++------------------------------------+ +; Files Not Restored ; ++------------------------------------+ +; File Name ; ++------------------------------------+ +; qar_info.json ; +; clk_gen.ppf ; +; clk_gen.qip ; +; clk_gen.v ; +; clk_gen_bb.v ; +; clk_gen_inst.v ; +; clkgen.ppf ; +; clkgen.qip ; +; clkgen.v ; +; clkgen_bb.v ; +; clkgen_inst.v ; +; ddr_ctrl.v ; +; ddr_ctrl_tb.v ; +; intan_m10.qpf ; +; intan_m10.qsf ; +; intan_m10.v ; +; intan_m10_assignment_defaults.qdf ; +; output_files/intan_m10.asm.rpt ; +; output_files/intan_m10.cdf ; +; output_files/intan_m10.done ; +; output_files/intan_m10.eda.rpt ; +; output_files/intan_m10.fit.rpt ; +; output_files/intan_m10.fit.smsg ; +; output_files/intan_m10.fit.summary ; +; output_files/intan_m10.flow.rpt ; +; output_files/intan_m10.jdi ; +; output_files/intan_m10.map.rpt ; +; output_files/intan_m10.map.smsg ; +; output_files/intan_m10.map.summary ; +; output_files/intan_m10.pin ; +; output_files/intan_m10.pof ; +; output_files/intan_m10.pow.rpt ; +; output_files/intan_m10.pow.summary ; +; output_files/intan_m10.sld ; +; output_files/intan_m10.sof ; +; output_files/intan_m10.sta.rpt ; +; output_files/intan_m10.sta.summary ; +; spi_master_2164.v ; +; spi_master_esp32.v ; +; assignment_defaults.qdf ; ++------------------------------------+ + + diff --git a/puart2/uart_tx_restored/intan_m10.v b/puart2/uart_tx_restored/intan_m10.v new file mode 100644 index 0000000..aea94c7 --- /dev/null +++ b/puart2/uart_tx_restored/intan_m10.v @@ -0,0 +1,83 @@ +module uart_tx ( + input wire clk, // 时钟信号 + input wire rst, // 复位信号 + input wire tx_start, // 开始发送信号 + input wire [15:0] tx_data, // 顶层输入的16位待发送数据 + output wire tx, // 串行输出信号 + output reg tx_done // 发送完成信号 +); + +parameter BAUD_RATE = 115200; +parameter CLOCK_FREQ = 12000000; // 12 MHz时钟 + +localparam integer BAUD_TICK = CLOCK_FREQ / BAUD_RATE; // 波特率计数，计算出每个比特的时钟周期数 + +// 波特率计数器 +reg [15:0] baud_counter; +reg [7:0] data_to_send; // 用于存储当前要发送的8位数据 +reg [1:0] byte_select; // 控制发送高8位还是低8位数据 + +// 发送状态机定义 +reg [3:0] tx_state; +reg [9:0] tx_shift_reg; // 10位移位寄存器（8位数据 + 起始位 + 停止位） +reg [3:0] tx_bit_counter; // 用于计数8位数据发送的每一位 + +// 波特率计数器更新 +always @(posedge clk or negedge rst) begin + if (!rst) begin + baud_counter <= 0; + end + else if (baud_counter == BAUD_TICK - 1) + baud_counter <= 0; + else + baud_counter <= baud_counter + 1; +end + +// UART发送逻辑 +always @(posedge clk or negedge rst) begin + if (!rst) begin + tx_state <= 0; + tx_done <= 0; + byte_select <= 0; + tx_shift_reg <= 10'b1111111111; // 空闲状态（全1表示停止位） + end + else if (baud_counter == BAUD_TICK - 1) begin + case (tx_state) + 0: begin + if (tx_start) begin + // 根据 byte_select 选择发送高8位或低8位数据 + if (byte_select == 0) + data_to_send <= tx_data[15:8]; // 发送低8位 + else + data_to_send <= tx_data[7:0]; // 发送高8位 + + // 将要发送的8位数据加上起始位（0）和停止位（1） + tx_shift_reg <= {1'b1, data_to_send, 1'b0}; // 1位停止位，8位数据，1位起始位 + tx_bit_counter <= 0; + tx_state <= 1; + tx_done <= 0; + end + end + 1: begin + // 每个波特率时钟周期发送一位 + if (tx_bit_counter == 9) begin // 所有位发送完成后回到空闲状态 + if (byte_select == 0) + byte_select <= 1; // 切换到发送高8位 + else begin + byte_select <= 0; // 重置为低8位 + tx_done <= 1; // 完成整个16位数据的发送 + end + tx_state <= 0; + end + else begin + tx_shift_reg <= {1'b1, tx_shift_reg[9:1]}; // 右移移位寄存器 + tx_bit_counter <= tx_bit_counter + 1; + end + end + endcase + end +end + +assign tx = tx_shift_reg[0]; // 串行输出当前最低位 + +endmodule \ No newline at end of file diff --git a/puart2/uart_tx_restored/intan_m10.v.bak b/puart2/uart_tx_restored/intan_m10.v.bak new file mode 100644 index 0000000..b825663 --- /dev/null +++ b/puart2/uart_tx_restored/intan_m10.v.bak @@ -0,0 +1,82 @@ +module uart_tx ( + input wire clk, // 时钟信号 + input wire rst, // 复位信号 + input wire tx_start, // 开始发送信号 + input wire [15:0] tx_data, // 顶层输入的16位待发送数据 + output wire tx, // 串行输出信号 + output reg tx_done // 发送完成信号 +); + +parameter BAUD_RATE = 115200; +parameter CLOCK_FREQ = 12000000; // 12 MHz时钟 + +localparam integer BAUD_TICK = CLOCK_FREQ / BAUD_RATE; // 波特率计数，计算出每个比特的时钟周期数 + +// 波特率计数器 +reg [15:0] baud_counter; +reg [7:0] data_to_send; // 用于存储当前要发送的8位数据 +reg [1:0] byte_select; // 控制发送高8位还是低8位数据 + +// 发送状态机定义 +reg [3:0] tx_state; +reg [9:0] tx_shift_reg; // 10位移位寄存器（8位数据 + 起始位 + 停止位） +reg [3:0] tx_bit_counter; // 用于计数8位数据发送的每一位 + +// 波特率计数器更新 +always @(posedge clk or posedge rst) begin + if (!rst) + baud_counter <= 0; + else if (baud_counter == BAUD_TICK - 1) + baud_counter <= 0; + else + baud_counter <= baud_counter + 1; +end + +// UART发送逻辑 +always @(posedge clk or posedge rst) begin + if (!rst) begin + tx_state <= 0; + tx_done <= 0; + byte_select <= 0; + tx_shift_reg <= 10'b1111111111; // 空闲状态（全1表示停止位） + end + else if (baud_counter == BAUD_TICK - 1) begin + case (tx_state) + 0: begin + if (tx_start) begin + // 根据 byte_select 选择发送高8位或低8位数据 + if (byte_select == 0) + data_to_send <= tx_data[15:8]; // 发送低8位 + else + data_to_send <= tx_data[7:0]; // 发送高8位 + + // 将要发送的8位数据加上起始位（0）和停止位（1） + tx_shift_reg <= {1'b1, data_to_send, 1'b0}; // 1位停止位，8位数据，1位起始位 + tx_bit_counter <= 0; + tx_state <= 1; + tx_done <= 0; + end + end + 1: begin + // 每个波特率时钟周期发送一位 + if (tx_bit_counter == 9) begin // 所有位发送完成后回到空闲状态 + if (byte_select == 0) + byte_select <= 1; // 切换到发送高8位 + else begin + byte_select <= 0; // 重置为低8位 + tx_done <= 1; // 完成整个16位数据的发送 + end + tx_state <= 0; + end + else begin + tx_shift_reg <= {1'b1, tx_shift_reg[9:1]}; // 右移移位寄存器 + tx_bit_counter <= tx_bit_counter + 1; + end + end + endcase + end +end + +assign tx = tx_shift_reg[0]; // 串行输出当前最低位 + +endmodule \ No newline at end of file diff --git a/puart2/uart_tx_restored/intan_m10_assignment_defaults.qdf b/puart2/uart_tx_restored/intan_m10_assignment_defaults.qdf new file mode 100644 index 0000000..55926a4 --- /dev/null +++ b/puart2/uart_tx_restored/intan_m10_assignment_defaults.qdf @@ -0,0 +1,807 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition +# Date created = 17:57:18 April 15, 2024 +# +# -------------------------------------------------------------------------- # +# +# Note: +# +# 1) Do not modify this file. This file was generated +# automatically by the Quartus Prime software and is used +# to preserve global assignments across Quartus Prime versions. +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off +set_global_assignment -name IP_COMPONENT_INTERNAL Off +set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On +set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off +set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off +set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db +set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off +set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off +set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off +set_global_assignment -name HC_OUTPUT_DIR hc_output +set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off +set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off +set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" +set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On +set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On +set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off +set_global_assignment -name REVISION_TYPE Base -family "Arria V" +set_global_assignment -name REVISION_TYPE Base -family "Stratix V" +set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ" +set_global_assignment -name REVISION_TYPE Base -family "Cyclone V" +set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" +set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On +set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On +set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On +set_global_assignment -name DO_COMBINED_ANALYSIS Off +set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off +set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off +set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off +set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off +set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On +set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone V" +set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V" +set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100 +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V" +set_global_assignment -name OPTIMIZATION_MODE Balanced +set_global_assignment -name ALLOW_REGISTER_MERGING On +set_global_assignment -name ALLOW_REGISTER_DUPLICATION On +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix IV" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV E" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Arria 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX II" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone V" +set_global_assignment -name MUX_RESTRUCTURE Auto +set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off +set_global_assignment -name ENABLE_IP_DEBUG Off +set_global_assignment -name SAVE_DISK_SPACE On +set_global_assignment -name OCP_HW_EVAL Enable +set_global_assignment -name DEVICE_FILTER_PACKAGE Any +set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name TRUE_WYSIWYG_FLOW Off +set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off +set_global_assignment -name STATE_MACHINE_PROCESSING Auto +set_global_assignment -name SAFE_STATE_MACHINE Off +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On +set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On +set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off +set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 +set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 +set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On +set_global_assignment -name PARALLEL_SYNTHESIS On +set_global_assignment -name DSP_BLOCK_BALANCING Auto +set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" +set_global_assignment -name NOT_GATE_PUSH_BACK On +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On +set_global_assignment -name IGNORE_CARRY_BUFFERS Off +set_global_assignment -name IGNORE_CASCADE_BUFFERS Off +set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_LCELL_BUFFERS Off +set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO +set_global_assignment -name IGNORE_SOFT_BUFFERS On +set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off +set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off +set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On +set_global_assignment -name AUTO_GLOBAL_OE_MAX On +set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off +set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut +set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name ALLOW_XOR_GATE_USAGE On +set_global_assignment -name AUTO_LCELL_INSERTION On +set_global_assignment -name CARRY_CHAIN_LENGTH 48 +set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 +set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name CASCADE_CHAIN_LENGTH 2 +set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 +set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 +set_global_assignment -name AUTO_CARRY_CHAINS On +set_global_assignment -name AUTO_CASCADE_CHAINS On +set_global_assignment -name AUTO_PARALLEL_EXPANDERS On +set_global_assignment -name AUTO_OPEN_DRAIN_PINS On +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off +set_global_assignment -name AUTO_ROM_RECOGNITION On +set_global_assignment -name AUTO_RAM_RECOGNITION On +set_global_assignment -name AUTO_DSP_RECOGNITION On +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto +set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On +set_global_assignment -name STRICT_RAM_RECOGNITION Off +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On +set_global_assignment -name FORCE_SYNCH_CLEAR Off +set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On +set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off +set_global_assignment -name AUTO_RESOURCE_SHARING Off +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off +set_global_assignment -name MAX7000_FANIN_PER_CELL 100 +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On +set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" +set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off +set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" +set_global_assignment -name REPORT_PARAMETER_SETTINGS On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On +set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100 +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 +set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000 +set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off +set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" +set_global_assignment -name MAX_LABS "-1 (Unlimited)" +set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On +set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" +set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On +set_global_assignment -name PRPOF_ID Off +set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off +set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On +set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name TXPMA_SLEW_RATE Low +set_global_assignment -name ADCE_ENABLED Auto +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name PHYSICAL_SYNTHESIS Off +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name ENABLE_NCEO_OUTPUT Off +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image" +set_global_assignment -name CVP_MODE Off +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V" +set_global_assignment -name VID_OPERATION_MODE "PMBus Slave" +set_global_assignment -name USE_CONF_DONE AUTO +set_global_assignment -name USE_PWRMGT_SCL AUTO +set_global_assignment -name USE_PWRMGT_SDA AUTO +set_global_assignment -name USE_PWRMGT_ALERT AUTO +set_global_assignment -name USE_INIT_DONE AUTO +set_global_assignment -name USE_CVP_CONFDONE AUTO +set_global_assignment -name USE_SEU_ERROR AUTO +set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off +set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On +set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name INIT_DONE_OPEN_DRAIN On +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name ENABLE_CONFIGURATION_PINS On +set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off +set_global_assignment -name ENABLE_NCE_PIN Off +set_global_assignment -name ENABLE_BOOT_SEL_PIN On +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name INTERNAL_SCRUBBING Off +set_global_assignment -name PR_ERROR_OPEN_DRAIN On +set_global_assignment -name PR_READY_OPEN_DRAIN On +set_global_assignment -name ENABLE_CVP_CONFDONE Off +set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On +set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ" +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF +set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto +set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V" +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto +set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" +set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off +set_global_assignment -name PR_DONE_OPEN_DRAIN On +set_global_assignment -name NCEO_OPEN_DRAIN On +set_global_assignment -name ENABLE_CRC_ERROR_PIN Off +set_global_assignment -name ENABLE_PR_PINS Off +set_global_assignment -name RESERVE_PR_PINS Off +set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off +set_global_assignment -name PR_PINS_OPEN_DRAIN Off +set_global_assignment -name CLAMPING_DIODE Off +set_global_assignment -name TRI_STATE_SPI_PINS Off +set_global_assignment -name UNUSED_TSD_PINS_GND Off +set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off +set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V" +set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0 +set_global_assignment -name SEU_FIT_REPORT Off +set_global_assignment -name HYPER_RETIMER Off -family "Arria 10" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE On +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130" +set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000 +set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery" +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0 +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP" +set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V" +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF +set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off +set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off +set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off +set_global_assignment -name POR_SCHEME "Instant ON" +set_global_assignment -name EN_USER_IO_WEAK_PULLUP On +set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On +set_global_assignment -name POF_VERIFY_PROTECT Off +set_global_assignment -name ENABLE_SPI_MODE_CHECK Off +set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On +set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0 +set_global_assignment -name GENERATE_PMSF_FILES On +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment 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SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name POWER_HPS_ENABLE Off +set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 +set_global_assignment -name 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EQC_RAM_REGISTER_UNPACK On +set_global_assignment -name EQC_MAC_REGISTER_UNPACK On +set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? 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-section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? 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? +set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? +set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? +set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? +set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? +set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ? diff --git a/puart2/uart_tx_restored/output_files/greybox_tmp/cbx_args.txt b/puart2/uart_tx_restored/output_files/greybox_tmp/cbx_args.txt new file mode 100644 index 0000000..ba166fc --- /dev/null +++ b/puart2/uart_tx_restored/output_files/greybox_tmp/cbx_args.txt @@ -0,0 +1,63 @@ +BANDWIDTH_TYPE=AUTO +CLK0_DIVIDE_BY=625 +CLK0_DUTY_CYCLE=50 +CLK0_MULTIPLY_BY=6 +CLK0_PHASE_SHIFT=0 +CLK1_DIVIDE_BY=625 +CLK1_DUTY_CYCLE=50 +CLK1_MULTIPLY_BY=12 +CLK1_PHASE_SHIFT=0 +COMPENSATE_CLOCK=CLK0 +INCLK0_INPUT_FREQUENCY=83333 +INTENDED_DEVICE_FAMILY="MAX 10" +LPM_TYPE=altpll +OPERATION_MODE=NORMAL +PLL_TYPE=AUTO +PORT_ACTIVECLOCK=PORT_UNUSED +PORT_ARESET=PORT_UNUSED +PORT_CLKBAD0=PORT_UNUSED +PORT_CLKBAD1=PORT_UNUSED +PORT_CLKLOSS=PORT_UNUSED +PORT_CLKSWITCH=PORT_UNUSED +PORT_CONFIGUPDATE=PORT_UNUSED +PORT_FBIN=PORT_UNUSED +PORT_INCLK0=PORT_USED +PORT_INCLK1=PORT_UNUSED +PORT_LOCKED=PORT_UNUSED +PORT_PFDENA=PORT_UNUSED +PORT_PHASECOUNTERSELECT=PORT_UNUSED +PORT_PHASEDONE=PORT_UNUSED +PORT_PHASESTEP=PORT_UNUSED +PORT_PHASEUPDOWN=PORT_UNUSED +PORT_PLLENA=PORT_UNUSED +PORT_SCANACLR=PORT_UNUSED +PORT_SCANCLK=PORT_UNUSED +PORT_SCANCLKENA=PORT_UNUSED +PORT_SCANDATA=PORT_UNUSED +PORT_SCANDATAOUT=PORT_UNUSED +PORT_SCANDONE=PORT_UNUSED +PORT_SCANREAD=PORT_UNUSED +PORT_SCANWRITE=PORT_UNUSED +PORT_clk0=PORT_USED +PORT_clk1=PORT_USED +PORT_clk2=PORT_UNUSED +PORT_clk3=PORT_UNUSED +PORT_clk4=PORT_UNUSED +PORT_clk5=PORT_UNUSED +PORT_clkena0=PORT_UNUSED +PORT_clkena1=PORT_UNUSED +PORT_clkena2=PORT_UNUSED +PORT_clkena3=PORT_UNUSED +PORT_clkena4=PORT_UNUSED +PORT_clkena5=PORT_UNUSED +PORT_extclk0=PORT_UNUSED +PORT_extclk1=PORT_UNUSED +PORT_extclk2=PORT_UNUSED +PORT_extclk3=PORT_UNUSED +WIDTH_CLOCK=5 +DEVICE_FAMILY="MAX 10" +CBX_AUTO_BLACKBOX=ALL +inclk +inclk +clk +clk diff --git a/puart2/uart_tx_restored/output_files/intan_m10.asm.rpt b/puart2/uart_tx_restored/output_files/intan_m10.asm.rpt new file mode 100644 index 0000000..b2c478f --- /dev/null +++ b/puart2/uart_tx_restored/output_files/intan_m10.asm.rpt @@ -0,0 +1,91 @@ +Assembler report for intan_m10 +Sat Dec 6 16:45:19 2025 +Quartus Prime Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: E:/FPGA/20240726/uart_tx_restored/output_files/intan_m10.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2024 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Sat Dec 6 16:45:19 2025 ; +; Revision Name ; intan_m10 ; +; Top-level Entity Name ; ddr_ctrl ; +; Family ; MAX 10 ; +; Device ; 10M08SAM153C8G ; ++-----------------------+---------------------------------------+ + + ++----------------------------------+ +; Assembler Settings ; ++--------+---------+---------------+ +; Option ; Setting ; Default Value ; ++--------+---------+---------------+ + + ++--------------------------------------------------------------+ +; Assembler Generated Files ; ++--------------------------------------------------------------+ +; File Name ; ++--------------------------------------------------------------+ +; E:/FPGA/20240726/uart_tx_restored/output_files/intan_m10.sof ; ++--------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------+ +; Assembler Device Options: E:/FPGA/20240726/uart_tx_restored/output_files/intan_m10.sof ; ++----------------+-----------------------------------------------------------------------+ +; Option ; Setting ; ++----------------+-----------------------------------------------------------------------+ +; JTAG usercode ; 0x00096EE7 ; +; Checksum ; 0x00096EE7 ; ++----------------+-----------------------------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Assembler + Info: Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition + Info: Processing started: Sat Dec 6 16:45:18 2025 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10 +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 4687 megabytes + Info: Processing ended: Sat Dec 6 16:45:19 2025 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/puart2/uart_tx_restored/output_files/intan_m10.cdf b/puart2/uart_tx_restored/output_files/intan_m10.cdf new file mode 100644 index 0000000..26c5c3c --- /dev/null +++ b/puart2/uart_tx_restored/output_files/intan_m10.cdf @@ -0,0 +1,13 @@ +/* Quartus Prime Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition */ +JedecChain; + FileRevision(JESD32A); + DefaultMfr(6E); + + P ActionCode(Cfg) + Device PartName(10M08SAM153) Path("E:/FPGA/20240726/uart_tx_restored/output_files/") File("intan_m10.pof") MfrSpec(OpMask(3) Child_OpMask(2 3 3)); + +ChainEnd; + +AlteraBegin; + ChainType(JTAG); +AlteraEnd; diff --git a/puart2/uart_tx_restored/output_files/intan_m10.done b/puart2/uart_tx_restored/output_files/intan_m10.done new file mode 100644 index 0000000..3702814 --- /dev/null +++ b/puart2/uart_tx_restored/output_files/intan_m10.done @@ -0,0 +1 @@ +Sat Dec 6 16:45:31 2025 diff --git a/puart2/uart_tx_restored/output_files/intan_m10.eda.rpt b/puart2/uart_tx_restored/output_files/intan_m10.eda.rpt new file mode 100644 index 0000000..87000b0 --- /dev/null +++ b/puart2/uart_tx_restored/output_files/intan_m10.eda.rpt @@ -0,0 +1,60 @@ +EDA Netlist Writer report for intan_m10 +Mon Apr 15 18:12:21 2024 +Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++----------------------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++---------------------------+------------------------------------------------------+ +; EDA Netlist Writer Status ; No Output Files Generated - Mon Apr 15 18:12:21 2024 ; +; Revision Name ; intan_m10 ; +; Top-level Entity Name ; ddr_ctrl ; +; Family ; MAX 10 ; ++---------------------------+------------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime EDA Netlist Writer + Info: Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition + Info: Processing started: Mon Apr 15 18:12:20 2024 +Info: Command: quartus_eda --read_settings_files=on --write_settings_files=off intan_m10 -c intan_m10 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Warning (199027): Can't generate output files. Specify command-line options to generate output files, or update EDA tool settings using GUI or Tcl script. +Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 2 warnings + Info: Peak virtual memory: 4633 megabytes + Info: Processing ended: Mon Apr 15 18:12:21 2024 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:00 + + diff --git a/puart2/uart_tx_restored/output_files/intan_m10.fit.rpt b/puart2/uart_tx_restored/output_files/intan_m10.fit.rpt new file mode 100644 index 0000000..0e87062 --- /dev/null +++ b/puart2/uart_tx_restored/output_files/intan_m10.fit.rpt @@ -0,0 +1,1174 @@ +Fitter report for intan_m10 +Sat Dec 6 16:45:17 2025 +Quartus Prime Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Ignored Assignments + 6. Incremental Compilation Preservation Summary + 7. Incremental Compilation Partition Settings + 8. Incremental Compilation Placement Preservation + 9. Pin-Out File + 10. Fitter Resource Usage Summary + 11. Fitter Partition Statistics + 12. Input Pins + 13. Output Pins + 14. Dual Purpose and Dedicated Pins + 15. I/O Bank Usage + 16. All Package Pins + 17. PLL Summary + 18. PLL Usage + 19. I/O Assignment Warnings + 20. Fitter Resource Utilization by Entity + 21. Delay Chain Summary + 22. Pad To Core Delay Chain Fanout + 23. Control Signals + 24. Global & Other Fast Signals + 25. Routing Usage Summary + 26. LAB Logic Elements + 27. LAB-wide Signals + 28. LAB Signals Sourced + 29. LAB Signals Sourced Out + 30. LAB Distinct Inputs + 31. I/O Rules Summary + 32. I/O Rules Details + 33. I/O Rules Matrix + 34. Fitter Device Options + 35. Operating Settings and Conditions + 36. Estimated Delay Added for Hold Timing Summary + 37. Estimated Delay Added for Hold Timing Details + 38. Fitter Messages + 39. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2024 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++-------------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+------------------------------------------------+ +; Fitter Status ; Successful - Sat Dec 6 16:45:17 2025 ; +; Quartus Prime Version ; 23.1std.1 Build 993 05/14/2024 SC Lite Edition ; +; Revision Name ; intan_m10 ; +; Top-level Entity Name ; ddr_ctrl ; +; Family ; MAX 10 ; +; Device ; 10M08SAM153C8G ; +; Timing Models ; Final ; +; Total logic elements ; 120 / 8,064 ( 1 % ) ; +; Total combinational functions ; 112 / 8,064 ( 1 % ) ; +; Dedicated logic registers ; 79 / 8,064 ( < 1 % ) ; +; Total registers ; 79 ; +; Total pins ; 13 / 112 ( 12 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 387,072 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 48 ( 0 % ) ; +; Total PLLs ; 1 / 1 ( 100 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 1 ( 0 % ) ; ++------------------------------------+------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; 10M08SAM153C8G ; ; +; Maximum processors allowed for parallel compilation ; 4 ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; Power Optimization During Fitting ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Periphery to Core Placement and Routing Optimization ; Off ; Off ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Auto ; Auto ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.07 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 2.2% ; +; Processors 3-4 ; 2.2% ; ++----------------------------+-------------+ + + ++----------------------------------------------------------------------------------------+ +; Ignored Assignments ; ++----------+----------------+--------------+------------+---------------+----------------+ +; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ; ++----------+----------------+--------------+------------+---------------+----------------+ +; Location ; ; ; UART_tx ; PIN_A5 ; QSF Assignment ; ++----------+----------------+--------------+------------+---------------+----------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+--------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+--------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 237 ) ; 0.00 % ( 0 / 237 ) ; 0.00 % ( 0 / 237 ) ; +; -- Achieved ; 0.00 % ( 0 / 237 ) ; 0.00 % ( 0 / 237 ) ; 0.00 % ( 0 / 237 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+--------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 218 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 19 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in E:/FPGA/20240726/uart_tx_restored/output_files/intan_m10.pin. + + ++--------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+----------------------+ +; Resource ; Usage ; ++---------------------------------------------+----------------------+ +; Total logic elements ; 120 / 8,064 ( 1 % ) ; +; -- Combinational with no register ; 41 ; +; -- Register only ; 8 ; +; -- Combinational with a register ; 71 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 57 ; +; -- 3 input functions ; 10 ; +; -- <=2 input functions ; 45 ; +; -- Register only ; 8 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 91 ; +; -- arithmetic mode ; 21 ; +; ; ; +; Total registers* ; 79 / 8,597 ( < 1 % ) ; +; -- Dedicated logic registers ; 79 / 8,064 ( < 1 % ) ; +; -- I/O registers ; 0 / 533 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 11 / 504 ( 2 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 13 / 112 ( 12 % ) ; +; -- Clock pins ; 2 / 4 ( 50 % ) ; +; -- Dedicated input pins ; 1 / 1 ( 100 % ) ; +; ; ; +; M9Ks ; 0 / 42 ( 0 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 1 ( 0 % ) ; +; Total block memory bits ; 0 / 387,072 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 387,072 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 48 ( 0 % ) ; +; PLLs ; 1 / 1 ( 100 % ) ; +; Global signals ; 3 ; +; -- Global clocks ; 3 / 10 ( 30 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; Remote update blocks ; 0 / 1 ( 0 % ) ; +; Oscillator blocks ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0.3% / 0.3% / 0.2% ; +; Peak interconnect usage (total/H/V) ; 1.2% / 1.2% / 1.2% ; +; Maximum fan-out ; 77 ; +; Highest non-global fan-out ; 77 ; +; Total fan-out ; 623 ; +; Average fan-out ; 2.53 ; ++---------------------------------------------+----------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++----------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+---------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++---------------------------------------------+---------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; +; ; ; ; +; Total logic elements ; 120 / 8064 ( 1 % ) ; 0 / 8064 ( 0 % ) ; +; -- Combinational with no register ; 41 ; 0 ; +; -- Register only ; 8 ; 0 ; +; -- Combinational with a register ; 71 ; 0 ; +; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; +; -- 4 input functions ; 57 ; 0 ; +; -- 3 input functions ; 10 ; 0 ; +; -- <=2 input functions ; 45 ; 0 ; +; -- Register only ; 8 ; 0 ; +; ; ; ; +; Logic elements by mode ; ; ; +; -- normal mode ; 91 ; 0 ; +; -- arithmetic mode ; 21 ; 0 ; +; ; ; ; +; Total registers ; 79 ; 0 ; +; -- Dedicated logic registers ; 79 / 8064 ( < 1 % ) ; 0 / 8064 ( 0 % ) ; +; -- I/O registers ; 0 ; 0 ; +; ; ; ; +; Total LABs: partially or completely used ; 11 / 504 ( 2 % ) ; 0 / 504 ( 0 % ) ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 13 ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 / 48 ( 0 % ) ; 0 / 48 ( 0 % ) ; +; Total memory bits ; 0 ; 0 ; +; Total RAM block bits ; 0 ; 0 ; +; PLL ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ; +; Clock control block ; 1 / 12 ( 8 % ) ; 2 / 12 ( 16 % ) ; +; User Flash Memory ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; +; Analog-to-Digital Converter ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 48 ; 1 ; +; -- Registered Input Connections ; 48 ; 0 ; +; -- Output Connections ; 1 ; 48 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 620 ; 60 ; +; -- Registered Connections ; 308 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 49 ; +; -- hard_block:auto_generated_inst ; 49 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 4 ; 1 ; +; -- Output Ports ; 9 ; 2 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++---------------------------------------------+---------------------+--------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++-----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ; ++-----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; miso ; R3 ; 3 ; 3 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVCMOS ; -- ; User ; 0 ; +; rst_n ; J14 ; 5 ; 31 ; 6 ; 0 ; 77 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVCMOS ; -- ; User ; 0 ; +; sys_clk ; J5 ; 2 ; 0 ; 7 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVCMOS ; -- ; User ; 0 ; +; test_flag ; J12 ; 6 ; 31 ; 9 ; 21 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVCMOS ; -- ; User ; 0 ; ++-----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; MOSI_ESP32 ; A14 ; 8 ; 13 ; 25 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; convert_flag_led ; M12 ; 5 ; 31 ; 1 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 2mA ; Off ; -- ; no ; no ; User ; - ; - ; +; cs_ESP32 ; B13 ; 8 ; 15 ; 25 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; cs_n ; P6 ; 3 ; 9 ; 0 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 2mA ; Off ; -- ; no ; no ; User ; - ; - ; +; mosi ; M5 ; 3 ; 3 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 2mA ; Off ; -- ; no ; no ; User ; - ; - ; +; sclk ; P3 ; 3 ; 3 ; 0 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 2mA ; Off ; -- ; no ; no ; User ; - ; - ; +; sclk_ESP32 ; B14 ; 8 ; 15 ; 25 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; test_flag_led ; N15 ; 5 ; 31 ; 1 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 2mA ; Off ; -- ; no ; no ; User ; - ; - ; +; tx ; P15 ; 3 ; 13 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 2mA ; Off ; -- ; no ; no ; User ; - ; - ; ++------------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Dual Purpose and Dedicated Pins ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ +; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ +; G1 ; DIFFIO_RX_L11n, DIFFOUT_L11n, TMS, Low_Speed ; Reserved as secondary function ; ~ALTERA_TMS~ ; Dual Purpose Pin ; +; J1 ; DIFFIO_RX_L11p, DIFFOUT_L11p, TCK, Low_Speed ; Reserved as secondary function ; ~ALTERA_TCK~ ; Dual Purpose Pin ; +; H5 ; DIFFIO_RX_L12n, DIFFOUT_L12n, TDI, Low_Speed ; Reserved as secondary function ; ~ALTERA_TDI~ ; Dual Purpose Pin ; +; H4 ; DIFFIO_RX_L12p, DIFFOUT_L12p, TDO, Low_Speed ; Reserved as secondary function ; ~ALTERA_TDO~ ; Dual Purpose Pin ; +; D8 ; CONFIG_SEL, Low_Speed ; Reserved as secondary function ; ~ALTERA_CONFIG_SEL~ ; Dual Purpose Pin ; +; E8 ; nCONFIG, Low_Speed ; Reserved as secondary function ; ~ALTERA_nCONFIG~ ; Dual Purpose Pin ; +; D6 ; DIFFIO_RX_T24p, DIFFOUT_T24p, nSTATUS, Low_Speed ; Reserved as secondary function ; ~ALTERA_nSTATUS~ ; Dual Purpose Pin ; +; E6 ; DIFFIO_RX_T24n, DIFFOUT_T24n, CONF_DONE, Low_Speed ; Reserved as secondary function ; ~ALTERA_CONF_DONE~ ; Dual Purpose Pin ; ++----------+----------------------------------------------------+--------------------------------+---------------------+------------------+ + + ++-----------------------------------------------------------+ +; I/O Bank Usage ; ++----------+-----------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+-----------------+---------------+--------------+ +; 1A ; 0 / 8 ( 0 % ) ; 2.5V ; -- ; +; 1B ; 4 / 10 ( 40 % ) ; 2.5V ; -- ; +; 2 ; 1 / 10 ( 10 % ) ; 3.3V ; -- ; +; 3 ; 5 / 28 ( 18 % ) ; 3.3V ; -- ; +; 5 ; 3 / 12 ( 25 % ) ; 3.3V ; -- ; +; 6 ; 1 / 16 ( 6 % ) ; 3.3V ; -- ; +; 8 ; 7 / 28 ( 25 % ) ; 2.5V ; -- ; ++----------+-----------------+---------------+--------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+-----------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+-----------+------------+-----------------+----------+--------------+ +; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A2 ; 248 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A3 ; 250 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A5 ; 243 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A7 ; 241 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A9 ; 237 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A11 ; 239 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A13 ; 231 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; A14 ; 227 ; 8 ; MOSI_ESP32 ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B1 ; 10 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B3 ; ; -- ; VCCA3 ; power ; ; 3.0V/3.3V ; -- ; ; -- ; -- ; +; B4 ; 245 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B5 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; B6 ; 238 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B7 ; 236 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B8 ; 226 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; B10 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; B11 ; 235 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B12 ; 233 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B13 ; 225 ; 8 ; cs_ESP32 ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B14 ; 223 ; 8 ; sclk_ESP32 ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B15 ; 221 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C1 ; 8 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C2 ; 2 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C8 ; 224 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C14 ; 179 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C15 ; 177 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D2 ; 0 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D4 ; ; ; ANAIN1 ; ; ; ; -- ; ; -- ; -- ; +; D5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D6 ; 244 ; 8 ; ~ALTERA_nSTATUS~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; D7 ; 240 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D8 ; 232 ; 8 ; ~ALTERA_CONFIG_SEL~ / RESERVED_INPUT ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ; +; D9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D10 ; 222 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D11 ; 220 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D12 ; 190 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D14 ; ; -- ; VCCA2 ; power ; ; 3.0V/3.3V ; -- ; ; -- ; -- ; +; E1 ; 12 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E2 ; 14 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E4 ; ; ; REFGND ; ; ; ; -- ; ; -- ; -- ; +; E5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E6 ; 246 ; 8 ; ~ALTERA_CONF_DONE~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; E7 ; 242 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E8 ; 234 ; 8 ; ~ALTERA_nCONFIG~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Column I/O ; N ; no ; Off ; +; E9 ; 230 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E10 ; 228 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; E11 ; 188 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E14 ; 175 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E15 ; 173 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; F2 ; ; 1A ; VCCIO1A ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F4 ; ; ; ADC_VREF ; ; ; ; -- ; ; -- ; -- ; +; F5 ; 4 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F11 ; 176 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F12 ; 178 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F14 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; G1 ; 20 ; 1B ; ~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; On ; +; G2 ; 21 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G5 ; 6 ; 1A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G7 ; 18 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G8 ; ; -- ; VCC_ONE ; power ; ; 3.0V/3.3V ; -- ; ; -- ; -- ; +; G9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G11 ; 172 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G12 ; 174 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G14 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; G15 ; 158 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H2 ; ; 1B ; VCCIO1B ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; H3 ; 28 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H4 ; 26 ; 1B ; ~ALTERA_TDO~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; H5 ; 24 ; 1B ; ~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; On ; +; H7 ; ; -- ; VCC_ONE ; power ; ; 3.0V/3.3V ; -- ; ; -- ; -- ; +; H8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H9 ; ; -- ; VCC_ONE ; power ; ; 3.0V/3.3V ; -- ; ; -- ; -- ; +; H11 ; 150 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H12 ; 152 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H13 ; 154 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J1 ; 22 ; 1B ; ~ALTERA_TCK~ / RESERVED_INPUT ; input ; 2.5 V Schmitt Trigger ; ; Row I/O ; N ; no ; Off ; +; J2 ; 30 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J4 ; 36 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J5 ; 38 ; 2 ; sys_clk ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; J7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J8 ; ; -- ; VCC_ONE ; power ; ; 3.0V/3.3V ; -- ; ; -- ; -- ; +; J9 ; 140 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J11 ; 142 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J12 ; 148 ; 6 ; test_flag ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; J14 ; 143 ; 5 ; rst_n ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; J15 ; 156 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K2 ; 34 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K4 ; 42 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K5 ; 40 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K11 ; 132 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K12 ; 134 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; K14 ; 141 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L1 ; 32 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L2 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; L4 ; 46 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L5 ; 44 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L6 ; 64 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L7 ; 66 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L8 ; 72 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L9 ; 84 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L10 ; 88 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; L11 ; 122 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; L15 ; 135 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; M2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M4 ; 60 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M5 ; 62 ; 3 ; mosi ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; M6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M7 ; 74 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M8 ; 76 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M9 ; 86 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; 90 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; M12 ; 120 ; 5 ; convert_flag_led ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; M14 ; 133 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N1 ; 56 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N2 ; ; -- ; VCCA1 ; power ; ; 3.0V/3.3V ; -- ; ; -- ; -- ; +; N8 ; 78 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; N14 ; 123 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N15 ; 121 ; 5 ; test_flag_led ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; P1 ; 45 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; P2 ; 58 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P3 ; 61 ; 3 ; sclk ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; P4 ; 65 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P5 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; P6 ; 68 ; 3 ; cs_n ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; P7 ; 70 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P8 ; 71 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P9 ; 73 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P10 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; P11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; P12 ; 79 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P13 ; ; -- ; VCCA4 ; power ; ; 3.0V/3.3V ; -- ; ; -- ; -- ; +; P14 ; 92 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; P15 ; 82 ; 3 ; tx ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; R1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R2 ; 47 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; R3 ; 63 ; 3 ; miso ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; R5 ; 67 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R7 ; 69 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R9 ; 75 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R11 ; 77 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; R13 ; 94 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R14 ; 80 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; ++----------+------------+----------+------------------------------------------------+--------+-----------------------+-----------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++-----------------------------------------------------------------------------------------------------------------+ +; PLL Summary ; ++-------------------------------+---------------------------------------------------------------------------------+ +; Name ; clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|pll1 ; ++-------------------------------+---------------------------------------------------------------------------------+ +; SDC pin name ; clk_gen_inst|altpll_component|auto_generated|pll1 ; +; PLL mode ; Normal ; +; Compensate clock ; clock0 ; +; Compensated input/output pins ; -- ; +; Switchover type ; -- ; +; Input frequency 0 ; 12.0 MHz ; +; Input frequency 1 ; -- ; +; Nominal PFD frequency ; 12.0 MHz ; +; Nominal VCO frequency ; 432.0 MHz ; +; VCO post scale K counter ; 2 ; +; VCO frequency control ; Auto ; +; VCO phase shift step ; 289 ps ; +; VCO multiply ; -- ; +; VCO divide ; -- ; +; Freq min lock ; 9.8 MHz ; +; Freq max lock ; 18.06 MHz ; +; M VCO Tap ; 0 ; +; M Initial ; 1 ; +; M value ; 36 ; +; N value ; 1 ; +; Charge pump current ; setting 1 ; +; Loop filter resistance ; setting 24 ; +; Loop filter capacitance ; setting 0 ; +; Bandwidth ; 450 kHz to 980 kHz ; +; Bandwidth type ; Medium ; +; Real time reconfigurable ; Off ; +; Scan chain MIF file ; -- ; +; Preserve PLL counter order ; Off ; +; PLL location ; PLL_1 ; +; Inclk0 signal ; sys_clk ; +; Inclk1 signal ; -- ; +; Inclk0 signal type ; Dedicated Pin ; +; Inclk1 signal type ; -- ; ++-------------------------------+---------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; PLL Usage ; ++--------------------------------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+-------------+---------------+---------+---------+----------------------------------------------------------+ +; Name ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift ; Phase Shift Step ; Duty Cycle ; Counter ; Counter Value ; High / Low ; Cascade Input ; Initial ; VCO Tap ; SDC Pin Name ; ++--------------------------------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+-------------+---------------+---------+---------+----------------------------------------------------------+ +; clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|wire_pll1_clk[0] ; clock0 ; 6 ; 625 ; 0.12 MHz ; 0 (0 ps) ; 0.12 (289 ps) ; 50/50 ; C1 ; 375 ; 188/187 Odd ; C0 ; 1 ; 0 ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; +; clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|wire_pll1_clk[1] ; clock1 ; 12 ; 625 ; 0.23 MHz ; 0 (0 ps) ; 0.12 (289 ps) ; 50/50 ; C3 ; 375 ; 188/187 Odd ; C2 ; 1 ; 0 ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] ; +; clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|wire_pll1_clk[1]~cascade_in ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; C2 ; 5 ; 2/3 Odd ; -- ; 1 ; 0 ; ; +; clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|wire_pll1_clk[0]~cascade_in ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; C0 ; 10 ; 5/5 Even ; -- ; 1 ; 0 ; ; ++--------------------------------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+-------------+---------------+---------+---------+----------------------------------------------------------+ + + ++--------------------------------------------------+ +; I/O Assignment Warnings ; ++------------------+-------------------------------+ +; Pin Name ; Reason ; ++------------------+-------------------------------+ +; mosi ; Missing drive strength ; +; cs_n ; Missing drive strength ; +; sclk ; Missing drive strength ; +; MOSI_ESP32 ; Incomplete set of assignments ; +; cs_ESP32 ; Incomplete set of assignments ; +; sclk_ESP32 ; Incomplete set of assignments ; +; tx ; Missing drive strength ; +; test_flag_led ; Missing drive strength ; +; convert_flag_led ; Missing drive strength ; ++------------------+-------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++------------------------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+--------------------------------------------------------------------------------------+-----------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ; ++------------------------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+--------------------------------------------------------------------------------------+-----------------+--------------+ +; |ddr_ctrl ; 120 (44) ; 79 (36) ; 0 (0) ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 13 ; 0 ; 41 (9) ; 8 (7) ; 71 (26) ; 0 ; |ddr_ctrl ; ddr_ctrl ; work ; +; |clk_gen:clk_gen_inst| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; |ddr_ctrl|clk_gen:clk_gen_inst ; clk_gen ; work ; +; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; |ddr_ctrl|clk_gen:clk_gen_inst|altpll:altpll_component ; altpll ; work ; +; |clk_gen_altpll:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; |ddr_ctrl|clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated ; clk_gen_altpll ; work ; +; |spi_master_2164:u_spi_master_2164| ; 30 (30) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 17 (17) ; 1 (1) ; 12 (12) ; 0 ; |ddr_ctrl|spi_master_2164:u_spi_master_2164 ; spi_master_2164 ; work ; +; |uart_tx:u_uart_pc| ; 48 (48) ; 33 (33) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 15 (15) ; 0 (0) ; 33 (33) ; 0 ; |ddr_ctrl|uart_tx:u_uart_pc ; uart_tx ; work ; ++------------------------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+--------------------------------------------------------------------------------------+-----------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++--------------------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++------------------+----------+---------------+---------------+-----------------------+-----+------+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; ++------------------+----------+---------------+---------------+-----------------------+-----+------+ +; miso ; Input ; -- ; -- ; -- ; -- ; -- ; +; mosi ; Output ; -- ; -- ; -- ; -- ; -- ; +; cs_n ; Output ; -- ; -- ; -- ; -- ; -- ; +; sclk ; Output ; -- ; -- ; -- ; -- ; -- ; +; MOSI_ESP32 ; Output ; -- ; -- ; -- ; -- ; -- ; +; cs_ESP32 ; Output ; -- ; -- ; -- ; -- ; -- ; +; sclk_ESP32 ; Output ; -- ; -- ; -- ; -- ; -- ; +; tx ; Output ; -- ; -- ; -- ; -- ; -- ; +; test_flag_led ; Output ; -- ; -- ; -- ; -- ; -- ; +; convert_flag_led ; Output ; -- ; -- ; -- ; -- ; -- ; +; test_flag ; Input ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -- ; +; rst_n ; Input ; (6) 873 ps ; -- ; -- ; -- ; -- ; +; sys_clk ; Input ; -- ; -- ; -- ; -- ; -- ; ++------------------+----------+---------------+---------------+-----------------------+-----+------+ + + ++-------------------------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++-------------------------------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++-------------------------------------------------+-------------------+---------+ +; miso ; ; ; +; test_flag ; ; ; +; - Selector7~0 ; 1 ; 0 ; +; - test_flag_led~output ; 0 ; 0 ; +; - convert_flag_led~output ; 0 ; 0 ; +; rst_n ; ; ; +; - state[1] ; 0 ; 6 ; +; - state[2] ; 0 ; 6 ; +; - state[3] ; 0 ; 6 ; +; - state[4] ; 0 ; 6 ; +; - state[5] ; 0 ; 6 ; +; - state[6] ; 0 ; 6 ; +; - state[7] ; 0 ; 6 ; +; - state[8] ; 0 ; 6 ; +; - state[9] ; 0 ; 6 ; +; - state[10] ; 0 ; 6 ; +; - state[11] ; 0 ; 6 ; +; - state[12] ; 0 ; 6 ; +; - state[13] ; 0 ; 6 ; +; - state[14] ; 0 ; 6 ; +; - state[15] ; 0 ; 6 ; +; - state[16] ; 0 ; 6 ; +; - state[17] ; 0 ; 6 ; +; - state[18] ; 0 ; 6 ; +; - state[19] ; 0 ; 6 ; +; - state[20] ; 0 ; 6 ; +; - state[21] ; 0 ; 6 ; +; - state[22] ; 0 ; 6 ; +; - state[23] ; 0 ; 6 ; +; - state[24] ; 0 ; 6 ; +; - state[25] ; 0 ; 6 ; +; - state[26] ; 0 ; 6 ; +; - state[27] ; 0 ; 6 ; +; - state[28] ; 0 ; 6 ; +; - state[29] ; 0 ; 6 ; +; - state[30] ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|mosi ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|sclk ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|cnt[1] ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|cnt[2] ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|cnt[3] ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|cnt[4] ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|cnt[5] ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|cnt[6] ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|cs_n ; 0 ; 6 ; +; - uart_tx:u_uart_pc|tx_shift_reg[0] ; 0 ; 6 ; +; - state[0] ; 0 ; 6 ; +; - start1 ; 0 ; 6 ; +; - spi_master_2164:u_spi_master_2164|cnt[0] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|tx_state.0001 ; 0 ; 6 ; +; - uart_tx:u_uart_pc|tx_shift_reg[1] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|baud_counter[15] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|baud_counter[14] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|baud_counter[13] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|baud_counter[12] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|baud_counter[11] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|baud_counter[10] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|baud_counter[9] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|baud_counter[8] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|baud_counter[6] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|baud_counter[5] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|baud_counter[7] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|baud_counter[4] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|baud_counter[2] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|baud_counter[1] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|baud_counter[0] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|baud_counter[3] ; 0 ; 6 ; +; - start_uart ; 0 ; 6 ; +; - state_top.SEND3 ; 0 ; 6 ; +; - state_top.IDLE ; 0 ; 6 ; +; - uart_tx:u_uart_pc|tx_shift_reg[2] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|tx_bit_counter[0]~1 ; 0 ; 6 ; +; - uart_tx:u_uart_pc|tx_bit_counter[0]~4 ; 0 ; 6 ; +; - uart_tx:u_uart_pc|tx_done ; 0 ; 6 ; +; - state_top.SEND1 ; 0 ; 6 ; +; - uart_tx:u_uart_pc|byte_select.01 ; 0 ; 6 ; +; - uart_tx:u_uart_pc|data_to_send[0]~2 ; 0 ; 6 ; +; - uart_tx:u_uart_pc|tx_shift_reg[3] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|tx_shift_reg[4] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|tx_shift_reg[5] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|tx_shift_reg[6] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|tx_shift_reg[7] ; 0 ; 6 ; +; - uart_tx:u_uart_pc|tx_shift_reg[8] ; 0 ; 6 ; +; sys_clk ; ; ; ++-------------------------------------------------+-------------------+---------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++---------------------------------------------------------------------------------------------+-------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++---------------------------------------------------------------------------------------------+-------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+ +; clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|wire_pll1_clk[0] ; PLL_1 ; 33 ; Clock ; yes ; Global Clock ; GCLK4 ; -- ; +; clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|wire_pll1_clk[1] ; PLL_1 ; 15 ; Clock ; yes ; Global Clock ; GCLK3 ; -- ; +; rst_n ; PIN_J14 ; 77 ; Async. clear, Clock enable ; no ; -- ; -- ; -- ; +; spi_master_2164:u_spi_master_2164|cs_n ; FF_X30_Y10_N11 ; 31 ; Clock ; yes ; Global Clock ; GCLK6 ; -- ; +; start1 ; FF_X25_Y8_N23 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; sys_clk ; PIN_J5 ; 1 ; Clock ; no ; -- ; -- ; -- ; +; uart_tx:u_uart_pc|tx_bit_counter[0]~0 ; LCCOMB_X28_Y6_N10 ; 11 ; Clock enable ; no ; -- ; -- ; -- ; ++---------------------------------------------------------------------------------------------+-------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++---------------------------------------------------------------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++---------------------------------------------------------------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ +; clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|wire_pll1_clk[0] ; PLL_1 ; 33 ; 0 ; Global Clock ; GCLK4 ; -- ; +; clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|wire_pll1_clk[1] ; PLL_1 ; 15 ; 1 ; Global Clock ; GCLK3 ; -- ; +; spi_master_2164:u_spi_master_2164|cs_n ; FF_X30_Y10_N11 ; 31 ; 0 ; Global Clock ; GCLK6 ; -- ; ++---------------------------------------------------------------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ + + ++------------------------------------------------+ +; Routing Usage Summary ; ++-----------------------+------------------------+ +; Routing Resource Type ; Usage ; ++-----------------------+------------------------+ +; Block interconnects ; 134 / 27,275 ( < 1 % ) ; +; C16 interconnects ; 0 / 1,240 ( 0 % ) ; +; C4 interconnects ; 51 / 20,832 ( < 1 % ) ; +; Direct links ; 62 / 27,275 ( < 1 % ) ; +; Global clocks ; 3 / 10 ( 30 % ) ; +; Local interconnects ; 96 / 8,064 ( 1 % ) ; +; R24 interconnects ; 4 / 1,320 ( < 1 % ) ; +; R4 interconnects ; 69 / 28,560 ( < 1 % ) ; ++-----------------------+------------------------+ + + ++----------------------------------------------------------------------------+ +; LAB Logic Elements ; ++---------------------------------------------+------------------------------+ +; Number of Logic Elements (Average = 10.91) ; Number of LABs (Total = 11) ; ++---------------------------------------------+------------------------------+ +; 1 ; 2 ; +; 2 ; 1 ; +; 3 ; 0 ; +; 4 ; 1 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 7 ; ++---------------------------------------------+------------------------------+ + + ++-------------------------------------------------------------------+ +; LAB-wide Signals ; ++------------------------------------+------------------------------+ +; LAB-wide Signals (Average = 2.00) ; Number of LABs (Total = 11) ; ++------------------------------------+------------------------------+ +; 1 Async. clear ; 8 ; +; 1 Clock ; 8 ; +; 1 Clock enable ; 4 ; +; 2 Clocks ; 2 ; ++------------------------------------+------------------------------+ + + ++-----------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++----------------------------------------------+------------------------------+ +; Number of Signals Sourced (Average = 18.00) ; Number of LABs (Total = 11) ; ++----------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 1 ; +; 3 ; 0 ; +; 4 ; 1 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 1 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; +; 17 ; 0 ; +; 18 ; 0 ; +; 19 ; 0 ; +; 20 ; 0 ; +; 21 ; 0 ; +; 22 ; 1 ; +; 23 ; 1 ; +; 24 ; 1 ; +; 25 ; 0 ; +; 26 ; 0 ; +; 27 ; 0 ; +; 28 ; 2 ; +; 29 ; 2 ; ++----------------------------------------------+------------------------------+ + + ++--------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+------------------------------+ +; Number of Signals Sourced Out (Average = 6.82) ; Number of LABs (Total = 11) ; ++-------------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 2 ; +; 2 ; 1 ; +; 3 ; 1 ; +; 4 ; 1 ; +; 5 ; 2 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 2 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 1 ; +; 17 ; 0 ; +; 18 ; 0 ; +; 19 ; 0 ; +; 20 ; 1 ; ++-------------------------------------------------+------------------------------+ + + ++----------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++---------------------------------------------+------------------------------+ +; Number of Distinct Inputs (Average = 9.00) ; Number of LABs (Total = 11) ; ++---------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 1 ; +; 4 ; 2 ; +; 5 ; 2 ; +; 6 ; 1 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 1 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 1 ; +; 16 ; 0 ; +; 17 ; 0 ; +; 18 ; 0 ; +; 19 ; 0 ; +; 20 ; 1 ; +; 21 ; 0 ; +; 22 ; 0 ; +; 23 ; 0 ; +; 24 ; 0 ; +; 25 ; 0 ; +; 26 ; 0 ; +; 27 ; 0 ; +; 28 ; 1 ; ++---------------------------------------------+------------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 30 ; +; Number of I/O Rules Passed ; 12 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 18 ; ++----------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Total Pass ; 13 ; 0 ; 13 ; 0 ; 0 ; 13 ; 13 ; 0 ; 13 ; 13 ; 0 ; 3 ; 0 ; 0 ; 4 ; 0 ; 3 ; 4 ; 0 ; 0 ; 0 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 13 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 0 ; 13 ; 0 ; 13 ; 13 ; 0 ; 0 ; 13 ; 0 ; 0 ; 13 ; 10 ; 13 ; 13 ; 9 ; 13 ; 10 ; 9 ; 13 ; 13 ; 13 ; 10 ; 13 ; 13 ; 13 ; 13 ; 13 ; 0 ; 13 ; 13 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; miso ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; mosi ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; cs_n ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; sclk ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; MOSI_ESP32 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; cs_ESP32 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; sclk_ESP32 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; tx ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; test_flag_led ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; convert_flag_led ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; test_flag ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; rst_n ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; sys_clk ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ + + ++-------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Internal Configuration ; +; Enable Error Detection CRC_ERROR pin ; Off ; +; Enable open drain on CRC_ERROR pin ; Off ; +; Enable nCONFIG, nSTATUS, and CONF_DONE pins ; On ; +; Enable JTAG pin sharing ; Off ; +; Enable nCE pin ; Off ; +; Enable CONFIG_SEL pin ; On ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; Data[0] ; Unreserved ; +; Data[1]/ASDO ; Unreserved ; +; FLASH_nCE/nCSO ; Unreserved ; +; DCLK ; Unreserved ; ++------------------------------------------------------------------+------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 C ; +; High Junction Temperature ; 85 C ; ++---------------------------+--------+ + + ++------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing Summary ; ++-----------------+----------------------+-------------------+ +; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; ++-----------------+----------------------+-------------------+ +Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. +This will disable optimization of problematic paths and expose them for further analysis using the Timing Analyzer. + + ++-------------------------------------------------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing Details ; ++------------------------------------------+----------------------------------------+-------------------+ +; Source Register ; Destination Register ; Delay Added in ns ; ++------------------------------------------+----------------------------------------+-------------------+ +; uart_tx:u_uart_pc|tx_done ; start_uart ; 0.170 ; +; uart_tx:u_uart_pc|data_to_send[0] ; uart_tx:u_uart_pc|tx_shift_reg[1] ; 0.094 ; +; uart_tx:u_uart_pc|tx_state.0001 ; uart_tx:u_uart_pc|tx_shift_reg[8] ; 0.094 ; +; state_top.IDLE ; start_uart ; 0.066 ; +; spi_master_2164:u_spi_master_2164|cnt[0] ; spi_master_2164:u_spi_master_2164|sclk ; 0.064 ; ++------------------------------------------+----------------------------------------+-------------------+ +Note: This table only shows the top 5 path(s) that have the largest delay added for hold. + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Info (20032): Parallel compilation is enabled and will use up to 4 processors +Info (119006): Selected device 10M08SAM153C8G for design "intan_m10" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (15535): Implemented PLL "clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|pll1" as MAX 10 PLL type File: E:/FPGA/20240726/uart_tx_restored/db/clk_gen_altpll.v Line: 44 + Info (15099): Implementing clock multiplication of 6, clock division of 625, and phase shift of 0 degrees (0 ps) for clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|wire_pll1_clk[0] port File: E:/FPGA/20240726/uart_tx_restored/db/clk_gen_altpll.v Line: 44 + Info (15099): Implementing clock multiplication of 12, clock division of 625, and phase shift of 0 degrees (0 ps) for clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|wire_pll1_clk[1] port File: E:/FPGA/20240726/uart_tx_restored/db/clk_gen_altpll.v Line: 44 +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Critical Warning (16562): Review the Power Analyzer report file (.pow.rpt) to ensure your design is within the maximum power utilization limit of the single power-supply target device and to avoid functional failures. +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info (176445): Device 10M08SAM153C8GES is compatible + Info (176445): Device 10M04SAM153C8G is compatible +Info (169124): Fitter converted 8 user pins into dedicated programming pins + Info (169125): Pin ~ALTERA_TMS~ is reserved at location G1 + Info (169125): Pin ~ALTERA_TCK~ is reserved at location J1 + Info (169125): Pin ~ALTERA_TDI~ is reserved at location H5 + Info (169125): Pin ~ALTERA_TDO~ is reserved at location H4 + Info (169125): Pin ~ALTERA_CONFIG_SEL~ is reserved at location D8 + Info (169125): Pin ~ALTERA_nCONFIG~ is reserved at location E8 + Info (169125): Pin ~ALTERA_nSTATUS~ is reserved at location D6 + Info (169125): Pin ~ALTERA_CONF_DONE~ is reserved at location E6 +Info (169141): DATA[0] dual-purpose pin not reserved +Info (12825): Data[1]/ASDO dual-purpose pin not reserved +Info (12825): nCSO dual-purpose pin not reserved +Info (12825): DCLK dual-purpose pin not reserved +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Critical Warning (332012): Synopsys Design Constraints File file not found: 'intan_m10.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained generated clocks found in the design +Info (332144): No user constrained base clocks found in the design +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (176353): Automatically promoted node clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|wire_pll1_clk[0] (placed in counter C1 of PLL_1) File: E:/FPGA/20240726/uart_tx_restored/db/clk_gen_altpll.v Line: 78 + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4 +Info (176353): Automatically promoted node clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|wire_pll1_clk[1] (placed in counter C3 of PLL_1) File: E:/FPGA/20240726/uart_tx_restored/db/clk_gen_altpll.v Line: 78 + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3 +Info (176353): Automatically promoted node spi_master_2164:u_spi_master_2164|cs_n File: E:/FPGA/20240726/uart_tx_restored/spi_master_2164.v Line: 11 + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock + Info (176356): Following destination nodes may be non-global or may not use global or regional clocks + Info (176357): Destination node cs_n~output File: E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v Line: 9 +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Warning (15705): Ignored locations or region assignments to the following nodes + Warning (15706): Node "UART_tx" is assigned to location or region, but does not exist in design +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 +Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X21_Y0 to location X31_Y12 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped +Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 +Info (11888): Total time spent on timing analysis during the Fitter is 0.21 seconds. +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01 +Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. +Warning (169177): 4 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing MAX 10 Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems. + Info (169178): Pin miso uses I/O standard 3.3-V LVCMOS at R3 File: E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v Line: 7 + Info (169178): Pin test_flag uses I/O standard 3.3-V LVCMOS at J12 File: E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v Line: 4 + Info (169178): Pin rst_n uses I/O standard 3.3-V LVCMOS at J14 File: E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v Line: 3 + Info (169178): Pin sys_clk uses I/O standard 3.3-V LVCMOS at J5 File: E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v Line: 2 +Info (144001): Generated suppressed messages file E:/FPGA/20240726/uart_tx_restored/output_files/intan_m10.fit.smsg +Info: Quartus Prime Fitter was successful. 0 errors, 8 warnings + Info: Peak virtual memory: 5534 megabytes + Info: Processing ended: Sat Dec 6 16:45:17 2025 + Info: Elapsed time: 00:00:05 + Info: Total CPU time (on all processors): 00:00:06 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in E:/FPGA/20240726/uart_tx_restored/output_files/intan_m10.fit.smsg. + + diff --git a/puart2/uart_tx_restored/output_files/intan_m10.fit.smsg b/puart2/uart_tx_restored/output_files/intan_m10.fit.smsg new file mode 100644 index 0000000..7121cbb --- /dev/null +++ b/puart2/uart_tx_restored/output_files/intan_m10.fit.smsg @@ -0,0 +1,8 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/puart2/uart_tx_restored/output_files/intan_m10.fit.summary b/puart2/uart_tx_restored/output_files/intan_m10.fit.summary new file mode 100644 index 0000000..9c0460d --- /dev/null +++ b/puart2/uart_tx_restored/output_files/intan_m10.fit.summary @@ -0,0 +1,18 @@ +Fitter Status : Successful - Sat Dec 6 16:45:17 2025 +Quartus Prime Version : 23.1std.1 Build 993 05/14/2024 SC Lite Edition +Revision Name : intan_m10 +Top-level Entity Name : ddr_ctrl +Family : MAX 10 +Device : 10M08SAM153C8G +Timing Models : Final +Total logic elements : 120 / 8,064 ( 1 % ) + Total combinational functions : 112 / 8,064 ( 1 % ) + Dedicated logic registers : 79 / 8,064 ( < 1 % ) +Total registers : 79 +Total pins : 13 / 112 ( 12 % ) +Total virtual pins : 0 +Total memory bits : 0 / 387,072 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 48 ( 0 % ) +Total PLLs : 1 / 1 ( 100 % ) +UFM blocks : 0 / 1 ( 0 % ) +ADC blocks : 0 / 1 ( 0 % ) diff --git a/puart2/uart_tx_restored/output_files/intan_m10.flow.rpt b/puart2/uart_tx_restored/output_files/intan_m10.flow.rpt new file mode 100644 index 0000000..28165b4 --- /dev/null +++ b/puart2/uart_tx_restored/output_files/intan_m10.flow.rpt @@ -0,0 +1,137 @@ +Flow report for intan_m10 +Sat Dec 6 16:45:30 2025 +Quartus Prime Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2024 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++-------------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+------------------------------------------------+ +; Flow Status ; Successful - Sat Dec 6 16:45:27 2025 ; +; Quartus Prime Version ; 23.1std.1 Build 993 05/14/2024 SC Lite Edition ; +; Revision Name ; intan_m10 ; +; Top-level Entity Name ; ddr_ctrl ; +; Family ; MAX 10 ; +; Device ; 10M08SAM153C8G ; +; Timing Models ; Final ; +; Total logic elements ; 120 / 8,064 ( 1 % ) ; +; Total combinational functions ; 112 / 8,064 ( 1 % ) ; +; Dedicated logic registers ; 79 / 8,064 ( < 1 % ) ; +; Total registers ; 79 ; +; Total pins ; 13 / 112 ( 12 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 387,072 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 48 ( 0 % ) ; +; Total PLLs ; 1 / 1 ( 100 % ) ; +; UFM blocks ; 0 / 1 ( 0 % ) ; +; ADC blocks ; 0 / 1 ( 0 % ) ; ++------------------------------------+------------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 12/06/2025 16:45:03 ; +; Main task ; Compilation ; +; Revision Name ; intan_m10 ; ++-------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ +; COMPILER_SIGNATURE_ID ; 92384129777849.176501070322148 ; -- ; -- ; -- ; +; FLOW_ENABLE_POWER_ANALYZER ; On ; Off ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; MISC_FILE ; clk_gen_inst.v ; -- ; -- ; -- ; +; MISC_FILE ; clk_gen_bb.v ; -- ; -- ; -- ; +; MISC_FILE ; clk_gen.ppf ; -- ; -- ; -- ; +; NUM_PARALLEL_PROCESSORS ; 4 ; -- ; -- ; -- ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; ddr_ctrl ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; ddr_ctrl ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; ddr_ctrl ; Top ; +; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ; +; POWER_DEFAULT_INPUT_IO_TOGGLE_RATE ; 12.5 % ; 12.5% ; -- ; -- ; +; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; +; TOP_LEVEL_ENTITY ; ddr_ctrl ; intan_m10 ; -- ; -- ; ++-------------------------------------+----------------------------------------+---------------+-------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:09 ; 1.0 ; 4777 MB ; 00:00:21 ; +; Fitter ; 00:00:05 ; 1.1 ; 5534 MB ; 00:00:06 ; +; Assembler ; 00:00:01 ; 1.0 ; 4686 MB ; 00:00:01 ; +; Power Analyzer ; 00:00:02 ; 1.1 ; 4814 MB ; 00:00:01 ; +; Timing Analyzer ; 00:00:02 ; 1.1 ; 4783 MB ; 00:00:02 ; +; Total ; 00:00:19 ; -- ; -- ; 00:00:31 ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++----------------------+------------------+------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++----------------------+------------------+------------+------------+----------------+ +; Analysis & Synthesis ; LAPTOP-DER6L7FD ; Windows 10 ; 10.0 ; x86_64 ; +; Fitter ; LAPTOP-DER6L7FD ; Windows 10 ; 10.0 ; x86_64 ; +; Assembler ; LAPTOP-DER6L7FD ; Windows 10 ; 10.0 ; x86_64 ; +; Power Analyzer ; LAPTOP-DER6L7FD ; Windows 10 ; 10.0 ; x86_64 ; +; Timing Analyzer ; LAPTOP-DER6L7FD ; Windows 10 ; 10.0 ; x86_64 ; ++----------------------+------------------+------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off intan_m10 -c intan_m10 +quartus_fit --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10 +quartus_asm --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10 +quartus_pow --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10 +quartus_sta intan_m10 -c intan_m10 + + + diff --git a/puart2/uart_tx_restored/output_files/intan_m10.jdi b/puart2/uart_tx_restored/output_files/intan_m10.jdi new file mode 100644 index 0000000..6dc386c --- /dev/null +++ b/puart2/uart_tx_restored/output_files/intan_m10.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/puart2/uart_tx_restored/output_files/intan_m10.map.rpt b/puart2/uart_tx_restored/output_files/intan_m10.map.rpt new file mode 100644 index 0000000..5b6e72f --- /dev/null +++ b/puart2/uart_tx_restored/output_files/intan_m10.map.rpt @@ -0,0 +1,1016 @@ +Analysis & Synthesis report for intan_m10 +Sat Dec 6 16:45:11 2025 +Quartus Prime Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. Analysis & Synthesis IP Cores Summary + 9. State Machine - |ddr_ctrl|state_top + 10. State Machine - |ddr_ctrl|uart_tx:u_uart_pc|byte_select + 11. State Machine - |ddr_ctrl|uart_tx:u_uart_pc|tx_state + 12. State Machine - |ddr_ctrl|spi_master_esp32:tranfer|state + 13. Registers Removed During Synthesis + 14. Removed Registers Triggering Further Register Optimizations + 15. General Register Statistics + 16. Inverted Register Statistics + 17. Multiplexer Restructuring Statistics (Restructuring Performed) + 18. Parameter Settings for User Entity Instance: Top-level Entity: |ddr_ctrl + 19. Parameter Settings for User Entity Instance: clk_gen:clk_gen_inst|altpll:altpll_component + 20. Parameter Settings for User Entity Instance: uart_tx:u_uart_pc + 21. altpll Parameter Settings by Entity Instance + 22. Port Connectivity Checks: "spi_master_2164:u_spi_master_2164" + 23. Post-Synthesis Netlist Statistics for Top Partition + 24. Elapsed Time Per Partition + 25. Analysis & Synthesis Messages + 26. Analysis & Synthesis Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2024 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++-------------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+------------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Sat Dec 6 16:45:11 2025 ; +; Quartus Prime Version ; 23.1std.1 Build 993 05/14/2024 SC Lite Edition ; +; Revision Name ; intan_m10 ; +; Top-level Entity Name ; ddr_ctrl ; +; Family ; MAX 10 ; +; Total logic elements ; 139 ; +; Total combinational functions ; 109 ; +; Dedicated logic registers ; 79 ; +; Total registers ; 79 ; +; Total pins ; 13 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 1 ; +; UFM blocks ; 0 ; +; ADC blocks ; 0 ; ++------------------------------------+------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++------------------------------------------------------------------+--------------------+--------------------+ +; Device ; 10M08SAM153C8G ; ; +; Top-level entity name ; ddr_ctrl ; intan_m10 ; +; Family name ; MAX 10 ; Cyclone V ; +; Maximum processors allowed for parallel compilation ; 4 ; ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM Block Balancing ; On ; On ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; ++------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 0.0% ; ++----------------------------+-------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------------+---------+ +; spi_master_2164.v ; yes ; User Verilog HDL File ; E:/FPGA/20240726/uart_tx_restored/spi_master_2164.v ; ; +; ddr_ctrl.v ; yes ; User Verilog HDL File ; E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v ; ; +; clk_gen.v ; yes ; User Wizard-Generated File ; E:/FPGA/20240726/uart_tx_restored/clk_gen.v ; ; +; spi_master_esp32.v ; yes ; User Verilog HDL File ; E:/FPGA/20240726/uart_tx_restored/spi_master_esp32.v ; ; +; intan_m10.v ; yes ; User Verilog HDL File ; E:/FPGA/20240726/uart_tx_restored/intan_m10.v ; ; +; altpll.tdf ; yes ; Megafunction ; f:/quartus_prime_lite/quartus/libraries/megafunctions/altpll.tdf ; ; +; aglobal231.inc ; yes ; Megafunction ; f:/quartus_prime_lite/quartus/libraries/megafunctions/aglobal231.inc ; ; +; stratix_pll.inc ; yes ; Megafunction ; f:/quartus_prime_lite/quartus/libraries/megafunctions/stratix_pll.inc ; ; +; stratixii_pll.inc ; yes ; Megafunction ; f:/quartus_prime_lite/quartus/libraries/megafunctions/stratixii_pll.inc ; ; +; cycloneii_pll.inc ; yes ; Megafunction ; f:/quartus_prime_lite/quartus/libraries/megafunctions/cycloneii_pll.inc ; ; +; db/clk_gen_altpll.v ; yes ; Auto-Generated Megafunction ; E:/FPGA/20240726/uart_tx_restored/db/clk_gen_altpll.v ; ; ++----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------------+---------+ + + ++-----------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+-------------+ +; Resource ; Usage ; ++---------------------------------------------+-------------+ +; Estimated Total logic elements ; 139 ; +; ; ; +; Total combinational functions ; 109 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 57 ; +; -- 3 input functions ; 10 ; +; -- <=2 input functions ; 42 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 88 ; +; -- arithmetic mode ; 21 ; +; ; ; +; Total registers ; 79 ; +; -- Dedicated logic registers ; 79 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 13 ; +; ; ; +; Embedded Multiplier 9-bit elements ; 0 ; +; ; ; +; Total PLLs ; 1 ; +; -- PLLs ; 1 ; +; ; ; +; Maximum fan-out node ; rst_n~input ; +; Maximum fan-out ; 77 ; +; Total fan-out ; 601 ; +; Average fan-out ; 2.80 ; ++---------------------------------------------+-------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++------------------------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+--------------------------------------------------------------------------------------+-----------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ; ++------------------------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+--------------------------------------------------------------------------------------+-----------------+--------------+ +; |ddr_ctrl ; 109 (32) ; 79 (36) ; 0 ; 0 ; 0 ; 0 ; 0 ; 13 ; 0 ; 0 ; |ddr_ctrl ; ddr_ctrl ; work ; +; |clk_gen:clk_gen_inst| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ddr_ctrl|clk_gen:clk_gen_inst ; clk_gen ; work ; +; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ddr_ctrl|clk_gen:clk_gen_inst|altpll:altpll_component ; altpll ; work ; +; |clk_gen_altpll:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ddr_ctrl|clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated ; clk_gen_altpll ; work ; +; |spi_master_2164:u_spi_master_2164| ; 29 (29) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ddr_ctrl|spi_master_2164:u_spi_master_2164 ; spi_master_2164 ; work ; +; |uart_tx:u_uart_pc| ; 48 (48) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ddr_ctrl|uart_tx:u_uart_pc ; uart_tx ; work ; ++------------------------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+--------------------------------------------------------------------------------------+-----------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis IP Cores Summary ; ++--------+--------------+---------+--------------+--------------+--------------------------------+-----------------+ +; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ; ++--------+--------------+---------+--------------+--------------+--------------------------------+-----------------+ +; Altera ; ALTPLL ; 23.1 ; N/A ; N/A ; |ddr_ctrl|clk_gen:clk_gen_inst ; clk_gen.v ; ++--------+--------------+---------+--------------+--------------+--------------------------------+-----------------+ + + +Encoding Type: One-Hot ++----------------------------------------------------------------------------------------+ +; State Machine - |ddr_ctrl|state_top ; ++-----------------+-----------------+-----------------+-----------------+----------------+ +; Name ; state_top.SEND3 ; state_top.SEND2 ; state_top.SEND1 ; state_top.IDLE ; ++-----------------+-----------------+-----------------+-----------------+----------------+ +; state_top.IDLE ; 0 ; 0 ; 0 ; 0 ; +; state_top.SEND1 ; 0 ; 0 ; 1 ; 1 ; +; state_top.SEND2 ; 0 ; 1 ; 0 ; 1 ; +; state_top.SEND3 ; 1 ; 0 ; 0 ; 1 ; ++-----------------+-----------------+-----------------+-----------------+----------------+ + + +Encoding Type: One-Hot ++---------------------------------------------------------+ +; State Machine - |ddr_ctrl|uart_tx:u_uart_pc|byte_select ; ++----------------+----------------------------------------+ +; Name ; byte_select.01 ; ++----------------+----------------------------------------+ +; byte_select.00 ; 0 ; +; byte_select.01 ; 1 ; ++----------------+----------------------------------------+ + + +Encoding Type: One-Hot ++------------------------------------------------------+ +; State Machine - |ddr_ctrl|uart_tx:u_uart_pc|tx_state ; ++---------------+--------------------------------------+ +; Name ; tx_state.0001 ; ++---------------+--------------------------------------+ +; tx_state.0000 ; 0 ; +; tx_state.0001 ; 1 ; ++---------------+--------------------------------------+ + + +Encoding Type: One-Hot ++-----------------------------------------------------------+ +; State Machine - |ddr_ctrl|spi_master_esp32:tranfer|state ; ++----------------+------------+------------+----------------+ +; Name ; state.IDLE ; state.DONE ; state.TRANSFER ; ++----------------+------------+------------+----------------+ +; state.IDLE ; 0 ; 0 ; 0 ; +; state.TRANSFER ; 1 ; 0 ; 1 ; +; state.DONE ; 1 ; 1 ; 0 ; ++----------------+------------+------------+----------------+ + + ++--------------------------------------------------------------------------------------------+ +; Registers Removed During Synthesis ; ++----------------------------------------------+---------------------------------------------+ +; Register name ; Reason for Removal ; ++----------------------------------------------+---------------------------------------------+ +; sent_data[1..15] ; Stuck at GND due to stuck port data_in ; +; sent_data[0] ; Stuck at VCC due to stuck port data_in ; +; uart_tx:u_uart_pc|data_to_send[1..7] ; Stuck at GND due to stuck port data_in ; +; uart_tx:u_uart_pc|tx_shift_reg[9] ; Stuck at VCC due to stuck port data_in ; +; state_top~8 ; Lost fanout ; +; state_top~9 ; Lost fanout ; +; uart_tx:u_uart_pc|byte_select~6 ; Lost fanout ; +; uart_tx:u_uart_pc|tx_state~7 ; Lost fanout ; +; uart_tx:u_uart_pc|tx_state~8 ; Lost fanout ; +; uart_tx:u_uart_pc|tx_state~9 ; Lost fanout ; +; state_top.SEND2 ; Stuck at GND due to stuck port data_in ; +; start2 ; Stuck at GND due to stuck port data_in ; +; spi_master_esp32:tranfer|bit_cnt[0..3] ; Stuck at GND due to stuck port clock_enable ; +; spi_master_esp32:tranfer|shift_reg[13] ; Stuck at GND due to stuck port clock_enable ; +; spi_master_esp32:tranfer|done ; Stuck at GND due to stuck port clock_enable ; +; spi_master_esp32:tranfer|shift_reg[0..12,15] ; Stuck at GND due to stuck port clock_enable ; +; spi_master_esp32:tranfer|cs ; Stuck at VCC due to stuck port clock_enable ; +; spi_master_esp32:tranfer|sclk_reg ; Stuck at GND due to stuck port clock_enable ; +; spi_master_esp32:tranfer|shift_reg[14] ; Stuck at GND due to stuck port clock_enable ; +; spi_master_esp32:tranfer|state.DONE ; Stuck at GND due to stuck port data_in ; +; spi_master_esp32:tranfer|state.TRANSFER ; Stuck at GND due to stuck port data_in ; +; spi_master_esp32:tranfer|state.IDLE ; Stuck at GND due to stuck port data_in ; +; Total Number of Removed Registers = 58 ; ; ++----------------------------------------------+---------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Removed Registers Triggering Further Register Optimizations ; ++-----------------+---------------------------+-----------------------------------------------------------------------------------+ +; Register name ; Reason for Removal ; Registers Removed due to This Register ; ++-----------------+---------------------------+-----------------------------------------------------------------------------------+ +; state_top.SEND2 ; Stuck at GND ; start2, spi_master_esp32:tranfer|bit_cnt[3], spi_master_esp32:tranfer|bit_cnt[2], ; +; ; due to stuck port data_in ; spi_master_esp32:tranfer|bit_cnt[1], spi_master_esp32:tranfer|bit_cnt[0], ; +; ; ; spi_master_esp32:tranfer|done, spi_master_esp32:tranfer|cs, ; +; ; ; spi_master_esp32:tranfer|sclk_reg, spi_master_esp32:tranfer|state.IDLE ; +; sent_data[15] ; Stuck at GND ; uart_tx:u_uart_pc|data_to_send[7], spi_master_esp32:tranfer|shift_reg[15] ; +; ; due to stuck port data_in ; ; +; sent_data[14] ; Stuck at GND ; uart_tx:u_uart_pc|data_to_send[6], spi_master_esp32:tranfer|shift_reg[14] ; +; ; due to stuck port data_in ; ; +; sent_data[13] ; Stuck at GND ; uart_tx:u_uart_pc|data_to_send[5], spi_master_esp32:tranfer|shift_reg[13] ; +; ; due to stuck port data_in ; ; +; sent_data[12] ; Stuck at GND ; uart_tx:u_uart_pc|data_to_send[4], spi_master_esp32:tranfer|shift_reg[12] ; +; ; due to stuck port data_in ; ; +; sent_data[11] ; Stuck at GND ; uart_tx:u_uart_pc|data_to_send[3], spi_master_esp32:tranfer|shift_reg[11] ; +; ; due to stuck port data_in ; ; +; sent_data[10] ; Stuck at GND ; uart_tx:u_uart_pc|data_to_send[2], spi_master_esp32:tranfer|shift_reg[10] ; +; ; due to stuck port data_in ; ; +; sent_data[9] ; Stuck at GND ; uart_tx:u_uart_pc|data_to_send[1], spi_master_esp32:tranfer|shift_reg[9] ; +; ; due to stuck port data_in ; ; +; sent_data[8] ; Stuck at GND ; spi_master_esp32:tranfer|shift_reg[8] ; +; ; due to stuck port data_in ; ; +; sent_data[7] ; Stuck at GND ; spi_master_esp32:tranfer|shift_reg[7] ; +; ; due to stuck port data_in ; ; +; sent_data[6] ; Stuck at GND ; spi_master_esp32:tranfer|shift_reg[6] ; +; ; due to stuck port data_in ; ; +; sent_data[5] ; Stuck at GND ; spi_master_esp32:tranfer|shift_reg[5] ; +; ; due to stuck port data_in ; ; +; sent_data[4] ; Stuck at GND ; spi_master_esp32:tranfer|shift_reg[4] ; +; ; due to stuck port data_in ; ; +; sent_data[3] ; Stuck at GND ; spi_master_esp32:tranfer|shift_reg[3] ; +; ; due to stuck port data_in ; ; +; sent_data[2] ; Stuck at GND ; spi_master_esp32:tranfer|shift_reg[2] ; +; ; due to stuck port data_in ; ; +; sent_data[1] ; Stuck at GND ; spi_master_esp32:tranfer|shift_reg[1] ; +; ; due to stuck port data_in ; ; +; sent_data[0] ; Stuck at VCC ; spi_master_esp32:tranfer|shift_reg[0] ; +; ; due to stuck port data_in ; ; ++-----------------+---------------------------+-----------------------------------------------------------------------------------+ + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 79 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 73 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 13 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++---------------------------------------------------+ +; Inverted Register Statistics ; ++-----------------------------------------+---------+ +; Inverted Register ; Fan out ; ++-----------------------------------------+---------+ +; spi_master_2164:u_spi_master_2164|cs_n ; 32 ; +; uart_tx:u_uart_pc|tx_shift_reg[0] ; 1 ; +; state[0] ; 3 ; +; uart_tx:u_uart_pc|tx_shift_reg[1] ; 1 ; +; uart_tx:u_uart_pc|tx_shift_reg[2] ; 1 ; +; uart_tx:u_uart_pc|tx_shift_reg[3] ; 1 ; +; uart_tx:u_uart_pc|tx_shift_reg[4] ; 1 ; +; uart_tx:u_uart_pc|tx_shift_reg[5] ; 1 ; +; uart_tx:u_uart_pc|tx_shift_reg[6] ; 1 ; +; uart_tx:u_uart_pc|tx_shift_reg[7] ; 1 ; +; uart_tx:u_uart_pc|tx_shift_reg[8] ; 1 ; +; Total number of inverted registers = 11 ; ; ++-----------------------------------------+---------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Restructuring Statistics (Restructuring Performed) ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------+ +; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------+ +; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |ddr_ctrl|uart_tx:u_uart_pc|tx_bit_counter[3] ; +; 3:1 ; 7 bits ; 14 LEs ; 7 LEs ; 7 LEs ; Yes ; |ddr_ctrl|uart_tx:u_uart_pc|tx_shift_reg[6] ; +; 6:1 ; 2 bits ; 8 LEs ; 6 LEs ; 2 LEs ; No ; |ddr_ctrl|Selector5 ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------+ + + ++--------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Top-level Entity: |ddr_ctrl ; ++----------------+-------+-------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-------------------------------------------------+ +; IDLE ; 00 ; Unsigned Binary ; +; SEND1 ; 01 ; Unsigned Binary ; +; SEND2 ; 10 ; Unsigned Binary ; +; SEND3 ; 11 ; Unsigned Binary ; ++----------------+-------+-------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: clk_gen:clk_gen_inst|altpll:altpll_component ; ++-------------------------------+---------------------------+-------------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------------+---------------------------+-------------------------------+ +; OPERATION_MODE ; NORMAL ; Untyped ; +; PLL_TYPE ; AUTO ; Untyped ; +; LPM_HINT ; CBX_MODULE_PREFIX=clk_gen ; Untyped ; +; QUALIFY_CONF_DONE ; OFF ; Untyped ; +; COMPENSATE_CLOCK ; CLK0 ; Untyped ; +; SCAN_CHAIN ; LONG ; Untyped ; +; PRIMARY_CLOCK ; INCLK0 ; Untyped ; +; INCLK0_INPUT_FREQUENCY ; 83333 ; Signed Integer ; +; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ; +; GATE_LOCK_SIGNAL ; NO ; Untyped ; +; GATE_LOCK_COUNTER ; 0 ; Untyped ; +; LOCK_HIGH ; 1 ; Untyped ; +; LOCK_LOW ; 1 ; Untyped ; +; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ; +; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ; +; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ; +; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ; +; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ; +; SKIP_VCO ; OFF ; Untyped ; +; SWITCH_OVER_COUNTER ; 0 ; Untyped ; +; SWITCH_OVER_TYPE ; AUTO ; Untyped ; +; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ; +; BANDWIDTH ; 0 ; Untyped ; +; BANDWIDTH_TYPE ; AUTO ; Untyped ; +; SPREAD_FREQUENCY ; 0 ; Untyped ; +; DOWN_SPREAD ; 0 ; Untyped ; +; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ; +; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ; +; CLK9_MULTIPLY_BY ; 0 ; Untyped ; +; CLK8_MULTIPLY_BY ; 0 ; Untyped ; +; CLK7_MULTIPLY_BY ; 0 ; Untyped ; +; CLK6_MULTIPLY_BY ; 0 ; Untyped ; +; CLK5_MULTIPLY_BY ; 1 ; Untyped ; +; CLK4_MULTIPLY_BY ; 1 ; Untyped ; +; CLK3_MULTIPLY_BY ; 1 ; Untyped ; +; CLK2_MULTIPLY_BY ; 1 ; Untyped ; +; CLK1_MULTIPLY_BY ; 12 ; Signed Integer ; +; CLK0_MULTIPLY_BY ; 6 ; Signed Integer ; +; CLK9_DIVIDE_BY ; 0 ; Untyped ; +; CLK8_DIVIDE_BY ; 0 ; Untyped ; +; CLK7_DIVIDE_BY ; 0 ; Untyped ; +; CLK6_DIVIDE_BY ; 0 ; Untyped ; +; CLK5_DIVIDE_BY ; 1 ; Untyped ; +; CLK4_DIVIDE_BY ; 1 ; Untyped ; +; CLK3_DIVIDE_BY ; 1 ; Untyped ; +; CLK2_DIVIDE_BY ; 1 ; Untyped ; +; CLK1_DIVIDE_BY ; 625 ; Signed Integer ; +; CLK0_DIVIDE_BY ; 625 ; Signed Integer ; +; CLK9_PHASE_SHIFT ; 0 ; Untyped ; +; CLK8_PHASE_SHIFT ; 0 ; Untyped ; +; CLK7_PHASE_SHIFT ; 0 ; Untyped ; +; CLK6_PHASE_SHIFT ; 0 ; Untyped ; +; CLK5_PHASE_SHIFT ; 0 ; Untyped ; +; CLK4_PHASE_SHIFT ; 0 ; Untyped ; +; CLK3_PHASE_SHIFT ; 0 ; Untyped ; +; CLK2_PHASE_SHIFT ; 0 ; Untyped ; +; CLK1_PHASE_SHIFT ; 0 ; Untyped ; +; CLK0_PHASE_SHIFT ; 0 ; Untyped ; +; CLK5_TIME_DELAY ; 0 ; Untyped ; +; CLK4_TIME_DELAY ; 0 ; Untyped ; +; CLK3_TIME_DELAY ; 0 ; Untyped ; +; CLK2_TIME_DELAY ; 0 ; Untyped ; +; CLK1_TIME_DELAY ; 0 ; Untyped ; +; CLK0_TIME_DELAY ; 0 ; Untyped ; +; CLK9_DUTY_CYCLE ; 50 ; Untyped ; +; CLK8_DUTY_CYCLE ; 50 ; Untyped ; +; CLK7_DUTY_CYCLE ; 50 ; Untyped ; +; CLK6_DUTY_CYCLE ; 50 ; Untyped ; +; CLK5_DUTY_CYCLE ; 50 ; Untyped ; +; CLK4_DUTY_CYCLE ; 50 ; Untyped ; +; CLK3_DUTY_CYCLE ; 50 ; Untyped ; +; CLK2_DUTY_CYCLE ; 50 ; Untyped ; +; CLK1_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; LOCK_WINDOW_UI ; 0.05 ; Untyped ; +; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ; +; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ; +; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ; +; DPA_MULTIPLY_BY ; 0 ; Untyped ; +; DPA_DIVIDE_BY ; 1 ; Untyped ; +; DPA_DIVIDER ; 0 ; Untyped ; +; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK3_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK2_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK1_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK0_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ; +; VCO_MULTIPLY_BY ; 0 ; Untyped ; +; VCO_DIVIDE_BY ; 0 ; Untyped ; +; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ; +; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ; +; VCO_MIN ; 0 ; Untyped ; +; VCO_MAX ; 0 ; Untyped ; +; VCO_CENTER ; 0 ; Untyped ; +; PFD_MIN ; 0 ; Untyped ; +; PFD_MAX ; 0 ; Untyped ; +; M_INITIAL ; 0 ; Untyped ; +; M ; 0 ; Untyped ; +; N ; 1 ; Untyped ; +; M2 ; 1 ; Untyped ; +; N2 ; 1 ; Untyped ; +; SS ; 1 ; Untyped ; +; C0_HIGH ; 0 ; Untyped ; +; C1_HIGH ; 0 ; Untyped ; +; C2_HIGH ; 0 ; Untyped ; +; C3_HIGH ; 0 ; Untyped ; +; C4_HIGH ; 0 ; Untyped ; +; C5_HIGH ; 0 ; Untyped ; +; C6_HIGH ; 0 ; Untyped ; +; C7_HIGH ; 0 ; Untyped ; +; C8_HIGH ; 0 ; Untyped ; +; C9_HIGH ; 0 ; Untyped ; +; C0_LOW ; 0 ; Untyped ; +; C1_LOW ; 0 ; Untyped ; +; C2_LOW ; 0 ; Untyped ; +; C3_LOW ; 0 ; Untyped ; +; C4_LOW ; 0 ; Untyped ; +; C5_LOW ; 0 ; Untyped ; +; C6_LOW ; 0 ; Untyped ; +; C7_LOW ; 0 ; Untyped ; +; C8_LOW ; 0 ; Untyped ; +; C9_LOW ; 0 ; Untyped ; +; C0_INITIAL ; 0 ; Untyped ; +; C1_INITIAL ; 0 ; Untyped ; +; C2_INITIAL ; 0 ; Untyped ; +; C3_INITIAL ; 0 ; Untyped ; +; C4_INITIAL ; 0 ; Untyped ; +; C5_INITIAL ; 0 ; Untyped ; +; C6_INITIAL ; 0 ; Untyped ; +; C7_INITIAL ; 0 ; Untyped ; +; C8_INITIAL ; 0 ; Untyped ; +; C9_INITIAL ; 0 ; Untyped ; +; C0_MODE ; BYPASS ; Untyped ; +; C1_MODE ; BYPASS ; Untyped ; +; C2_MODE ; BYPASS ; Untyped ; +; C3_MODE ; BYPASS ; Untyped ; +; C4_MODE ; BYPASS ; Untyped ; +; C5_MODE ; BYPASS ; Untyped ; +; C6_MODE ; BYPASS ; Untyped ; +; C7_MODE ; BYPASS ; Untyped ; +; C8_MODE ; BYPASS ; Untyped ; +; C9_MODE ; BYPASS ; Untyped ; +; C0_PH ; 0 ; Untyped ; +; C1_PH ; 0 ; Untyped ; +; C2_PH ; 0 ; Untyped ; +; C3_PH ; 0 ; Untyped ; +; C4_PH ; 0 ; Untyped ; +; C5_PH ; 0 ; Untyped ; +; C6_PH ; 0 ; Untyped ; +; C7_PH ; 0 ; Untyped ; +; C8_PH ; 0 ; Untyped ; +; C9_PH ; 0 ; Untyped ; +; L0_HIGH ; 1 ; Untyped ; +; L1_HIGH ; 1 ; Untyped ; +; G0_HIGH ; 1 ; Untyped ; +; G1_HIGH ; 1 ; Untyped ; +; G2_HIGH ; 1 ; Untyped ; +; G3_HIGH ; 1 ; Untyped ; +; E0_HIGH ; 1 ; Untyped ; +; E1_HIGH ; 1 ; Untyped ; +; E2_HIGH ; 1 ; Untyped ; +; E3_HIGH ; 1 ; Untyped ; +; L0_LOW ; 1 ; Untyped ; +; L1_LOW ; 1 ; Untyped ; +; G0_LOW ; 1 ; Untyped ; +; G1_LOW ; 1 ; Untyped ; +; G2_LOW ; 1 ; Untyped ; +; G3_LOW ; 1 ; Untyped ; +; E0_LOW ; 1 ; Untyped ; +; E1_LOW ; 1 ; Untyped ; +; E2_LOW ; 1 ; Untyped ; +; E3_LOW ; 1 ; Untyped ; +; L0_INITIAL ; 1 ; Untyped ; +; L1_INITIAL ; 1 ; Untyped ; +; G0_INITIAL ; 1 ; Untyped ; +; G1_INITIAL ; 1 ; Untyped ; +; G2_INITIAL ; 1 ; Untyped ; +; G3_INITIAL ; 1 ; Untyped ; +; E0_INITIAL ; 1 ; Untyped ; +; E1_INITIAL ; 1 ; Untyped ; +; E2_INITIAL ; 1 ; Untyped ; +; E3_INITIAL ; 1 ; Untyped ; +; L0_MODE ; BYPASS ; Untyped ; +; L1_MODE ; BYPASS ; Untyped ; +; G0_MODE ; BYPASS ; Untyped ; +; G1_MODE ; BYPASS ; Untyped ; +; G2_MODE ; BYPASS ; Untyped ; +; G3_MODE ; BYPASS ; Untyped ; +; E0_MODE ; BYPASS ; Untyped ; +; E1_MODE ; BYPASS ; Untyped ; +; E2_MODE ; BYPASS ; Untyped ; +; E3_MODE ; BYPASS ; Untyped ; +; L0_PH ; 0 ; Untyped ; +; L1_PH ; 0 ; Untyped ; +; G0_PH ; 0 ; Untyped ; +; G1_PH ; 0 ; Untyped ; +; G2_PH ; 0 ; Untyped ; +; G3_PH ; 0 ; Untyped ; +; E0_PH ; 0 ; Untyped ; +; E1_PH ; 0 ; Untyped ; +; E2_PH ; 0 ; Untyped ; +; E3_PH ; 0 ; Untyped ; +; M_PH ; 0 ; Untyped ; +; C1_USE_CASC_IN ; OFF ; Untyped ; +; C2_USE_CASC_IN ; OFF ; Untyped ; +; C3_USE_CASC_IN ; OFF ; Untyped ; +; C4_USE_CASC_IN ; OFF ; Untyped ; +; C5_USE_CASC_IN ; OFF ; Untyped ; +; C6_USE_CASC_IN ; OFF ; Untyped ; +; C7_USE_CASC_IN ; OFF ; Untyped ; +; C8_USE_CASC_IN ; OFF ; Untyped ; +; C9_USE_CASC_IN ; OFF ; Untyped ; +; CLK0_COUNTER ; G0 ; Untyped ; +; CLK1_COUNTER ; G0 ; Untyped ; +; CLK2_COUNTER ; G0 ; Untyped ; +; CLK3_COUNTER ; G0 ; Untyped ; +; CLK4_COUNTER ; G0 ; Untyped ; +; CLK5_COUNTER ; G0 ; Untyped ; +; CLK6_COUNTER ; E0 ; Untyped ; +; CLK7_COUNTER ; E1 ; Untyped ; +; CLK8_COUNTER ; E2 ; Untyped ; +; CLK9_COUNTER ; E3 ; Untyped ; +; L0_TIME_DELAY ; 0 ; Untyped ; +; L1_TIME_DELAY ; 0 ; Untyped ; +; G0_TIME_DELAY ; 0 ; Untyped ; +; G1_TIME_DELAY ; 0 ; Untyped ; +; G2_TIME_DELAY ; 0 ; Untyped ; +; G3_TIME_DELAY ; 0 ; Untyped ; +; E0_TIME_DELAY ; 0 ; Untyped ; +; E1_TIME_DELAY ; 0 ; Untyped ; +; E2_TIME_DELAY ; 0 ; Untyped ; +; E3_TIME_DELAY ; 0 ; Untyped ; +; M_TIME_DELAY ; 0 ; Untyped ; +; N_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK3_COUNTER ; E3 ; Untyped ; +; EXTCLK2_COUNTER ; E2 ; Untyped ; +; EXTCLK1_COUNTER ; E1 ; Untyped ; +; EXTCLK0_COUNTER ; E0 ; Untyped ; +; ENABLE0_COUNTER ; L0 ; Untyped ; +; ENABLE1_COUNTER ; L0 ; Untyped ; +; CHARGE_PUMP_CURRENT ; 2 ; Untyped ; +; LOOP_FILTER_R ; 1.000000 ; Untyped ; +; LOOP_FILTER_C ; 5 ; Untyped ; +; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ; +; LOOP_FILTER_R_BITS ; 9999 ; Untyped ; +; LOOP_FILTER_C_BITS ; 9999 ; Untyped ; +; VCO_POST_SCALE ; 0 ; Untyped ; +; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; INTENDED_DEVICE_FAMILY ; MAX 10 ; Untyped ; +; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA2 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ; +; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ; +; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ; +; PORT_CLK0 ; PORT_USED ; Untyped ; +; PORT_CLK1 ; PORT_USED ; Untyped ; +; PORT_CLK2 ; PORT_UNUSED ; Untyped ; +; PORT_CLK3 ; PORT_UNUSED ; Untyped ; +; PORT_CLK4 ; PORT_UNUSED ; Untyped ; +; PORT_CLK5 ; PORT_UNUSED ; Untyped ; +; PORT_CLK6 ; PORT_UNUSED ; Untyped ; +; PORT_CLK7 ; PORT_UNUSED ; Untyped ; +; PORT_CLK8 ; PORT_UNUSED ; Untyped ; +; PORT_CLK9 ; PORT_UNUSED ; Untyped ; +; PORT_SCANDATA ; PORT_UNUSED ; Untyped ; +; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ; +; PORT_SCANDONE ; PORT_UNUSED ; Untyped ; +; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ; +; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ; +; PORT_INCLK1 ; PORT_UNUSED ; Untyped ; +; PORT_INCLK0 ; PORT_USED ; Untyped ; +; PORT_FBIN ; PORT_UNUSED ; Untyped ; +; PORT_PLLENA ; PORT_UNUSED ; Untyped ; +; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ; +; PORT_ARESET ; PORT_UNUSED ; Untyped ; +; PORT_PFDENA ; PORT_UNUSED ; Untyped ; +; PORT_SCANCLK ; PORT_UNUSED ; Untyped ; +; PORT_SCANACLR ; PORT_UNUSED ; Untyped ; +; PORT_SCANREAD ; PORT_UNUSED ; Untyped ; +; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ; +; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_LOCKED ; PORT_UNUSED ; Untyped ; +; PORT_CONFIGUPDATE ; PORT_UNUSED ; Untyped ; +; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ; +; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ; +; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ; +; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ; +; PORT_SCANCLKENA ; PORT_UNUSED ; Untyped ; +; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ; +; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ; +; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ; +; M_TEST_SOURCE ; 5 ; Untyped ; +; C0_TEST_SOURCE ; 5 ; Untyped ; +; C1_TEST_SOURCE ; 5 ; Untyped ; +; C2_TEST_SOURCE ; 5 ; Untyped ; +; C3_TEST_SOURCE ; 5 ; Untyped ; +; C4_TEST_SOURCE ; 5 ; Untyped ; +; C5_TEST_SOURCE ; 5 ; Untyped ; +; C6_TEST_SOURCE ; 5 ; Untyped ; +; C7_TEST_SOURCE ; 5 ; Untyped ; +; C8_TEST_SOURCE ; 5 ; Untyped ; +; C9_TEST_SOURCE ; 5 ; Untyped ; +; CBXI_PARAMETER ; clk_gen_altpll ; Untyped ; +; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ; +; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ; +; WIDTH_CLOCK ; 5 ; Signed Integer ; +; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ; +; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ; +; DEVICE_FAMILY ; MAX 10 ; Untyped ; +; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ; +; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++-------------------------------+---------------------------+-------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: uart_tx:u_uart_pc ; ++----------------+----------+------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+----------+------------------------------------+ +; BAUD_RATE ; 115200 ; Signed Integer ; +; CLOCK_FREQ ; 12000000 ; Signed Integer ; ++----------------+----------+------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------+ +; altpll Parameter Settings by Entity Instance ; ++-------------------------------+----------------------------------------------+ +; Name ; Value ; ++-------------------------------+----------------------------------------------+ +; Number of entity instances ; 1 ; +; Entity Instance ; clk_gen:clk_gen_inst|altpll:altpll_component ; +; -- OPERATION_MODE ; NORMAL ; +; -- PLL_TYPE ; AUTO ; +; -- PRIMARY_CLOCK ; INCLK0 ; +; -- INCLK0_INPUT_FREQUENCY ; 83333 ; +; -- INCLK1_INPUT_FREQUENCY ; 0 ; +; -- VCO_MULTIPLY_BY ; 0 ; +; -- VCO_DIVIDE_BY ; 0 ; ++-------------------------------+----------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "spi_master_2164:u_spi_master_2164" ; ++------+--------+----------+-------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------+--------+----------+-------------------------------------------------------------------------------------+ +; dout ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; done ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; cnt ; Output ; Info ; Explicitly unconnected ; ++------+--------+----------+-------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------+ +; Post-Synthesis Netlist Statistics for Top Partition ; ++-----------------------+-----------------------------+ +; Type ; Count ; ++-----------------------+-----------------------------+ +; boundary_port ; 13 ; +; cycloneiii_ff ; 79 ; +; CLR ; 61 ; +; ENA ; 1 ; +; ENA CLR ; 12 ; +; plain ; 5 ; +; cycloneiii_lcell_comb ; 114 ; +; arith ; 21 ; +; 2 data inputs ; 21 ; +; normal ; 93 ; +; 0 data inputs ; 2 ; +; 1 data inputs ; 7 ; +; 2 data inputs ; 17 ; +; 3 data inputs ; 10 ; +; 4 data inputs ; 57 ; +; cycloneiii_pll ; 1 ; +; ; ; +; Max LUT depth ; 7.00 ; +; Average LUT depth ; 3.82 ; ++-----------------------+-----------------------------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:00 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Analysis & Synthesis + Info: Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition + Info: Processing started: Sat Dec 6 16:45:02 2025 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off intan_m10 -c intan_m10 +Info (20032): Parallel compilation is enabled and will use up to 4 processors +Info (12021): Found 1 design units, including 1 entities, in source file spi_master_2164.v + Info (12023): Found entity 1: spi_master_2164 File: E:/FPGA/20240726/uart_tx_restored/spi_master_2164.v Line: 1 +Info (12021): Found 1 design units, including 1 entities, in source file ddr_ctrl.v + Info (12023): Found entity 1: ddr_ctrl File: E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v Line: 1 +Info (12021): Found 1 design units, including 1 entities, in source file clk_gen.v + Info (12023): Found entity 1: clk_gen File: E:/FPGA/20240726/uart_tx_restored/clk_gen.v Line: 40 +Info (12021): Found 1 design units, including 1 entities, in source file spi_master_esp32.v + Info (12023): Found entity 1: spi_master_esp32 File: E:/FPGA/20240726/uart_tx_restored/spi_master_esp32.v Line: 1 +Info (12021): Found 1 design units, including 1 entities, in source file intan_m10.v + Info (12023): Found entity 1: uart_tx File: E:/FPGA/20240726/uart_tx_restored/intan_m10.v Line: 1 +Info (12127): Elaborating entity "ddr_ctrl" for the top level hierarchy +Warning (10036): Verilog HDL or VHDL warning at ddr_ctrl.v(71): object "received_data" assigned a value but never read File: E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v Line: 71 +Warning (10763): Verilog HDL warning at ddr_ctrl.v(153): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness File: E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v Line: 153 +Warning (10208): Verilog HDL Case Statement warning at ddr_ctrl.v(153): honored full_case synthesis attribute - differences between design synthesis and simulation may occur File: E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v Line: 153 +Info (12128): Elaborating entity "clk_gen" for hierarchy "clk_gen:clk_gen_inst" File: E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v Line: 204 +Info (12128): Elaborating entity "altpll" for hierarchy "clk_gen:clk_gen_inst|altpll:altpll_component" File: E:/FPGA/20240726/uart_tx_restored/clk_gen.v Line: 95 +Info (12130): Elaborated megafunction instantiation "clk_gen:clk_gen_inst|altpll:altpll_component" File: E:/FPGA/20240726/uart_tx_restored/clk_gen.v Line: 95 +Info (12133): Instantiated megafunction "clk_gen:clk_gen_inst|altpll:altpll_component" with the following parameter: File: E:/FPGA/20240726/uart_tx_restored/clk_gen.v Line: 95 + Info (12134): Parameter "bandwidth_type" = "AUTO" + Info (12134): Parameter "clk0_divide_by" = "625" + Info (12134): Parameter "clk0_duty_cycle" = "50" + Info (12134): Parameter "clk0_multiply_by" = "6" + Info (12134): Parameter "clk0_phase_shift" = "0" + Info (12134): Parameter "clk1_divide_by" = "625" + Info (12134): Parameter "clk1_duty_cycle" = "50" + Info (12134): Parameter "clk1_multiply_by" = "12" + Info (12134): Parameter "clk1_phase_shift" = "0" + Info (12134): Parameter "compensate_clock" = "CLK0" + Info (12134): Parameter "inclk0_input_frequency" = "83333" + Info (12134): Parameter "intended_device_family" = "MAX 10" + Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=clk_gen" + Info (12134): Parameter "lpm_type" = "altpll" + Info (12134): Parameter "operation_mode" = "NORMAL" + Info (12134): Parameter "pll_type" = "AUTO" + Info (12134): Parameter "port_activeclock" = "PORT_UNUSED" + Info (12134): Parameter "port_areset" = "PORT_UNUSED" + Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED" + Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED" + Info (12134): Parameter "port_clkloss" = "PORT_UNUSED" + Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED" + Info (12134): Parameter "port_configupdate" = "PORT_UNUSED" + Info (12134): Parameter "port_fbin" = "PORT_UNUSED" + Info (12134): Parameter "port_inclk0" = "PORT_USED" + Info (12134): Parameter "port_inclk1" = "PORT_UNUSED" + Info (12134): Parameter "port_locked" = "PORT_UNUSED" + Info (12134): Parameter "port_pfdena" = "PORT_UNUSED" + Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED" + Info (12134): Parameter "port_phasedone" = "PORT_UNUSED" + Info (12134): Parameter "port_phasestep" = "PORT_UNUSED" + Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED" + Info (12134): Parameter "port_pllena" = "PORT_UNUSED" + Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED" + Info (12134): Parameter "port_scanclk" = "PORT_UNUSED" + Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED" + Info (12134): Parameter "port_scandata" = "PORT_UNUSED" + Info (12134): Parameter "port_scandataout" = "PORT_UNUSED" + Info (12134): Parameter "port_scandone" = "PORT_UNUSED" + Info (12134): Parameter "port_scanread" = "PORT_UNUSED" + Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED" + Info (12134): Parameter "port_clk0" = "PORT_USED" + Info (12134): Parameter "port_clk1" = "PORT_USED" + Info (12134): Parameter "port_clk2" = "PORT_UNUSED" + Info (12134): Parameter "port_clk3" = "PORT_UNUSED" + Info (12134): Parameter "port_clk4" = "PORT_UNUSED" + Info (12134): Parameter "port_clk5" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena0" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena1" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena2" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena3" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena4" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena5" = "PORT_UNUSED" + Info (12134): Parameter "port_extclk0" = "PORT_UNUSED" + Info (12134): Parameter "port_extclk1" = "PORT_UNUSED" + Info (12134): Parameter "port_extclk2" = "PORT_UNUSED" + Info (12134): Parameter "port_extclk3" = "PORT_UNUSED" + Info (12134): Parameter "width_clock" = "5" +Info (12021): Found 1 design units, including 1 entities, in source file db/clk_gen_altpll.v + Info (12023): Found entity 1: clk_gen_altpll File: E:/FPGA/20240726/uart_tx_restored/db/clk_gen_altpll.v Line: 30 +Info (12128): Elaborating entity "clk_gen_altpll" for hierarchy "clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated" File: f:/quartus_prime_lite/quartus/libraries/megafunctions/altpll.tdf Line: 898 +Info (12128): Elaborating entity "spi_master_2164" for hierarchy "spi_master_2164:u_spi_master_2164" File: E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v Line: 221 +Info (12128): Elaborating entity "spi_master_esp32" for hierarchy "spi_master_esp32:tranfer" File: E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v Line: 234 +Warning (10230): Verilog HDL assignment warning at spi_master_esp32.v(49): truncated value with size 32 to match size of target (4) File: E:/FPGA/20240726/uart_tx_restored/spi_master_esp32.v Line: 49 +Info (12128): Elaborating entity "uart_tx" for hierarchy "uart_tx:u_uart_pc" File: E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v Line: 243 +Warning (10230): Verilog HDL assignment warning at intan_m10.v(33): truncated value with size 32 to match size of target (16) File: E:/FPGA/20240726/uart_tx_restored/intan_m10.v Line: 33 +Warning (10230): Verilog HDL assignment warning at intan_m10.v(74): truncated value with size 32 to match size of target (4) File: E:/FPGA/20240726/uart_tx_restored/intan_m10.v Line: 74 +Info (13000): Registers with preset signals will power-up high File: E:/FPGA/20240726/uart_tx_restored/spi_master_2164.v Line: 11 +Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back +Warning (13024): Output pins are stuck at VCC or GND + Warning (13410): Pin "MOSI_ESP32" is stuck at GND File: E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v Line: 12 + Warning (13410): Pin "cs_ESP32" is stuck at VCC File: E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v Line: 13 + Warning (13410): Pin "sclk_ESP32" is stuck at GND File: E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v Line: 14 +Info (286030): Timing-Driven Synthesis is running +Info (17049): 6 registers lost all their fanouts during netlist optimizations. +Info (144001): Generated suppressed messages file E:/FPGA/20240726/uart_tx_restored/output_files/intan_m10.map.smsg +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL +Warning (21074): Design contains 1 input pin(s) that do not drive logic + Warning (15610): No output dependent on input pin "miso" File: E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v Line: 7 +Info (21057): Implemented 154 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 4 input pins + Info (21059): Implemented 9 output pins + Info (21061): Implemented 140 logic cells + Info (21065): Implemented 1 PLLs +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings + Info: Peak virtual memory: 4777 megabytes + Info: Processing ended: Sat Dec 6 16:45:11 2025 + Info: Elapsed time: 00:00:09 + Info: Total CPU time (on all processors): 00:00:21 + + ++------------------------------------------+ +; Analysis & Synthesis Suppressed Messages ; ++------------------------------------------+ +The suppressed messages can be found in E:/FPGA/20240726/uart_tx_restored/output_files/intan_m10.map.smsg. + + diff --git a/puart2/uart_tx_restored/output_files/intan_m10.map.smsg b/puart2/uart_tx_restored/output_files/intan_m10.map.smsg new file mode 100644 index 0000000..245afa4 --- /dev/null +++ b/puart2/uart_tx_restored/output_files/intan_m10.map.smsg @@ -0,0 +1,2 @@ +Warning (10268): Verilog HDL information at ddr_ctrl.v(151): always construct contains both blocking and non-blocking assignments File: E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v Line: 151 +Info (10281): Verilog HDL Declaration information at spi_master_esp32.v(6): object "done" differs only in case from object "DONE" in the same scope File: E:/FPGA/20240726/uart_tx_restored/spi_master_esp32.v Line: 6 diff --git a/puart2/uart_tx_restored/output_files/intan_m10.map.summary b/puart2/uart_tx_restored/output_files/intan_m10.map.summary new file mode 100644 index 0000000..a9fef96 --- /dev/null +++ b/puart2/uart_tx_restored/output_files/intan_m10.map.summary @@ -0,0 +1,16 @@ +Analysis & Synthesis Status : Successful - Sat Dec 6 16:45:11 2025 +Quartus Prime Version : 23.1std.1 Build 993 05/14/2024 SC Lite Edition +Revision Name : intan_m10 +Top-level Entity Name : ddr_ctrl +Family : MAX 10 +Total logic elements : 139 + Total combinational functions : 109 + Dedicated logic registers : 79 +Total registers : 79 +Total pins : 13 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 1 +UFM blocks : 0 +ADC blocks : 0 diff --git a/puart2/uart_tx_restored/output_files/intan_m10.pin b/puart2/uart_tx_restored/output_files/intan_m10.pin new file mode 100644 index 0000000..e4101f3 --- /dev/null +++ b/puart2/uart_tx_restored/output_files/intan_m10.pin @@ -0,0 +1,223 @@ + -- Copyright (C) 2024 Intel Corporation. All rights reserved. + -- Your use of Intel Corporation's design tools, logic functions + -- and other software and tools, and any partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Intel Program License + -- Subscription Agreement, the Intel Quartus Prime License Agreement, + -- the Intel FPGA IP License Agreement, or other applicable license + -- agreement, including, without limitation, that your use is for + -- the sole purpose of programming logic devices manufactured by + -- Intel and sold by Intel or its authorized distributors. Please + -- refer to the applicable agreement for further details, at + -- https://fpgasoftware.intel.com/eula. + -- + -- This is a Quartus Prime output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus Prime input file. This file cannot be used + -- to make Quartus Prime pin assignments - for instructions on how to make pin + -- assignments, please see Quartus Prime help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1A: 2.5V + -- Bank 1B: 2.5V + -- Bank 2: 3.3V + -- Bank 3: 3.3V + -- Bank 5: 3.3V + -- Bank 6: 3.3V + -- Bank 8: 2.5V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus Prime Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition +CHIP "intan_m10" ASSIGNED TO AN: 10M08SAM153C8G + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : A1 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 8 : +MOSI_ESP32 : A14 : output : 2.5 V : : 8 : Y +GND : A15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 1A : +GND : B2 : gnd : : : : +VCCA3 : B3 : power : : 3.0V/3.3V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 : +VCCIO8 : B5 : power : : 2.5V : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8 : +VCCIO8 : B9 : power : : 2.5V : 8 : +VCCIO8 : B10 : power : : 2.5V : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 8 : +cs_ESP32 : B13 : output : 2.5 V : : 8 : Y +sclk_ESP32 : B14 : output : 2.5 V : : 8 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1A : +ANAIN1 : D4 : : : : : +GND : D5 : gnd : : : : +~ALTERA_nSTATUS~ / RESERVED_INPUT : D6 : input : 2.5 V Schmitt Trigger : : 8 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 : +~ALTERA_CONFIG_SEL~ / RESERVED_INPUT : D8 : input : 2.5 V : : 8 : N +GND : D9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 6 : +VCCA2 : D14 : power : : 3.0V/3.3V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : : : : 1A : +REFGND : E4 : : : : : +GND : E5 : gnd : : : : +~ALTERA_CONF_DONE~ / RESERVED_INPUT : E6 : input : 2.5 V Schmitt Trigger : : 8 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8 : +~ALTERA_nCONFIG~ / RESERVED_INPUT : E8 : input : 2.5 V Schmitt Trigger : : 8 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 6 : +GND : E12 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 6 : +VCCIO1A : F2 : power : : 2.5V : 1A : +ADC_VREF : F4 : : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 6 : +VCCIO6 : F14 : power : : 3.3V : 6 : +~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : input : 2.5 V Schmitt Trigger : : 1B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : G2 : : : : 1B : +GND : G4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1A : +RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 1B : +VCC_ONE : G8 : power : : 3.0V/3.3V : : +GND : G9 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 6 : +VCCIO6 : G14 : power : : 3.3V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 6 : +VCCIO1B : H2 : power : : 2.5V : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1B : +~ALTERA_TDO~ : H4 : output : 2.5 V : : 1B : N +~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP : H5 : input : 2.5 V Schmitt Trigger : : 1B : N +VCC_ONE : H7 : power : : 3.0V/3.3V : : +GND : H8 : gnd : : : : +VCC_ONE : H9 : power : : 3.0V/3.3V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : H11 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 6 : +GND : H14 : gnd : : : : +~ALTERA_TCK~ / RESERVED_INPUT : J1 : input : 2.5 V Schmitt Trigger : : 1B : N +RESERVED_INPUT_WITH_WEAK_PULLUP : J2 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 2 : +sys_clk : J5 : input : 3.3-V LVCMOS : : 2 : Y +GND : J7 : gnd : : : : +VCC_ONE : J8 : power : : 3.0V/3.3V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : J9 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J11 : : : : 5 : +test_flag : J12 : input : 3.3-V LVCMOS : : 6 : Y +rst_n : J14 : input : 3.3-V LVCMOS : : 5 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1B : +RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K11 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K12 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1B : +VCCIO2 : L2 : power : : 3.3V : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L5 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L6 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L10 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L11 : : : : 5 : +GND : L12 : gnd : : : : +VCCIO5 : L14 : power : : 3.3V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L15 : : : : 5 : +GND : M2 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 3 : +mosi : M5 : output : 3.3-V LVCMOS : : 3 : Y +GND : M6 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M9 : : : : 3 : +GND : M10 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M11 : : : : 3 : +convert_flag_led : M12 : output : 3.3-V LVCMOS : : 5 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : M14 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N1 : : : : 2 : +VCCA1 : N2 : power : : 3.0V/3.3V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N14 : : : : 5 : +test_flag_led : N15 : output : 3.3-V LVCMOS : : 5 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 2 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 2 : +sclk : P3 : output : 3.3-V LVCMOS : : 3 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : P4 : : : : 3 : +VCCIO3 : P5 : power : : 3.3V : 3 : +cs_n : P6 : output : 3.3-V LVCMOS : : 3 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : P7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P8 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P9 : : : : 3 : +VCCIO3 : P10 : power : : 3.3V : 3 : +VCCIO3 : P11 : power : : 3.3V : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P12 : : : : 3 : +VCCA4 : P13 : power : : 3.0V/3.3V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P14 : : : : 3 : +tx : P15 : output : 3.3-V LVCMOS : : 3 : Y +GND : R1 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 : +miso : R3 : input : 3.3-V LVCMOS : : 3 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R13 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R14 : : : : 3 : +GND : R15 : gnd : : : : diff --git a/puart2/uart_tx_restored/output_files/intan_m10.pof b/puart2/uart_tx_restored/output_files/intan_m10.pof new file mode 100644 index 0000000..1b7a733 Binary files /dev/null and b/puart2/uart_tx_restored/output_files/intan_m10.pof differ diff --git a/puart2/uart_tx_restored/output_files/intan_m10.pow.rpt b/puart2/uart_tx_restored/output_files/intan_m10.pow.rpt new file mode 100644 index 0000000..dae9964 --- /dev/null +++ b/puart2/uart_tx_restored/output_files/intan_m10.pow.rpt @@ -0,0 +1,311 @@ +Power Analyzer report for intan_m10 +Sat Dec 6 16:45:27 2025 +Quartus Prime Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Parallel Compilation + 3. Power Analyzer Summary + 4. Power Analyzer Settings + 5. Indeterminate Toggle Rates + 6. Operating Conditions Used + 7. Thermal Power Dissipation by Block + 8. Thermal Power Dissipation by Block Type + 9. Thermal Power Dissipation by Hierarchy + 10. Core Dynamic Thermal Power Dissipation by Clock Domain + 11. Current Drawn from Voltage Supplies Summary + 12. VCCIO Supply Current Drawn by I/O Bank + 13. VCCIO Supply Current Drawn by Voltage + 14. Confidence Metric Details + 15. Signal Activities + 16. Power Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2024 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.09 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 2.9% ; ++----------------------------+-------------+ + + ++-------------------------------------------------------------------------------------------+ +; Power Analyzer Summary ; ++----------------------------------------+--------------------------------------------------+ +; Power Analyzer Status ; Successful - Sat Dec 6 16:45:27 2025 ; +; Quartus Prime Version ; 23.1std.1 Build 993 05/14/2024 SC Lite Edition ; +; Revision Name ; intan_m10 ; +; Top-level Entity Name ; ddr_ctrl ; +; Family ; MAX 10 ; +; Device ; 10M08SAM153C8G ; +; Power Models ; Final ; +; Total Thermal Power Dissipation ; 144.69 mW ; +; Core Dynamic Thermal Power Dissipation ; 0.00 mW ; +; Core Static Thermal Power Dissipation ; 121.20 mW ; +; I/O Thermal Power Dissipation ; 23.49 mW ; +; Power Estimation Confidence ; Low: user provided insufficient toggle rate data ; ++----------------------------------------+--------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------+ +; Power Analyzer Settings ; ++------------------------------------------------------------------+---------------------------------------+---------------+ +; Option ; Setting ; Default Value ; ++------------------------------------------------------------------+---------------------------------------+---------------+ +; Maximum processors allowed for parallel compilation ; 4 ; ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Default Power Input I/O Toggle Rate ; 12.5% ; 12.5% ; +; Preset Cooling Solution ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; ; +; Board thermal model ; None (CONSERVATIVE) ; ; +; Default Power Toggle Rate ; 12.5% ; 12.5% ; +; Use vectorless estimation ; On ; On ; +; Use Input Files ; Off ; Off ; +; Filter Glitches in VCD File Reader ; On ; On ; +; Power Analyzer Report Signal Activity ; Off ; Off ; +; Power Analyzer Report Power Dissipation ; Off ; Off ; +; Device Power Characteristics ; TYPICAL ; TYPICAL ; +; Automatically Compute Junction Temperature ; On ; On ; +; Specified Junction Temperature ; 25 ; 25 ; +; Ambient Temperature ; 25 ; 25 ; +; Use Custom Cooling Solution ; Off ; Off ; +; Board Temperature ; 25 ; 25 ; ++------------------------------------------------------------------+---------------------------------------+---------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------+ +; Indeterminate Toggle Rates ; ++-----------------------------------------------------------------------------------------------------+-----------------------------+ +; Node ; Reason ; ++-----------------------------------------------------------------------------------------------------+-----------------------------+ +; clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|wire_pll1_clk[0] ; No valid clock domain found ; +; clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|wire_pll1_clk[1] ; No valid clock domain found ; +; miso ; No valid clock domain found ; +; test_flag ; No valid clock domain found ; +; rst_n ; No valid clock domain found ; +; sys_clk ; No valid clock domain found ; +; spi_master_2164:u_spi_master_2164|cs_n~clkctrl ; No valid clock domain found ; +; clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|wire_pll1_clk[0]~clkctrl ; No valid clock domain found ; +; clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|wire_pll1_clk[1]~clkctrl ; No valid clock domain found ; ++-----------------------------------------------------------------------------------------------------+-----------------------------+ + + ++--------------------------------------------------------------------------+ +; Operating Conditions Used ; ++---------------------------------------------+----------------------------+ +; Setting ; Value ; ++---------------------------------------------+----------------------------+ +; Device power characteristics ; Typical ; +; ; ; +; Voltages ; ; +; VCCA ; 3.00 V ; +; VCC_ONE ; 3.00 V ; +; 3.3-V LVCMOS I/O Standard ; 3.3 V ; +; 2.5 V I/O Standard ; 2.5 V ; +; 2.5 V Schmitt Trigger I/O Standard ; 2.5 V ; +; ; ; +; Auto computed junction temperature ; 28.7 degrees Celsius ; +; Ambient temperature ; 25.0 degrees Celsius ; +; Junction-to-Case thermal resistance ; 11.00 degrees Celsius/Watt ; +; Case-to-Heat Sink thermal resistance ; 0.10 degrees Celsius/Watt ; +; Heat Sink-to-Ambient thermal resistance ; 14.30 degrees Celsius/Watt ; +; ; ; +; Board model used ; None ; ++---------------------------------------------+----------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------+ +; Thermal Power Dissipation by Block ; ++------------+------------+---------------------+-----------------------------+--------------------------------+-------------------------------+ +; Block Name ; Block Type ; Total Thermal Power ; Block Thermal Dynamic Power ; Block Thermal Static Power (1) ; Routing Thermal Dynamic Power ; ++------------+------------+---------------------+-----------------------------+--------------------------------+-------------------------------+ +(1) The "Thermal Power Dissipation by Block" Table has been hidden. To show this table, please select the "Write power dissipation by block to report file" option under "PowerPlay Power Analyzer Settings". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Thermal Power Dissipation by Block Type ; ++---------------------+-----------------------------------+-----------------------------+--------------------------------+-------------------------------+-----------------------------------------------------------+ +; Block Type ; Total Thermal Power by Block Type ; Block Thermal Dynamic Power ; Block Thermal Static Power (1) ; Routing Thermal Dynamic Power ; Block Average Toggle Rate (millions of transitions / sec) ; ++---------------------+-----------------------------------+-----------------------------+--------------------------------+-------------------------------+-----------------------------------------------------------+ +; Combinational cell ; 0.00 mW ; 0.00 mW ; -- ; 0.00 mW ; 0.000 ; +; Clock control block ; 0.00 mW ; 0.00 mW ; -- ; 0.00 mW ; 0.000 ; +; Register cell ; 0.00 mW ; 0.00 mW ; -- ; 0.00 mW ; 0.000 ; +; I/O ; 0.50 mW ; 0.00 mW ; 0.50 mW ; 0.00 mW ; 0.000 ; +; Voltage Regulator ; 0.76 mW ; 0.00 mW ; 0.76 mW ; -- ; -- ; ++---------------------+-----------------------------------+-----------------------------+--------------------------------+-------------------------------+-----------------------------------------------------------+ +(1) The "Block Thermal Static Power" for all block types except Pins and the Voltage Regulator, if one exists, is part of the "Core Static Thermal Power Dissipation" value found on the PowerPlay Power Analyzer-->Summary report panel. The "Core Static Thermal Power Dissipation" also contains the thermal static power dissipated by the routing. + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Thermal Power Dissipation by Hierarchy ; ++--------------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+--------------------------------------------------------------------------------------+ +; Compilation Hierarchy Node ; Total Thermal Power by Hierarchy (1) ; Block Thermal Dynamic Power (1) ; Block Thermal Static Power (1)(2) ; Routing Thermal Dynamic Power (1) ; Full Hierarchy Name ; ++--------------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+--------------------------------------------------------------------------------------+ +; |ddr_ctrl ; 1.26 mW (1.26 mW) ; 0.00 mW (0.00 mW) ; 1.26 mW (1.26 mW) ; 0.00 mW (0.00 mW) ; |ddr_ctrl ; +; |hard_block:auto_generated_inst ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |ddr_ctrl|hard_block:auto_generated_inst ; +; |clk_gen:clk_gen_inst ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |ddr_ctrl|clk_gen:clk_gen_inst ; +; |altpll:altpll_component ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |ddr_ctrl|clk_gen:clk_gen_inst|altpll:altpll_component ; +; |clk_gen_altpll:auto_generated ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |ddr_ctrl|clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated ; +; |spi_master_esp32:tranfer ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |ddr_ctrl|spi_master_esp32:tranfer ; +; |spi_master_2164:u_spi_master_2164 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |ddr_ctrl|spi_master_2164:u_spi_master_2164 ; +; |uart_tx:u_uart_pc ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |ddr_ctrl|uart_tx:u_uart_pc ; ++--------------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+--------------------------------------------------------------------------------------+ +(1) Value in parentheses is the power consumed at that level of hierarchy. Value not in parentheses is the power consumed at that level of hierarchy plus the power consumed by all levels of hierarchy below it. + +(2) The "Block Thermal Static Power" for all levels of hierarchy except the top-level hierarchy is part of the "Core Static Thermal Power Dissipation" value found on the PowerPlay Power Analyzer-->Summary report panel. The "Core Static Thermal Power Dissipation" also contains the thermal static power dissipated by the routing. + + ++--------------------------------------------------------------------+ +; Core Dynamic Thermal Power Dissipation by Clock Domain ; ++-----------------+-----------------------+--------------------------+ +; Clock Domain ; Clock Frequency (MHz) ; Total Core Dynamic Power ; ++-----------------+-----------------------+--------------------------+ +; No clock domain ; 0.00 ; 0.00 ; ++-----------------+-----------------------+--------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Current Drawn from Voltage Supplies Summary ; ++----------------+-------------------------+---------------------------+--------------------------+----------------------------------+ +; Voltage Supply ; Total Current Drawn (1) ; Dynamic Current Drawn (1) ; Static Current Drawn (1) ; Minimum Power Supply Current (2) ; ++----------------+-------------------------+---------------------------+--------------------------+----------------------------------+ +; VCCIO ; 7.34 mA ; 0.00 mA ; 7.34 mA ; 7.34 mA ; +; VCCA ; 3.03 mA ; 0.00 mA ; 3.03 mA ; 3.03 mA ; +; VCC_ONE ; 37.37 mA ; 0.00 mA ; 37.37 mA ; 37.37 mA ; ++----------------+-------------------------+---------------------------+--------------------------+----------------------------------+ +(1) Currents reported in columns "Total Current Drawn", "Dynamic Current Drawn", and "Static Current Drawn" are sufficient for user operation of the device. +(2) Currents reported in column "Minimum Power Supply Current" are sufficient for power-up, configuration, and user operation of the device. + + ++-----------------------------------------------------------------------------------------------+ +; VCCIO Supply Current Drawn by I/O Bank ; ++----------+---------------+---------------------+-----------------------+----------------------+ +; I/O Bank ; VCCIO Voltage ; Total Current Drawn ; Dynamic Current Drawn ; Static Current Drawn ; ++----------+---------------+---------------------+-----------------------+----------------------+ +; 1A ; 2.5V ; 0.25 mA ; 0.00 mA ; 0.25 mA ; +; 1B ; 2.5V ; 0.26 mA ; 0.00 mA ; 0.26 mA ; +; 2 ; 3.3V ; 1.62 mA ; 0.00 mA ; 1.62 mA ; +; 3 ; 3.3V ; 1.68 mA ; 0.00 mA ; 1.68 mA ; +; 4 ; -- ; -- ; -- ; -- ; +; 5 ; 3.3V ; 1.65 mA ; 0.00 mA ; 1.65 mA ; +; 6 ; 3.3V ; 1.62 mA ; 0.00 mA ; 1.62 mA ; +; 7 ; -- ; -- ; -- ; -- ; +; 8 ; 2.5V ; 0.27 mA ; 0.00 mA ; 0.27 mA ; ++----------+---------------+---------------------+-----------------------+----------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------+ +; VCCIO Supply Current Drawn by Voltage ; ++---------------+-------------------------+---------------------------+--------------------------+----------------------------------+ +; VCCIO Voltage ; Total Current Drawn (1) ; Dynamic Current Drawn (1) ; Static Current Drawn (1) ; Minimum Power Supply Current (2) ; ++---------------+-------------------------+---------------------------+--------------------------+----------------------------------+ +; 2.5V ; 0.78 mA ; 0.00 mA ; 0.78 mA ; 0.78 mA ; +; 3.3V ; 6.57 mA ; 0.00 mA ; 6.57 mA ; 6.57 mA ; ++---------------+-------------------------+---------------------------+--------------------------+----------------------------------+ +(1) Currents reported in columns "Total Current Drawn", "Dynamic Current Drawn", and "Static Current Drawn" are sufficient for user operation of the device. +(2) Currents reported in column "Minimum Power Supply Current" are sufficient for power-up, configuration, and user operation of the device. + + ++-------------------------------------------------------------------------------------------------------------------------------------------------+ +; Confidence Metric Details ; ++----------------------------------------------------------------------------------------+-------------+------------+-------------+---------------+ +; Data Source ; Total ; Pin ; Registered ; Combinational ; ++----------------------------------------------------------------------------------------+-------------+------------+-------------+---------------+ +; Simulation (from file) ; ; ; ; ; +; -- Number of signals with Toggle Rate from Simulation ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; +; -- Number of signals with Static Probability from Simulation ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; +; ; ; ; ; ; +; Node, entity or clock assignment ; ; ; ; ; +; -- Number of signals with Toggle Rate from Node, entity or clock assignment ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; +; -- Number of signals with Static Probability from Node, entity or clock assignment ; 3 (1.2%) ; 0 (0.0%) ; 0 (0.0%) ; 3 (1.9%) ; +; ; ; ; ; ; +; Vectorless estimation ; ; ; ; ; +; -- Number of signals with Toggle Rate from Vectorless estimation ; 247 (95.4%) ; 11 (52.4%) ; 79 (100.0%) ; 157 (98.7%) ; +; -- Number of signals with Zero toggle rate, from Vectorless estimation ; 21 (8.1%) ; 6 (28.6%) ; 1 (1.3%) ; 14 (8.8%) ; +; -- Number of signals with Static Probability from Vectorless estimation ; 244 (94.2%) ; 11 (52.4%) ; 79 (100.0%) ; 154 (96.9%) ; +; ; ; ; ; ; +; Default assignment ; ; ; ; ; +; -- Number of signals with Toggle Rate from Default assignment ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; +; -- Number of signals with Static Probability from Default assignment ; 12 (4.6%) ; 10 (47.6%) ; 0 (0.0%) ; 2 (1.3%) ; +; ; ; ; ; ; +; Assumed 0 ; ; ; ; ; +; -- Number of signals with Toggle Rate assumed 0 ; 12 (4.6%) ; 10 (47.6%) ; 0 (0.0%) ; 2 (1.3%) ; ++----------------------------------------------------------------------------------------+-------------+------------+-------------+---------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Activities ; ++--------+------+---------------------------------------------+-------------------------+--------------------+--------------------------------+ +; Signal ; Type ; Toggle Rate (millions of transitions / sec) ; Toggle Rate Data Source ; Static Probability ; Static Probability Data Source ; ++--------+------+---------------------------------------------+-------------------------+--------------------+--------------------------------+ +(1) The "Signal Activity" Table has been hidden. To show this table, please select the "Write signal activities to report file" option under "PowerPlay Power Analyzer Settings". + + ++-------------------------+ +; Power Analyzer Messages ; ++-------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Power Analyzer + Info: Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition + Info: Processing started: Sat Dec 6 16:45:25 2025 +Info: Command: quartus_pow --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10 +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'intan_m10.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Warning (332060): Node: sys_clk was determined to be a clock but was found without an associated clock assignment. + Info (13166): Register spi_master_2164:u_spi_master_2164|cnt[0] is being clocked by sys_clk +Warning (332060): Node: spi_master_2164:u_spi_master_2164|cs_n was determined to be a clock but was found without an associated clock assignment. + Info (13166): Register state[7] is being clocked by spi_master_2164:u_spi_master_2164|cs_n +Warning (332068): No clocks defined in design. +Warning (332056): PLL cross checking found inconsistent PLL clock settings: + Warning (332056): Node: clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 83.333 + Warning (332056): Node: clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] was found missing 1 generated clock that corresponds to a base clock with a period of: 83.333 +Info (223000): Starting Vectorless Power Activity Estimation +Warning (222013): Relative toggle rates could not be calculated because no clock domain could be identified for some nodes +Info (223001): Completed Vectorless Power Activity Estimation +Info (218000): Using Advanced I/O Power to simulate I/O buffers with the specified board trace model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (215049): Average toggle rate for this design is 0.000 millions of transitions / sec +Info (215031): Total thermal power estimate for the design is 144.69 mW +Info: Quartus Prime Power Analyzer was successful. 0 errors, 8 warnings + Info: Peak virtual memory: 4814 megabytes + Info: Processing ended: Sat Dec 6 16:45:27 2025 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/puart2/uart_tx_restored/output_files/intan_m10.pow.summary b/puart2/uart_tx_restored/output_files/intan_m10.pow.summary new file mode 100644 index 0000000..db3a8f9 --- /dev/null +++ b/puart2/uart_tx_restored/output_files/intan_m10.pow.summary @@ -0,0 +1,12 @@ +Power Analyzer Status : Successful - Sat Dec 6 16:45:27 2025 +Quartus Prime Version : 23.1std.1 Build 993 05/14/2024 SC Lite Edition +Revision Name : intan_m10 +Top-level Entity Name : ddr_ctrl +Family : MAX 10 +Device : 10M08SAM153C8G +Power Models : Final +Total Thermal Power Dissipation : 144.69 mW +Core Dynamic Thermal Power Dissipation : 0.00 mW +Core Static Thermal Power Dissipation : 121.20 mW +I/O Thermal Power Dissipation : 23.49 mW +Power Estimation Confidence : Low: user provided insufficient toggle rate data diff --git a/puart2/uart_tx_restored/output_files/intan_m10.sld b/puart2/uart_tx_restored/output_files/intan_m10.sld new file mode 100644 index 0000000..f7d3ed7 --- /dev/null +++ b/puart2/uart_tx_restored/output_files/intan_m10.sld @@ -0,0 +1 @@ + diff --git a/puart2/uart_tx_restored/output_files/intan_m10.sof b/puart2/uart_tx_restored/output_files/intan_m10.sof new file mode 100644 index 0000000..43e499b Binary files /dev/null and b/puart2/uart_tx_restored/output_files/intan_m10.sof differ diff --git a/puart2/uart_tx_restored/output_files/intan_m10.sta.rpt b/puart2/uart_tx_restored/output_files/intan_m10.sta.rpt new file mode 100644 index 0000000..2096dce --- /dev/null +++ b/puart2/uart_tx_restored/output_files/intan_m10.sta.rpt @@ -0,0 +1,628 @@ +Timing Analyzer report for intan_m10 +Sat Dec 6 16:45:30 2025 +Quartus Prime Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow 1200mV 85C Model Fmax Summary + 6. Slow 1200mV 85C Model Setup Summary + 7. Slow 1200mV 85C Model Hold Summary + 8. Slow 1200mV 85C Model Recovery Summary + 9. Slow 1200mV 85C Model Removal Summary + 10. Slow 1200mV 85C Model Minimum Pulse Width Summary + 11. Slow 1200mV 85C Model Metastability Summary + 12. Slow 1200mV 0C Model Fmax Summary + 13. Slow 1200mV 0C Model Setup Summary + 14. Slow 1200mV 0C Model Hold Summary + 15. Slow 1200mV 0C Model Recovery Summary + 16. Slow 1200mV 0C Model Removal Summary + 17. Slow 1200mV 0C Model Minimum Pulse Width Summary + 18. Slow 1200mV 0C Model Metastability Summary + 19. Fast 1200mV 0C Model Setup Summary + 20. Fast 1200mV 0C Model Hold Summary + 21. Fast 1200mV 0C Model Recovery Summary + 22. Fast 1200mV 0C Model Removal Summary + 23. Fast 1200mV 0C Model Minimum Pulse Width Summary + 24. Fast 1200mV 0C Model Metastability Summary + 25. Multicorner Timing Analysis Summary + 26. Board Trace Model Assignments + 27. Input Transition Times + 28. Signal Integrity Metrics (Slow 1200mv 0c Model) + 29. Signal Integrity Metrics (Slow 1200mv 85c Model) + 30. Signal Integrity Metrics (Fast 1200mv 0c Model) + 31. Setup Transfers + 32. Hold Transfers + 33. Report TCCS + 34. Report RSKM + 35. Unconstrained Paths Summary + 36. Clock Status Summary + 37. Unconstrained Input Ports + 38. Unconstrained Output Ports + 39. Unconstrained Input Ports + 40. Unconstrained Output Ports + 41. Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2024 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++--------------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++-----------------------+--------------------------------------------------------+ +; Quartus Prime Version ; Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition ; +; Timing Analyzer ; Legacy Timing Analyzer ; +; Revision Name ; intan_m10 ; +; Device Family ; MAX 10 ; +; Device Name ; 10M08SAM153C8G ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++-----------------------+--------------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.07 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 2.3% ; +; Processors 3-4 ; 2.3% ; ++----------------------------+-------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clocks ; ++----------------------------------------------------------+-----------+----------+------------+-------+----------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------+------------------------------------------------------------+--------------------------------------------------------------+ +; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; ++----------------------------------------------------------+-----------+----------+------------+-------+----------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------+------------------------------------------------------------+--------------------------------------------------------------+ +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 8680.520 ; 0.12 MHz ; 0.000 ; 4340.260 ; 50.00 ; 625 ; 6 ; ; ; ; ; false ; sys_clk ; clk_gen_inst|altpll_component|auto_generated|pll1|inclk[0] ; { clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] } ; +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 4340.260 ; 0.23 MHz ; 0.000 ; 2170.130 ; 50.00 ; 625 ; 12 ; ; ; ; ; false ; sys_clk ; clk_gen_inst|altpll_component|auto_generated|pll1|inclk[0] ; { clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] } ; +; spi_master_2164:u_spi_master_2164|cs_n ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { spi_master_2164:u_spi_master_2164|cs_n } ; +; sys_clk ; Base ; 83.333 ; 12.0 MHz ; 0.000 ; 41.666 ; ; ; ; ; ; ; ; ; ; ; { sys_clk } ; ++----------------------------------------------------------+-----------+----------+------------+-------+----------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------+------------------------------------------------------------+--------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++------------+-----------------+----------------------------------------------------------+------------------------------------------------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+----------------------------------------------------------+------------------------------------------------+ +; 174.19 MHz ; 174.19 MHz ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; ; +; 201.37 MHz ; 201.37 MHz ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] ; ; +; 625.0 MHz ; 402.09 MHz ; spi_master_2164:u_spi_master_2164|cs_n ; limit due to minimum period restriction (tmin) ; ++------------+-----------------+----------------------------------------------------------+------------------------------------------------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + ++-------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Setup Summary ; ++----------------------------------------------------------+----------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------------+----------+---------------+ +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] ; -6.111 ; -6.111 ; +; spi_master_2164:u_spi_master_2164|cs_n ; -0.600 ; -7.693 ; +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 4335.838 ; 0.000 ; ++----------------------------------------------------------+----------+---------------+ + + ++----------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Hold Summary ; ++----------------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------------+-------+---------------+ +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.362 ; 0.000 ; +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.362 ; 0.000 ; +; spi_master_2164:u_spi_master_2164|cs_n ; 0.362 ; 0.000 ; ++----------------------------------------------------------+-------+---------------+ + + +------------------------------------------ +; Slow 1200mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1200mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + ++-------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Minimum Pulse Width Summary ; ++----------------------------------------------------------+----------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------------+----------+---------------+ +; spi_master_2164:u_spi_master_2164|cs_n ; -1.487 ; -46.097 ; +; sys_clk ; 41.541 ; 0.000 ; +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] ; 2169.851 ; 0.000 ; +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 4339.991 ; 0.000 ; ++----------------------------------------------------------+----------+---------------+ + + +----------------------------------------------- +; Slow 1200mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + ++------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Fmax Summary ; ++------------+-----------------+----------------------------------------------------------+------------------------------------------------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+----------------------------------------------------------+------------------------------------------------+ +; 184.03 MHz ; 184.03 MHz ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; ; +; 208.99 MHz ; 208.99 MHz ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] ; ; +; 658.76 MHz ; 402.09 MHz ; spi_master_2164:u_spi_master_2164|cs_n ; limit due to minimum period restriction (tmin) ; ++------------+-----------------+----------------------------------------------------------+------------------------------------------------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + ++-------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Setup Summary ; ++----------------------------------------------------------+----------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------------+----------+---------------+ +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] ; -5.633 ; -5.633 ; +; spi_master_2164:u_spi_master_2164|cs_n ; -0.518 ; -5.401 ; +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 4336.023 ; 0.000 ; ++----------------------------------------------------------+----------+---------------+ + + ++----------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Hold Summary ; ++----------------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------------+-------+---------------+ +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.324 ; 0.000 ; +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.324 ; 0.000 ; +; spi_master_2164:u_spi_master_2164|cs_n ; 0.324 ; 0.000 ; ++----------------------------------------------------------+-------+---------------+ + + +----------------------------------------- +; Slow 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + ++-------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Minimum Pulse Width Summary ; ++----------------------------------------------------------+----------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------------+----------+---------------+ +; spi_master_2164:u_spi_master_2164|cs_n ; -1.487 ; -46.097 ; +; sys_clk ; 41.545 ; 0.000 ; +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] ; 2169.828 ; 0.000 ; +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 4340.001 ; 0.000 ; ++----------------------------------------------------------+----------+---------------+ + + +---------------------------------------------- +; Slow 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++-------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Setup Summary ; ++----------------------------------------------------------+----------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------------+----------+---------------+ +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] ; -2.102 ; -2.102 ; +; spi_master_2164:u_spi_master_2164|cs_n ; 0.320 ; 0.000 ; +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 4338.451 ; 0.000 ; ++----------------------------------------------------------+----------+---------------+ + + ++----------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Hold Summary ; ++----------------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------------+-------+---------------+ +; spi_master_2164:u_spi_master_2164|cs_n ; 0.150 ; 0.000 ; +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.152 ; 0.000 ; +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.152 ; 0.000 ; ++----------------------------------------------------------+-------+---------------+ + + +----------------------------------------- +; Fast 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + ++-------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Minimum Pulse Width Summary ; ++----------------------------------------------------------+----------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------------+----------+---------------+ +; spi_master_2164:u_spi_master_2164|cs_n ; -1.000 ; -31.000 ; +; sys_clk ; 41.170 ; 0.000 ; +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] ; 2169.891 ; 0.000 ; +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 4340.042 ; 0.000 ; ++----------------------------------------------------------+----------+---------------+ + + +---------------------------------------------- +; Fast 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++-----------------------------------------------------------+----------+-------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++-----------------------------------------------------------+----------+-------+----------+---------+---------------------+ +; Worst-case Slack ; -6.111 ; 0.150 ; N/A ; N/A ; -1.487 ; +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 4335.838 ; 0.152 ; N/A ; N/A ; 4339.991 ; +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] ; -6.111 ; 0.152 ; N/A ; N/A ; 2169.828 ; +; spi_master_2164:u_spi_master_2164|cs_n ; -0.600 ; 0.150 ; N/A ; N/A ; -1.487 ; +; sys_clk ; N/A ; N/A ; N/A ; N/A ; 41.170 ; +; Design-wide TNS ; -13.804 ; 0.0 ; 0.0 ; 0.0 ; -46.097 ; +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.000 ; N/A ; N/A ; 0.000 ; +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] ; -6.111 ; 0.000 ; N/A ; N/A ; 0.000 ; +; spi_master_2164:u_spi_master_2164|cs_n ; -7.693 ; 0.000 ; N/A ; N/A ; -46.097 ; +; sys_clk ; N/A ; N/A ; N/A ; N/A ; 0.000 ; ++-----------------------------------------------------------+----------+-------+----------+---------+---------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; mosi ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; cs_n ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; sclk ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; MOSI_ESP32 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; cs_ESP32 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; sclk_ESP32 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; tx ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; test_flag_led ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; convert_flag_led ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++---------------------------------------------------------------------------------+ +; Input Transition Times ; ++---------------------+-----------------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++---------------------+-----------------------+-----------------+-----------------+ +; miso ; 3.3-V LVCMOS ; 2640 ps ; 2640 ps ; +; test_flag ; 3.3-V LVCMOS ; 2640 ps ; 2640 ps ; +; rst_n ; 3.3-V LVCMOS ; 2640 ps ; 2640 ps ; +; sys_clk ; 3.3-V LVCMOS ; 2640 ps ; 2640 ps ; +; ~ALTERA_TMS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_TCK~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_TDI~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_CONFIG_SEL~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_nCONFIG~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_nSTATUS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; +; ~ALTERA_CONF_DONE~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; ++---------------------+-----------------------+-----------------+-----------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 0c Model) ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; mosi ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0411 V ; 0.283 V ; 0.209 V ; 9e-10 s ; 1.03e-09 s ; No ; No ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0411 V ; 0.283 V ; 0.209 V ; 9e-10 s ; 1.03e-09 s ; No ; No ; +; cs_n ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0417 V ; 0.287 V ; 0.209 V ; 8.99e-10 s ; 1.03e-09 s ; No ; No ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0417 V ; 0.287 V ; 0.209 V ; 8.99e-10 s ; 1.03e-09 s ; No ; No ; +; sclk ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0463 V ; 0.208 V ; 0.277 V ; 8.5e-10 s ; 8.53e-10 s ; No ; No ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0463 V ; 0.208 V ; 0.277 V ; 8.5e-10 s ; 8.53e-10 s ; No ; No ; +; MOSI_ESP32 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.47e-09 V ; 2.4 V ; -0.0932 V ; 0.135 V ; 0.16 V ; 4.43e-10 s ; 4.36e-10 s ; No ; Yes ; 2.32 V ; 4.47e-09 V ; 2.4 V ; -0.0932 V ; 0.135 V ; 0.16 V ; 4.43e-10 s ; 4.36e-10 s ; No ; Yes ; +; cs_ESP32 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.47e-09 V ; 2.4 V ; -0.0905 V ; 0.135 V ; 0.167 V ; 4.43e-10 s ; 4.36e-10 s ; No ; Yes ; 2.32 V ; 4.47e-09 V ; 2.4 V ; -0.0905 V ; 0.135 V ; 0.167 V ; 4.43e-10 s ; 4.36e-10 s ; No ; Yes ; +; sclk_ESP32 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.47e-09 V ; 2.4 V ; -0.0932 V ; 0.135 V ; 0.16 V ; 4.43e-10 s ; 4.36e-10 s ; No ; Yes ; 2.32 V ; 4.47e-09 V ; 2.4 V ; -0.0932 V ; 0.135 V ; 0.16 V ; 4.43e-10 s ; 4.36e-10 s ; No ; Yes ; +; tx ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0411 V ; 0.283 V ; 0.209 V ; 9e-10 s ; 1.03e-09 s ; No ; No ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0411 V ; 0.283 V ; 0.209 V ; 9e-10 s ; 1.03e-09 s ; No ; No ; +; test_flag_led ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0464 V ; 0.207 V ; 0.276 V ; 8.51e-10 s ; 8.52e-10 s ; No ; No ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0464 V ; 0.207 V ; 0.276 V ; 8.51e-10 s ; 8.52e-10 s ; No ; No ; +; convert_flag_led ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0464 V ; 0.207 V ; 0.276 V ; 8.51e-10 s ; 8.52e-10 s ; No ; No ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0464 V ; 0.207 V ; 0.276 V ; 8.51e-10 s ; 8.52e-10 s ; No ; No ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.49e-09 V ; 2.38 V ; -0.0505 V ; 0.23 V ; 0.155 V ; 4.84e-10 s ; 6.18e-10 s ; Yes ; No ; 2.32 V ; 7.49e-09 V ; 2.38 V ; -0.0505 V ; 0.23 V ; 0.155 V ; 4.84e-10 s ; 6.18e-10 s ; Yes ; No ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 85c Model) ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; mosi ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.018 V ; 0.27 V ; 0.216 V ; 1.11e-09 s ; 1.22e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.018 V ; 0.27 V ; 0.216 V ; 1.11e-09 s ; 1.22e-09 s ; Yes ; Yes ; +; cs_n ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.018 V ; 0.27 V ; 0.217 V ; 1.11e-09 s ; 1.22e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.018 V ; 0.27 V ; 0.217 V ; 1.11e-09 s ; 1.22e-09 s ; Yes ; Yes ; +; sclk ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0199 V ; 0.191 V ; 0.262 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0199 V ; 0.191 V ; 0.262 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; +; MOSI_ESP32 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.66e-07 V ; 2.37 V ; -0.0521 V ; 0.17 V ; 0.231 V ; 4.74e-10 s ; 4.79e-10 s ; Yes ; Yes ; 2.32 V ; 4.66e-07 V ; 2.37 V ; -0.0521 V ; 0.17 V ; 0.231 V ; 4.74e-10 s ; 4.79e-10 s ; Yes ; Yes ; +; cs_ESP32 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.66e-07 V ; 2.37 V ; -0.0526 V ; 0.169 V ; 0.23 V ; 4.75e-10 s ; 4.8e-10 s ; Yes ; Yes ; 2.32 V ; 4.66e-07 V ; 2.37 V ; -0.0526 V ; 0.169 V ; 0.23 V ; 4.75e-10 s ; 4.8e-10 s ; Yes ; Yes ; +; sclk_ESP32 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.66e-07 V ; 2.37 V ; -0.0521 V ; 0.17 V ; 0.231 V ; 4.74e-10 s ; 4.79e-10 s ; Yes ; Yes ; 2.32 V ; 4.66e-07 V ; 2.37 V ; -0.0521 V ; 0.17 V ; 0.231 V ; 4.74e-10 s ; 4.79e-10 s ; Yes ; Yes ; +; tx ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.018 V ; 0.27 V ; 0.216 V ; 1.11e-09 s ; 1.22e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.018 V ; 0.27 V ; 0.216 V ; 1.11e-09 s ; 1.22e-09 s ; Yes ; Yes ; +; test_flag_led ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; +; convert_flag_led ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.88e-07 V ; 2.36 V ; -0.0211 V ; 0.162 V ; 0.122 V ; 6.58e-10 s ; 7.79e-10 s ; No ; Yes ; 2.32 V ; 7.88e-07 V ; 2.36 V ; -0.0211 V ; 0.162 V ; 0.122 V ; 6.58e-10 s ; 7.79e-10 s ; No ; Yes ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1200mv 0c Model) ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; mosi ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 8.93e-07 V ; 3.52 V ; -0.0321 V ; 0.324 V ; 0.176 V ; 6.87e-10 s ; 8.14e-10 s ; No ; Yes ; 3.46 V ; 8.93e-07 V ; 3.52 V ; -0.0321 V ; 0.324 V ; 0.176 V ; 6.87e-10 s ; 8.14e-10 s ; No ; Yes ; +; cs_n ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0325 V ; 0.324 V ; 0.176 V ; 6.87e-10 s ; 8.14e-10 s ; No ; Yes ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0325 V ; 0.324 V ; 0.176 V ; 6.87e-10 s ; 8.14e-10 s ; No ; Yes ; +; sclk ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.251 V ; 6.54e-10 s ; 6.68e-10 s ; No ; Yes ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.251 V ; 6.54e-10 s ; 6.68e-10 s ; No ; Yes ; +; MOSI_ESP32 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; cs_ESP32 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.94e-08 V ; 2.78 V ; -0.0444 V ; 0.25 V ; 0.107 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; sclk_ESP32 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; 2.62 V ; 9.95e-08 V ; 2.78 V ; -0.0452 V ; 0.248 V ; 0.108 V ; 2.67e-10 s ; 2.75e-10 s ; No ; Yes ; +; tx ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 8.93e-07 V ; 3.52 V ; -0.0321 V ; 0.324 V ; 0.176 V ; 6.87e-10 s ; 8.14e-10 s ; No ; Yes ; 3.46 V ; 8.93e-07 V ; 3.52 V ; -0.0321 V ; 0.324 V ; 0.176 V ; 6.87e-10 s ; 8.14e-10 s ; No ; Yes ; +; test_flag_led ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.252 V ; 6.55e-10 s ; 6.68e-10 s ; No ; Yes ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.252 V ; 6.55e-10 s ; 6.68e-10 s ; No ; Yes ; +; convert_flag_led ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.252 V ; 6.55e-10 s ; 6.68e-10 s ; No ; Yes ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.252 V ; 6.55e-10 s ; 6.68e-10 s ; No ; Yes ; +; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0395 V ; 0.361 V ; 0.109 V ; 3.1e-10 s ; 4.41e-10 s ; No ; Yes ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0395 V ; 0.361 V ; 0.109 V ; 3.1e-10 s ; 4.41e-10 s ; No ; Yes ; ++------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Setup Transfers ; ++----------------------------------------------------------+----------------------------------------------------------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++----------------------------------------------------------+----------------------------------------------------------+----------+----------+----------+----------+ +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 593 ; 0 ; 0 ; 0 ; +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 16 ; 0 ; 0 ; 0 ; +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] ; 3 ; 0 ; 0 ; 0 ; +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] ; 92 ; 0 ; 0 ; 0 ; +; spi_master_2164:u_spi_master_2164|cs_n ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] ; 0 ; 142 ; 0 ; 0 ; +; spi_master_2164:u_spi_master_2164|cs_n ; spi_master_2164:u_spi_master_2164|cs_n ; 0 ; 0 ; 0 ; 31 ; ++----------------------------------------------------------+----------------------------------------------------------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Hold Transfers ; ++----------------------------------------------------------+----------------------------------------------------------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++----------------------------------------------------------+----------------------------------------------------------+----------+----------+----------+----------+ +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 593 ; 0 ; 0 ; 0 ; +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 16 ; 0 ; 0 ; 0 ; +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] ; 3 ; 0 ; 0 ; 0 ; +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] ; 92 ; 0 ; 0 ; 0 ; +; spi_master_2164:u_spi_master_2164|cs_n ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] ; 0 ; 142 ; 0 ; 0 ; +; spi_master_2164:u_spi_master_2164|cs_n ; spi_master_2164:u_spi_master_2164|cs_n ; 0 ; 0 ; 0 ; 31 ; ++----------------------------------------------------------+----------------------------------------------------------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 2 ; 2 ; +; Unconstrained Input Port Paths ; 82 ; 82 ; +; Unconstrained Output Ports ; 6 ; 6 ; +; Unconstrained Output Port Paths ; 6 ; 6 ; ++---------------------------------+-------+------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Status Summary ; ++----------------------------------------------------------+----------------------------------------------------------+-----------+-------------+ +; Target ; Clock ; Type ; Status ; ++----------------------------------------------------------+----------------------------------------------------------+-----------+-------------+ +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; Generated ; Constrained ; +; clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] ; Generated ; Constrained ; +; spi_master_2164:u_spi_master_2164|cs_n ; spi_master_2164:u_spi_master_2164|cs_n ; Base ; Constrained ; +; sys_clk ; sys_clk ; Base ; Constrained ; ++----------------------------------------------------------+----------------------------------------------------------+-----------+-------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; rst_n ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; test_flag ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++------------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++------------------+---------------------------------------------------------------------------------------+ +; convert_flag_led ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; cs_n ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; mosi ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; sclk ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; test_flag_led ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tx ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------------+---------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; rst_n ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; test_flag ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++------------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++------------------+---------------------------------------------------------------------------------------+ +; convert_flag_led ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; cs_n ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; mosi ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; sclk ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; test_flag_led ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; tx ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------------+---------------------------------------------------------------------------------------+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Timing Analyzer + Info: Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition + Info: Processing started: Sat Dec 6 16:45:28 2025 +Info: Command: quartus_sta intan_m10 -c intan_m10 +Info: qsta_default_script.tcl version: #1 +Info (20032): Parallel compilation is enabled and will use up to 4 processors +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'intan_m10.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained generated clocks found in the design. Calling "derive_pll_clocks -create_base_clocks" +Info (332110): Deriving PLL clocks + Info (332110): create_clock -period 83.333 -waveform {0.000 41.666} -name sys_clk sys_clk + Info (332110): create_generated_clock -source {clk_gen_inst|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 625 -multiply_by 6 -duty_cycle 50.00 -name {clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]} {clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]} + Info (332110): create_generated_clock -source {clk_gen_inst|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 625 -multiply_by 12 -duty_cycle 50.00 -name {clk_gen_inst|altpll_component|auto_generated|pll1|clk[1]} {clk_gen_inst|altpll_component|auto_generated|pll1|clk[1]} +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332105): Deriving Clocks + Info (332105): create_clock -period 1.000 -name spi_master_2164:u_spi_master_2164|cs_n spi_master_2164:u_spi_master_2164|cs_n +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. +Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info: Analyzing Slow 1200mV 85C Model +Info: Can't run Report Timing Closure Recommendations. The current device family is not supported. +Critical Warning (332148): Timing requirements not met +Info (332146): Worst-case setup slack is -6.111 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -6.111 -6.111 clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] + Info (332119): -0.600 -7.693 spi_master_2164:u_spi_master_2164|cs_n + Info (332119): 4335.838 0.000 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] +Info (332146): Worst-case hold slack is 0.362 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.362 0.000 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 0.362 0.000 clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] + Info (332119): 0.362 0.000 spi_master_2164:u_spi_master_2164|cs_n +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is -1.487 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -1.487 -46.097 spi_master_2164:u_spi_master_2164|cs_n + Info (332119): 41.541 0.000 sys_clk + Info (332119): 2169.851 0.000 clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] + Info (332119): 4339.991 0.000 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] +Info: Analyzing Slow 1200mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. +Critical Warning (332148): Timing requirements not met +Info (332146): Worst-case setup slack is -5.633 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -5.633 -5.633 clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] + Info (332119): -0.518 -5.401 spi_master_2164:u_spi_master_2164|cs_n + Info (332119): 4336.023 0.000 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] +Info (332146): Worst-case hold slack is 0.324 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.324 0.000 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 0.324 0.000 clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] + Info (332119): 0.324 0.000 spi_master_2164:u_spi_master_2164|cs_n +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is -1.487 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -1.487 -46.097 spi_master_2164:u_spi_master_2164|cs_n + Info (332119): 41.545 0.000 sys_clk + Info (332119): 2169.828 0.000 clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] + Info (332119): 4340.001 0.000 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] +Info: Analyzing Fast 1200mV 0C Model +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. +Critical Warning (332148): Timing requirements not met +Info (332146): Worst-case setup slack is -2.102 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -2.102 -2.102 clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] + Info (332119): 0.320 0.000 spi_master_2164:u_spi_master_2164|cs_n + Info (332119): 4338.451 0.000 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] +Info (332146): Worst-case hold slack is 0.150 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 0.150 0.000 spi_master_2164:u_spi_master_2164|cs_n + Info (332119): 0.152 0.000 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 0.152 0.000 clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is -1.000 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -1.000 -31.000 spi_master_2164:u_spi_master_2164|cs_n + Info (332119): 41.170 0.000 sys_clk + Info (332119): 2169.891 0.000 clk_gen_inst|altpll_component|auto_generated|pll1|clk[1] + Info (332119): 4340.042 0.000 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus Prime Timing Analyzer was successful. 0 errors, 4 warnings + Info: Peak virtual memory: 4783 megabytes + Info: Processing ended: Sat Dec 6 16:45:30 2025 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/puart2/uart_tx_restored/output_files/intan_m10.sta.summary b/puart2/uart_tx_restored/output_files/intan_m10.sta.summary new file mode 100644 index 0000000..8fc4312 --- /dev/null +++ b/puart2/uart_tx_restored/output_files/intan_m10.sta.summary @@ -0,0 +1,125 @@ +------------------------------------------------------------ +Timing Analyzer Summary +------------------------------------------------------------ + +Type : Slow 1200mV 85C Model Setup 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[1]' +Slack : -6.111 +TNS : -6.111 + +Type : Slow 1200mV 85C Model Setup 'spi_master_2164:u_spi_master_2164|cs_n' +Slack : -0.600 +TNS : -7.693 + +Type : Slow 1200mV 85C Model Setup 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]' +Slack : 4335.838 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Hold 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]' +Slack : 0.362 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Hold 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[1]' +Slack : 0.362 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Hold 'spi_master_2164:u_spi_master_2164|cs_n' +Slack : 0.362 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Minimum Pulse Width 'spi_master_2164:u_spi_master_2164|cs_n' +Slack : -1.487 +TNS : -46.097 + +Type : Slow 1200mV 85C Model Minimum Pulse Width 'sys_clk' +Slack : 41.541 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Minimum Pulse Width 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[1]' +Slack : 2169.851 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Minimum Pulse Width 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]' +Slack : 4339.991 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Setup 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[1]' +Slack : -5.633 +TNS : -5.633 + +Type : Slow 1200mV 0C Model Setup 'spi_master_2164:u_spi_master_2164|cs_n' +Slack : -0.518 +TNS : -5.401 + +Type : Slow 1200mV 0C Model Setup 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]' +Slack : 4336.023 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Hold 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]' +Slack : 0.324 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Hold 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[1]' +Slack : 0.324 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Hold 'spi_master_2164:u_spi_master_2164|cs_n' +Slack : 0.324 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Minimum Pulse Width 'spi_master_2164:u_spi_master_2164|cs_n' +Slack : -1.487 +TNS : -46.097 + +Type : Slow 1200mV 0C Model Minimum Pulse Width 'sys_clk' +Slack : 41.545 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Minimum Pulse Width 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[1]' +Slack : 2169.828 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Minimum Pulse Width 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]' +Slack : 4340.001 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Setup 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[1]' +Slack : -2.102 +TNS : -2.102 + +Type : Fast 1200mV 0C Model Setup 'spi_master_2164:u_spi_master_2164|cs_n' +Slack : 0.320 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Setup 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]' +Slack : 4338.451 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Hold 'spi_master_2164:u_spi_master_2164|cs_n' +Slack : 0.150 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Hold 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]' +Slack : 0.152 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Hold 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[1]' +Slack : 0.152 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Minimum Pulse Width 'spi_master_2164:u_spi_master_2164|cs_n' +Slack : -1.000 +TNS : -31.000 + +Type : Fast 1200mV 0C Model Minimum Pulse Width 'sys_clk' +Slack : 41.170 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Minimum Pulse Width 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[1]' +Slack : 2169.891 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Minimum Pulse Width 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]' +Slack : 4340.042 +TNS : 0.000 + +------------------------------------------------------------ diff --git a/puart2/uart_tx_restored/qar_info.json b/puart2/uart_tx_restored/qar_info.json new file mode 100644 index 0000000..162429f --- /dev/null +++ b/puart2/uart_tx_restored/qar_info.json @@ -0,0 +1,7 @@ +{ + "common_dir" : "E:/FPGA/SPItransfer/20240726/", + "acds_version" : "Version 17.1.0", + "platform" : "windows", + "os" : "Windows 10", + "qpf" : "intan_m10.qpf" +} \ No newline at end of file diff --git a/puart2/uart_tx_restored/spi_master_2164.v b/puart2/uart_tx_restored/spi_master_2164.v new file mode 100644 index 0000000..2c43b17 --- /dev/null +++ b/puart2/uart_tx_restored/spi_master_2164.v @@ -0,0 +1,126 @@ +module spi_master_2164( + input sys_clk, + input rst_n, + input [15:0] din, + input wire start, + output reg [15:0] dout, + output reg done, + + // connect to 2164 + output reg sclk, + output reg cs_n, + output reg mosi, + input miso, + + // for test only + output reg [6:0] cnt // count to 47 +); + + localparam cnt_total = 'd47; + + reg [15:0] dout_r; + + +//================== cnt =====================// + always @ (posedge sys_clk or negedge rst_n) begin + if(!rst_n) + cnt <= 'd0; + else if(cnt == cnt_total) + cnt <= 'd0; + else + cnt <= cnt + 1'b1; + end + + + +//================== send data ===============// + always @ (posedge sys_clk or negedge rst_n) begin + if(!rst_n) begin + sclk <= 1'b0; + cs_n <= 1'b1; + mosi <= 1'b0; + end + else begin + if (start) begin + case(cnt) + 6'd0: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end + 6'd1: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end + 6'd2: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= 1'b0; end + 6'd3: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= 1'b0; end + 6'd4: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[15]; end + 6'd5: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[15]; dout_r <= {dout_r[14:0],miso}; end + 6'd6: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[14]; end + 6'd7: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[14]; dout_r <= {dout_r[14:0],miso}; end + 6'd8: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[13]; end + 6'd9: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[13]; dout_r <= {dout_r[14:0],miso}; end + 6'd10: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[12]; end + 6'd11: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[12]; dout_r <= {dout_r[14:0],miso}; end + 6'd12: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[11]; end + 6'd13: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[11]; dout_r <= {dout_r[14:0],miso}; end + 6'd14: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[10]; end + 6'd15: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[10]; dout_r <= {dout_r[14:0],miso}; end + 6'd16: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[9]; end + 6'd17: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[9]; dout_r <= {dout_r[14:0],miso}; end + 6'd18: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[8]; end + 6'd19: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[8]; dout_r <= {dout_r[14:0],miso}; end + 6'd20: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[7]; end + 6'd21: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[7]; dout_r <= {dout_r[14:0],miso}; end + 6'd22: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[6]; end + 6'd23: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[6]; dout_r <= {dout_r[14:0],miso}; end + 6'd24: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[5]; end + 6'd25: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[5]; dout_r <= {dout_r[14:0],miso}; end + 6'd26: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[4]; end + 6'd27: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[4]; dout_r <= {dout_r[14:0],miso}; end + 6'd28: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[3]; end + 6'd29: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[3]; dout_r <= {dout_r[14:0],miso}; end + 6'd30: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[2]; end + 6'd31: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[2]; dout_r <= {dout_r[14:0],miso}; end + 6'd32: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[1]; end + 6'd33: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[1]; dout_r <= {dout_r[14:0],miso}; end + 6'd34: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[0]; end + 6'd35: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[0]; dout_r <= {dout_r[14:0],miso}; end + 6'd36: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= 1'b0; end + 6'd37: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= 1'b0; end + 6'd38: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= 1'b0; end + 6'd39: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= 1'b0; end + 6'd40: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end + 6'd41: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end + 6'd42: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end + 6'd43: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end + 6'd44: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end + 6'd45: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end + 6'd46: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end + 6'd47: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end + default: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end + endcase + end + end + end + + +//================ done =================// + always @ (posedge sys_clk or negedge rst_n) begin + if(!rst_n) + done <= 1'b0; + else if(cnt == cnt_total) + done <= 1'b1; + + else + done <= 1'b0; + end + + + +//================ dout =================// + always@(posedge sys_clk or negedge rst_n) begin + if(!rst_n) + dout <= 'd0; + else if(cnt == 'd36) + dout <= dout_r; + else + dout <= dout; + end + + + +endmodule diff --git a/puart2/uart_tx_restored/spi_master_esp32.v b/puart2/uart_tx_restored/spi_master_esp32.v new file mode 100644 index 0000000..fde9580 --- /dev/null +++ b/puart2/uart_tx_restored/spi_master_esp32.v @@ -0,0 +1,67 @@ +module spi_master_esp32( + input wire clk, + input wire rst_n, + input wire start, + input wire [15:0] din, + output reg done, + output wire sclk, + output wire mosi, + output reg cs +); + +reg [3:0] bit_cnt; +reg [15:0] shift_reg; +reg sclk_reg; +reg [1:0] state; + +localparam IDLE = 2'b00, TRANSFER = 2'b01, DONE = 2'b10; + +assign sclk = sclk_reg; +assign mosi = shift_reg[15]; + +always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + state <= IDLE; + cs <= 1; + sclk_reg <= 0; + bit_cnt <= 0; + shift_reg <= 0; + done <= 0; + end + else begin + + if (start) begin + case (state) + IDLE: begin + + state <= TRANSFER; + cs <= 0; // 选择从机 + shift_reg <= din; + bit_cnt <= 0; + done <= 0; + + end + + TRANSFER: begin + sclk_reg <= ~sclk_reg; //这样也是一个系统时钟周期新的sclk反转一次，所以sclk的频率也是115200. + if (sclk_reg) begin //看上面的assign mosi = shift_reg[15]; 所以每个sclk高电平mosi输出要输出的值。 + shift_reg <= {shift_reg[14:0], 1'b0}; + bit_cnt <= bit_cnt + 1; + if (bit_cnt == 15) begin + state <= DONE; + end + end + end + + DONE: begin + state <= IDLE; + cs <= 1; // 取消选择从机 + done <= 1; + end + + endcase + end + end +end + +endmodule \ No newline at end of file