TJU-SUN-LAB/waveform_acquisition_FPGA_code
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

update

Browse Source
This commit is contained in:
dsfsdf
2025-12-11 18:35:48 +08:00
commit 58bb0da74b
308 changed files with 17759 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

63
puart2/output_files/greybox_tmp/cbx_args.txt Normal file
View File

@@ -0,0 +1,63 @@
BANDWIDTH_TYPE=AUTO
CLK0_DIVIDE_BY=625
CLK0_DUTY_CYCLE=50
CLK0_MULTIPLY_BY=6
CLK0_PHASE_SHIFT=0
CLK1_DIVIDE_BY=625
CLK1_DUTY_CYCLE=50
CLK1_MULTIPLY_BY=12
CLK1_PHASE_SHIFT=0
COMPENSATE_CLOCK=CLK0
INCLK0_INPUT_FREQUENCY=83333
INTENDED_DEVICE_FAMILY="MAX 10"
LPM_TYPE=altpll
OPERATION_MODE=NORMAL
PLL_TYPE=AUTO
PORT_ACTIVECLOCK=PORT_UNUSED
PORT_ARESET=PORT_UNUSED
PORT_CLKBAD0=PORT_UNUSED
PORT_CLKBAD1=PORT_UNUSED
PORT_CLKLOSS=PORT_UNUSED
PORT_CLKSWITCH=PORT_UNUSED
PORT_CONFIGUPDATE=PORT_UNUSED
PORT_FBIN=PORT_UNUSED
PORT_INCLK0=PORT_USED
PORT_INCLK1=PORT_UNUSED
PORT_LOCKED=PORT_UNUSED
PORT_PFDENA=PORT_UNUSED
PORT_PHASECOUNTERSELECT=PORT_UNUSED
PORT_PHASEDONE=PORT_UNUSED
PORT_PHASESTEP=PORT_UNUSED
PORT_PHASEUPDOWN=PORT_UNUSED
PORT_PLLENA=PORT_UNUSED
PORT_SCANACLR=PORT_UNUSED
PORT_SCANCLK=PORT_UNUSED
PORT_SCANCLKENA=PORT_UNUSED
PORT_SCANDATA=PORT_UNUSED
PORT_SCANDATAOUT=PORT_UNUSED
PORT_SCANDONE=PORT_UNUSED
PORT_SCANREAD=PORT_UNUSED
PORT_SCANWRITE=PORT_UNUSED
PORT_clk0=PORT_USED
PORT_clk1=PORT_USED
PORT_clk2=PORT_UNUSED
PORT_clk3=PORT_UNUSED
PORT_clk4=PORT_UNUSED
PORT_clk5=PORT_UNUSED
PORT_clkena0=PORT_UNUSED
PORT_clkena1=PORT_UNUSED
PORT_clkena2=PORT_UNUSED
PORT_clkena3=PORT_UNUSED
PORT_clkena4=PORT_UNUSED
PORT_clkena5=PORT_UNUSED
PORT_extclk0=PORT_UNUSED
PORT_extclk1=PORT_UNUSED
PORT_extclk2=PORT_UNUSED
PORT_extclk3=PORT_UNUSED
WIDTH_CLOCK=5
DEVICE_FAMILY="MAX 10"
CBX_AUTO_BLACKBOX=ALL
inclk
inclk
clk
clk

90
puart2/output_files/intan_m10.asm.rpt Normal file
View File

@@ -0,0 +1,90 @@
Assembler report for intan_m10
Thu Dec 11 18:00:34 2025
Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: E:/FPGA/puart2/output_files/intan_m10.sof
6. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2017 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Thu Dec 11 18:00:34 2025 ;
; Revision Name ; intan_m10 ;
; Top-level Entity Name ; ddr_ctrl ;
; Family ; MAX 10 ;
; Device ; 10M08SAM153C8G ;
+-----------------------+---------------------------------------+
+----------------------------------+
; Assembler Settings ;
+--------+---------+---------------+
; Option ; Setting ; Default Value ;
+--------+---------+---------------+
+-------------------------------------------+
; Assembler Generated Files ;
+-------------------------------------------+
; File Name ;
+-------------------------------------------+
; E:/FPGA/puart2/output_files/intan_m10.sof ;
+-------------------------------------------+
+---------------------------------------------------------------------+
; Assembler Device Options: E:/FPGA/puart2/output_files/intan_m10.sof ;
+----------------+----------------------------------------------------+
; Option ; Setting ;
+----------------+----------------------------------------------------+
; JTAG usercode ; 0x0009DE95 ;
; Checksum ; 0x0009DE95 ;
+----------------+----------------------------------------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
Info: Processing started: Thu Dec 11 18:00:32 2025
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 4672 megabytes
Info: Processing ended: Thu Dec 11 18:00:34 2025
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:01

13
puart2/output_files/intan_m10.cdf Normal file
View File

@@ -0,0 +1,13 @@
/* Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(10M08SAM153) Path("E:/FPGA/puart2/output_files/") File("intan_m10.pof") MfrSpec(OpMask(1) Child_OpMask(2 1 1));
ChainEnd;
AlteraBegin;
ChainType(JTAG);
AlteraEnd;

1
puart2/output_files/intan_m10.done Normal file
View File

@@ -0,0 +1 @@
Thu Dec 11 18:00:41 2025

60
puart2/output_files/intan_m10.eda.rpt Normal file
View File

@@ -0,0 +1,60 @@
EDA Netlist Writer report for intan_m10
Mon Apr 15 18:12:21 2024
Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. EDA Netlist Writer Summary
3. EDA Netlist Writer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
+----------------------------------------------------------------------------------+
; EDA Netlist Writer Summary ;
+---------------------------+------------------------------------------------------+
; EDA Netlist Writer Status ; No Output Files Generated - Mon Apr 15 18:12:21 2024 ;
; Revision Name ; intan_m10 ;
; Top-level Entity Name ; ddr_ctrl ;
; Family ; MAX 10 ;
+---------------------------+------------------------------------------------------+
+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition
Info: Processing started: Mon Apr 15 18:12:20 2024
Info: Command: quartus_eda --read_settings_files=on --write_settings_files=off intan_m10 -c intan_m10
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Warning (199027): Can't generate output files. Specify command-line options to generate output files, or update EDA tool settings using GUI or Tcl script.
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 2 warnings
Info: Peak virtual memory: 4633 megabytes
Info: Processing ended: Mon Apr 15 18:12:21 2024
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:00

1203
puart2/output_files/intan_m10.fit.rpt Normal file
View File

File diff suppressed because it is too large Load Diff

8
puart2/output_files/intan_m10.fit.smsg Normal file
View File

@@ -0,0 +1,8 @@
Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
Extra Info (176236): Started Fast Input/Output/OE register processing
Extra Info (176237): Finished Fast Input/Output/OE register processing
Extra Info (176238): Start inferring scan chains for DSP blocks
Extra Info (176239): Inferring scan chains for DSP blocks is complete
Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks

18
puart2/output_files/intan_m10.fit.summary Normal file
View File

@@ -0,0 +1,18 @@
Fitter Status : Successful - Thu Dec 11 18:00:31 2025
Quartus Prime Version : 17.1.0 Build 590 10/25/2017 SJ Lite Edition
Revision Name : intan_m10
Top-level Entity Name : ddr_ctrl
Family : MAX 10
Device : 10M08SAM153C8G
Timing Models : Final
Total logic elements : 183 / 8,064 ( 2 % )
Total combinational functions : 123 / 8,064 ( 2 % )
Dedicated logic registers : 135 / 8,064 ( 2 % )
Total registers : 135
Total pins : 13 / 112 ( 12 % )
Total virtual pins : 0
Total memory bits : 0 / 387,072 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 48 ( 0 % )
Total PLLs : 1 / 1 ( 100 % )
UFM blocks : 0 / 1 ( 0 % )
ADC blocks : 0 / 1 ( 0 % )

136
puart2/output_files/intan_m10.flow.rpt Normal file
View File

@@ -0,0 +1,136 @@
Flow report for intan_m10
Thu Dec 11 18:00:41 2025
Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
8. Flow Messages
9. Flow Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2017 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
+----------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+---------------------------------------------+
; Flow Status ; Successful - Thu Dec 11 18:00:36 2025 ;
; Quartus Prime Version ; 17.1.0 Build 590 10/25/2017 SJ Lite Edition ;
; Revision Name ; intan_m10 ;
; Top-level Entity Name ; ddr_ctrl ;
; Family ; MAX 10 ;
; Device ; 10M08SAM153C8G ;
; Timing Models ; Final ;
; Total logic elements ; 183 / 8,064 ( 2 % ) ;
; Total combinational functions ; 123 / 8,064 ( 2 % ) ;
; Dedicated logic registers ; 135 / 8,064 ( 2 % ) ;
; Total registers ; 135 ;
; Total pins ; 13 / 112 ( 12 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 387,072 ( 0 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 48 ( 0 % ) ;
; Total PLLs ; 1 / 1 ( 100 % ) ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
; ADC blocks ; 0 / 1 ( 0 % ) ;
+------------------------------------+---------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 12/11/2025 18:00:16 ;
; Main task ; Compilation ;
; Revision Name ; intan_m10 ;
+-------------------+---------------------+
+-------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+-------------------------------------+----------------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+------------+
; COMPILER_SIGNATURE_ID ; 92384129777849.176544721619224 ; -- ; -- ; -- ;
; FLOW_ENABLE_POWER_ANALYZER ; On ; Off ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; MISC_FILE ; clk_gen_inst.v ; -- ; -- ; -- ;
; MISC_FILE ; clk_gen_bb.v ; -- ; -- ; -- ;
; MISC_FILE ; clk_gen.ppf ; -- ; -- ; -- ;
; NUM_PARALLEL_PROCESSORS ; 4 ; -- ; -- ; -- ;
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; ddr_ctrl ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; ddr_ctrl ; Top ;
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; ddr_ctrl ; Top ;
; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
; POWER_DEFAULT_INPUT_IO_TOGGLE_RATE ; 12.5 % ; 12.5% ; -- ; -- ;
; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
; TOP_LEVEL_ENTITY ; ddr_ctrl ; intan_m10 ; -- ; -- ;
+-------------------------------------+----------------------------------------+---------------+-------------+------------+
+-------------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:10 ; 1.0 ; 4766 MB ; 00:00:21 ;
; Fitter ; 00:00:05 ; 1.1 ; 5547 MB ; 00:00:06 ;
; Assembler ; 00:00:02 ; 1.0 ; 4671 MB ; 00:00:01 ;
; Power Analyzer ; 00:00:01 ; 1.1 ; 4812 MB ; 00:00:02 ;
; TimeQuest Timing Analyzer ; 00:00:04 ; 1.1 ; 4784 MB ; 00:00:03 ;
; Total ; 00:00:22 ; -- ; -- ; 00:00:33 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+-----------------------------------------------------------------------------------------+
; Flow OS Summary ;
+---------------------------+------------------+------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+---------------------------+------------------+------------+------------+----------------+
; Analysis & Synthesis ; LAPTOP-DER6L7FD ; Windows 10 ; 10.0 ; x86_64 ;
; Fitter ; LAPTOP-DER6L7FD ; Windows 10 ; 10.0 ; x86_64 ;
; Assembler ; LAPTOP-DER6L7FD ; Windows 10 ; 10.0 ; x86_64 ;
; Power Analyzer ; LAPTOP-DER6L7FD ; Windows 10 ; 10.0 ; x86_64 ;
; TimeQuest Timing Analyzer ; LAPTOP-DER6L7FD ; Windows 10 ; 10.0 ; x86_64 ;
+---------------------------+------------------+------------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off intan_m10 -c intan_m10
quartus_fit --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10
quartus_asm --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10
quartus_pow --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10
quartus_sta intan_m10 -c intan_m10

8
puart2/output_files/intan_m10.jdi Normal file
View File

@@ -0,0 +1,8 @@
<sld_project_info>
<project>
<hash md5_digest_80b="c3463640387bc845fe6a"/>
</project>
<file_info>
<file device="10M08SAM153C8G" path="intan_m10.sof" usercode="0xFFFFFFFF"/>
</file_info>
</sld_project_info>

998
puart2/output_files/intan_m10.map.rpt Normal file
View File

@@ -0,0 +1,998 @@
Analysis & Synthesis report for intan_m10
Thu Dec 11 18:00:25 2025
Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. Analysis & Synthesis IP Cores Summary
9. State Machine - |ddr_ctrl|state_top
10. State Machine - |ddr_ctrl|uart_tx:u_uart_pc|byte_select
11. State Machine - |ddr_ctrl|uart_tx:u_uart_pc|tx_state
12. State Machine - |ddr_ctrl|spi_master_esp32:tranfer|state
13. Registers Removed During Synthesis
14. Removed Registers Triggering Further Register Optimizations
15. General Register Statistics
16. Inverted Register Statistics
17. Multiplexer Restructuring Statistics (Restructuring Performed)
18. Parameter Settings for User Entity Instance: Top-level Entity: |ddr_ctrl
19. Parameter Settings for User Entity Instance: clk_gen:clk_gen_inst|altpll:altpll_component
20. Parameter Settings for User Entity Instance: uart_tx:u_uart_pc
21. altpll Parameter Settings by Entity Instance
22. Port Connectivity Checks: "spi_master_2164:u_spi_master_2164"
23. Port Connectivity Checks: "clk_gen:clk_gen_inst"
24. Post-Synthesis Netlist Statistics for Top Partition
25. Elapsed Time Per Partition
26. Analysis & Synthesis Messages
27. Analysis & Synthesis Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2017 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
+----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+---------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Dec 11 18:00:25 2025 ;
; Quartus Prime Version ; 17.1.0 Build 590 10/25/2017 SJ Lite Edition ;
; Revision Name ; intan_m10 ;
; Top-level Entity Name ; ddr_ctrl ;
; Family ; MAX 10 ;
; Total logic elements ; 198 ;
; Total combinational functions ; 121 ;
; Dedicated logic registers ; 135 ;
; Total registers ; 135 ;
; Total pins ; 13 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 1 ;
; UFM blocks ; 0 ;
; ADC blocks ; 0 ;
+------------------------------------+---------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device ; 10M08SAM153C8G ; ;
; Top-level entity name ; ddr_ctrl ; intan_m10 ;
; Family name ; MAX 10 ; Cyclone V ;
; Maximum processors allowed for parallel compilation ; 4 ; ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Infer RAMs from Raw Logic ; On ; On ;
; Parallel Synthesis ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto DSP Block Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Timing-Driven Synthesis ; On ; On ;
; Report Parameter Settings ; On ; On ;
; Report Source Assignments ; On ; On ;
; Report Connectivity Checks ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Auto Gated Clock Conversion ; Off ; Off ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Resource Aware Inference For Block RAM ; On ; On ;
+----------------------------------------------------------------------------+--------------------+--------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 8 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 4 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processors 2-4 ; 0.0% ;
+----------------------------+-------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------+------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+------------------------------+------------------------------------------------------------------+---------+
; spi_master_2164.v ; yes ; User Verilog HDL File ; E:/FPGA/puart2/spi_master_2164.v ; ;
; ddr_ctrl.v ; yes ; User Verilog HDL File ; E:/FPGA/puart2/ddr_ctrl.v ; ;
; clk_gen.v ; yes ; User Wizard-Generated File ; E:/FPGA/puart2/clk_gen.v ; ;
; spi_master_esp32.v ; yes ; User Verilog HDL File ; E:/FPGA/puart2/spi_master_esp32.v ; ;
; uart_tx.v ; yes ; User Verilog HDL File ; E:/FPGA/puart2/uart_tx.v ; ;
; altpll.tdf ; yes ; Megafunction ; e:/quartuslite/quartus/libraries/megafunctions/altpll.tdf ; ;
; aglobal171.inc ; yes ; Megafunction ; e:/quartuslite/quartus/libraries/megafunctions/aglobal171.inc ; ;
; stratix_pll.inc ; yes ; Megafunction ; e:/quartuslite/quartus/libraries/megafunctions/stratix_pll.inc ; ;
; stratixii_pll.inc ; yes ; Megafunction ; e:/quartuslite/quartus/libraries/megafunctions/stratixii_pll.inc ; ;
; cycloneii_pll.inc ; yes ; Megafunction ; e:/quartuslite/quartus/libraries/megafunctions/cycloneii_pll.inc ; ;
; db/clk_gen_altpll.v ; yes ; Auto-Generated Megafunction ; E:/FPGA/puart2/db/clk_gen_altpll.v ; ;
+----------------------------------+-----------------+------------------------------+------------------------------------------------------------------+---------+
+-------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+---------------------------------------------------------------------------------------------+
; Resource ; Usage ;
+---------------------------------------------+---------------------------------------------------------------------------------------------+
; Estimated Total logic elements ; 198 ;
; ; ;
; Total combinational functions ; 121 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 60 ;
; -- 3 input functions ; 30 ;
; -- <=2 input functions ; 31 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 100 ;
; -- arithmetic mode ; 21 ;
; ; ;
; Total registers ; 135 ;
; -- Dedicated logic registers ; 135 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 13 ;
; ; ;
; Embedded Multiplier 9-bit elements ; 0 ;
; ; ;
; Total PLLs ; 1 ;
; -- PLLs ; 1 ;
; ; ;
; Maximum fan-out node ; clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|wire_pll1_clk[0] ;
; Maximum fan-out ; 105 ;
; Total fan-out ; 843 ;
; Average fan-out ; 2.98 ;
+---------------------------------------------+---------------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+------------------------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+--------------------------------------------------------------------------------------+-----------------+--------------+
; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ;
+------------------------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+--------------------------------------------------------------------------------------+-----------------+--------------+
; |ddr_ctrl ; 121 (33) ; 135 (52) ; 0 ; 0 ; 0 ; 0 ; 0 ; 13 ; 0 ; 0 ; |ddr_ctrl ; ddr_ctrl ; work ;
; |clk_gen:clk_gen_inst| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ddr_ctrl|clk_gen:clk_gen_inst ; clk_gen ; work ;
; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ddr_ctrl|clk_gen:clk_gen_inst|altpll:altpll_component ; altpll ; work ;
; |clk_gen_altpll:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ddr_ctrl|clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated ; clk_gen_altpll ; work ;
; |spi_master_2164:u_spi_master_2164| ; 37 (37) ; 43 (43) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ddr_ctrl|spi_master_2164:u_spi_master_2164 ; spi_master_2164 ; work ;
; |uart_tx:u_uart_pc| ; 51 (51) ; 40 (40) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |ddr_ctrl|uart_tx:u_uart_pc ; uart_tx ; work ;
+------------------------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+--------------------------------------------------------------------------------------+-----------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary ;
+--------+--------------+---------+--------------+--------------+--------------------------------+-----------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ;
+--------+--------------+---------+--------------+--------------+--------------------------------+-----------------+
; Altera ; ALTPLL ; 17.1 ; N/A ; N/A ; |ddr_ctrl|clk_gen:clk_gen_inst ; clk_gen.v ;
+--------+--------------+---------+--------------+--------------+--------------------------------+-----------------+
Encoding Type: One-Hot
+------------------------------------------------------------------------------------------------+
; State Machine - |ddr_ctrl|state_top ;
+---------------------+---------------------+-----------------+-----------------+----------------+
; Name ; state_top.SEND_uart ; state_top.SEND2 ; state_top.SEND1 ; state_top.IDLE ;
+---------------------+---------------------+-----------------+-----------------+----------------+
; state_top.IDLE ; 0 ; 0 ; 0 ; 0 ;
; state_top.SEND1 ; 0 ; 0 ; 1 ; 1 ;
; state_top.SEND2 ; 0 ; 1 ; 0 ; 1 ;
; state_top.SEND_uart ; 1 ; 0 ; 0 ; 1 ;
+---------------------+---------------------+-----------------+-----------------+----------------+
Encoding Type: One-Hot
+---------------------------------------------------------+
; State Machine - |ddr_ctrl|uart_tx:u_uart_pc|byte_select ;
+----------------+----------------------------------------+
; Name ; byte_select.01 ;
+----------------+----------------------------------------+
; byte_select.00 ; 0 ;
; byte_select.01 ; 1 ;
+----------------+----------------------------------------+
Encoding Type: One-Hot
+------------------------------------------------------+
; State Machine - |ddr_ctrl|uart_tx:u_uart_pc|tx_state ;
+---------------+--------------------------------------+
; Name ; tx_state.0001 ;
+---------------+--------------------------------------+
; tx_state.0000 ; 0 ;
; tx_state.0001 ; 1 ;
+---------------+--------------------------------------+
Encoding Type: One-Hot
+-----------------------------------------------------------+
; State Machine - |ddr_ctrl|spi_master_esp32:tranfer|state ;
+----------------+------------+------------+----------------+
; Name ; state.IDLE ; state.DONE ; state.TRANSFER ;
+----------------+------------+------------+----------------+
; state.IDLE ; 0 ; 0 ; 0 ;
; state.TRANSFER ; 1 ; 0 ; 1 ;
; state.DONE ; 1 ; 1 ; 0 ;
+----------------+------------+------------+----------------+
+--------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+----------------------------------------------+---------------------------------------------+
; Register name ; Reason for Removal ;
+----------------------------------------------+---------------------------------------------+
; uart_tx:u_uart_pc|tx_shift_reg[9] ; Stuck at VCC due to stuck port data_in ;
; state_top~8 ; Lost fanout ;
; state_top~9 ; Lost fanout ;
; uart_tx:u_uart_pc|byte_select~6 ; Lost fanout ;
; uart_tx:u_uart_pc|tx_state~7 ; Lost fanout ;
; uart_tx:u_uart_pc|tx_state~8 ; Lost fanout ;
; uart_tx:u_uart_pc|tx_state~9 ; Lost fanout ;
; state_top.SEND2 ; Stuck at GND due to stuck port data_in ;
; start2 ; Stuck at GND due to stuck port data_in ;
; spi_master_esp32:tranfer|shift_reg[13] ; Stuck at GND due to stuck port clock_enable ;
; spi_master_esp32:tranfer|bit_cnt[0..3] ; Stuck at GND due to stuck port clock_enable ;
; spi_master_esp32:tranfer|done ; Stuck at GND due to stuck port clock_enable ;
; spi_master_esp32:tranfer|shift_reg[0..12,15] ; Stuck at GND due to stuck port clock_enable ;
; spi_master_esp32:tranfer|cs ; Stuck at VCC due to stuck port clock_enable ;
; spi_master_esp32:tranfer|sclk_reg ; Stuck at GND due to stuck port clock_enable ;
; spi_master_esp32:tranfer|shift_reg[14] ; Stuck at GND due to stuck port clock_enable ;
; spi_master_esp32:tranfer|state.TRANSFER ; Stuck at GND due to stuck port data_in ;
; spi_master_esp32:tranfer|state.DONE ; Stuck at GND due to stuck port data_in ;
; spi_master_esp32:tranfer|state.IDLE ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 35 ; ;
+----------------------------------------------+---------------------------------------------+
+------------------------------------------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations ;
+-----------------+---------------------------+--------------------------------------------------------------------------------------+
; Register name ; Reason for Removal ; Registers Removed due to This Register ;
+-----------------+---------------------------+--------------------------------------------------------------------------------------+
; state_top.SEND2 ; Stuck at GND ; start2, spi_master_esp32:tranfer|shift_reg[13], spi_master_esp32:tranfer|bit_cnt[3], ;
; ; due to stuck port data_in ; spi_master_esp32:tranfer|bit_cnt[2], spi_master_esp32:tranfer|bit_cnt[1], ;
; ; ; spi_master_esp32:tranfer|bit_cnt[0], spi_master_esp32:tranfer|done, ;
; ; ; spi_master_esp32:tranfer|shift_reg[12], spi_master_esp32:tranfer|shift_reg[11], ;
; ; ; spi_master_esp32:tranfer|shift_reg[10], spi_master_esp32:tranfer|shift_reg[9], ;
; ; ; spi_master_esp32:tranfer|shift_reg[8], spi_master_esp32:tranfer|shift_reg[7], ;
; ; ; spi_master_esp32:tranfer|shift_reg[6], spi_master_esp32:tranfer|shift_reg[5], ;
; ; ; spi_master_esp32:tranfer|shift_reg[4], spi_master_esp32:tranfer|shift_reg[3], ;
; ; ; spi_master_esp32:tranfer|shift_reg[2], spi_master_esp32:tranfer|shift_reg[1], ;
; ; ; spi_master_esp32:tranfer|shift_reg[0], spi_master_esp32:tranfer|shift_reg[15], ;
; ; ; spi_master_esp32:tranfer|cs, spi_master_esp32:tranfer|sclk_reg, ;
; ; ; spi_master_esp32:tranfer|shift_reg[14] ;
+-----------------+---------------------------+--------------------------------------------------------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 135 ;
; Number of registers using Synchronous Clear ; 7 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 90 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 68 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+---------------------------------------------------+
; Inverted Register Statistics ;
+-----------------------------------------+---------+
; Inverted Register ; Fan out ;
+-----------------------------------------+---------+
; spi_master_2164:u_spi_master_2164|cs_n ; 32 ;
; uart_tx:u_uart_pc|tx_shift_reg[0] ; 1 ;
; state[0] ; 3 ;
; uart_tx:u_uart_pc|tx_shift_reg[1] ; 1 ;
; uart_tx:u_uart_pc|tx_shift_reg[2] ; 1 ;
; uart_tx:u_uart_pc|tx_shift_reg[3] ; 1 ;
; uart_tx:u_uart_pc|tx_shift_reg[4] ; 1 ;
; uart_tx:u_uart_pc|tx_shift_reg[5] ; 1 ;
; uart_tx:u_uart_pc|tx_shift_reg[6] ; 1 ;
; uart_tx:u_uart_pc|tx_shift_reg[7] ; 1 ;
; uart_tx:u_uart_pc|tx_shift_reg[8] ; 1 ;
; Total number of inverted registers = 11 ; ;
+-----------------------------------------+---------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------+
; 4:1 ; 15 bits ; 30 LEs ; 15 LEs ; 15 LEs ; Yes ; |ddr_ctrl|spi_master_esp32:tranfer|shift_reg[2] ;
; 3:1 ; 7 bits ; 14 LEs ; 7 LEs ; 7 LEs ; Yes ; |ddr_ctrl|uart_tx:u_uart_pc|tx_shift_reg[4] ;
; 7:1 ; 4 bits ; 16 LEs ; 8 LEs ; 8 LEs ; No ; |ddr_ctrl|Selector3 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------+
+--------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |ddr_ctrl ;
+----------------+-------+-------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+-------------------------------------------------+
; IDLE ; 00 ; Unsigned Binary ;
; SEND1 ; 01 ; Unsigned Binary ;
; SEND2 ; 10 ; Unsigned Binary ;
; SEND_uart ; 11 ; Unsigned Binary ;
+----------------+-------+-------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: clk_gen:clk_gen_inst|altpll:altpll_component ;
+-------------------------------+---------------------------+-------------------------------+
; Parameter Name ; Value ; Type ;
+-------------------------------+---------------------------+-------------------------------+
; OPERATION_MODE ; NORMAL ; Untyped ;
; PLL_TYPE ; AUTO ; Untyped ;
; LPM_HINT ; CBX_MODULE_PREFIX=clk_gen ; Untyped ;
; QUALIFY_CONF_DONE ; OFF ; Untyped ;
; COMPENSATE_CLOCK ; CLK0 ; Untyped ;
; SCAN_CHAIN ; LONG ; Untyped ;
; PRIMARY_CLOCK ; INCLK0 ; Untyped ;
; INCLK0_INPUT_FREQUENCY ; 83333 ; Signed Integer ;
; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ;
; GATE_LOCK_SIGNAL ; NO ; Untyped ;
; GATE_LOCK_COUNTER ; 0 ; Untyped ;
; LOCK_HIGH ; 1 ; Untyped ;
; LOCK_LOW ; 1 ; Untyped ;
; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ;
; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ;
; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ;
; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ;
; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ;
; SKIP_VCO ; OFF ; Untyped ;
; SWITCH_OVER_COUNTER ; 0 ; Untyped ;
; SWITCH_OVER_TYPE ; AUTO ; Untyped ;
; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ;
; BANDWIDTH ; 0 ; Untyped ;
; BANDWIDTH_TYPE ; AUTO ; Untyped ;
; SPREAD_FREQUENCY ; 0 ; Untyped ;
; DOWN_SPREAD ; 0 ; Untyped ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ;
; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ;
; CLK9_MULTIPLY_BY ; 0 ; Untyped ;
; CLK8_MULTIPLY_BY ; 0 ; Untyped ;
; CLK7_MULTIPLY_BY ; 0 ; Untyped ;
; CLK6_MULTIPLY_BY ; 0 ; Untyped ;
; CLK5_MULTIPLY_BY ; 1 ; Untyped ;
; CLK4_MULTIPLY_BY ; 1 ; Untyped ;
; CLK3_MULTIPLY_BY ; 1 ; Untyped ;
; CLK2_MULTIPLY_BY ; 1 ; Untyped ;
; CLK1_MULTIPLY_BY ; 12 ; Signed Integer ;
; CLK0_MULTIPLY_BY ; 6 ; Signed Integer ;
; CLK9_DIVIDE_BY ; 0 ; Untyped ;
; CLK8_DIVIDE_BY ; 0 ; Untyped ;
; CLK7_DIVIDE_BY ; 0 ; Untyped ;
; CLK6_DIVIDE_BY ; 0 ; Untyped ;
; CLK5_DIVIDE_BY ; 1 ; Untyped ;
; CLK4_DIVIDE_BY ; 1 ; Untyped ;
; CLK3_DIVIDE_BY ; 1 ; Untyped ;
; CLK2_DIVIDE_BY ; 1 ; Untyped ;
; CLK1_DIVIDE_BY ; 625 ; Signed Integer ;
; CLK0_DIVIDE_BY ; 625 ; Signed Integer ;
; CLK9_PHASE_SHIFT ; 0 ; Untyped ;
; CLK8_PHASE_SHIFT ; 0 ; Untyped ;
; CLK7_PHASE_SHIFT ; 0 ; Untyped ;
; CLK6_PHASE_SHIFT ; 0 ; Untyped ;
; CLK5_PHASE_SHIFT ; 0 ; Untyped ;
; CLK4_PHASE_SHIFT ; 0 ; Untyped ;
; CLK3_PHASE_SHIFT ; 0 ; Untyped ;
; CLK2_PHASE_SHIFT ; 0 ; Untyped ;
; CLK1_PHASE_SHIFT ; 0 ; Untyped ;
; CLK0_PHASE_SHIFT ; 0 ; Untyped ;
; CLK5_TIME_DELAY ; 0 ; Untyped ;
; CLK4_TIME_DELAY ; 0 ; Untyped ;
; CLK3_TIME_DELAY ; 0 ; Untyped ;
; CLK2_TIME_DELAY ; 0 ; Untyped ;
; CLK1_TIME_DELAY ; 0 ; Untyped ;
; CLK0_TIME_DELAY ; 0 ; Untyped ;
; CLK9_DUTY_CYCLE ; 50 ; Untyped ;
; CLK8_DUTY_CYCLE ; 50 ; Untyped ;
; CLK7_DUTY_CYCLE ; 50 ; Untyped ;
; CLK6_DUTY_CYCLE ; 50 ; Untyped ;
; CLK5_DUTY_CYCLE ; 50 ; Untyped ;
; CLK4_DUTY_CYCLE ; 50 ; Untyped ;
; CLK3_DUTY_CYCLE ; 50 ; Untyped ;
; CLK2_DUTY_CYCLE ; 50 ; Untyped ;
; CLK1_DUTY_CYCLE ; 50 ; Signed Integer ;
; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ;
; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
; LOCK_WINDOW_UI ; 0.05 ; Untyped ;
; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ;
; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ;
; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ;
; DPA_MULTIPLY_BY ; 0 ; Untyped ;
; DPA_DIVIDE_BY ; 1 ; Untyped ;
; DPA_DIVIDER ; 0 ; Untyped ;
; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ;
; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ;
; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ;
; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ;
; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ;
; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ;
; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ;
; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ;
; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ;
; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ;
; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ;
; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ;
; EXTCLK3_TIME_DELAY ; 0 ; Untyped ;
; EXTCLK2_TIME_DELAY ; 0 ; Untyped ;
; EXTCLK1_TIME_DELAY ; 0 ; Untyped ;
; EXTCLK0_TIME_DELAY ; 0 ; Untyped ;
; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ;
; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ;
; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ;
; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ;
; VCO_MULTIPLY_BY ; 0 ; Untyped ;
; VCO_DIVIDE_BY ; 0 ; Untyped ;
; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ;
; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ;
; VCO_MIN ; 0 ; Untyped ;
; VCO_MAX ; 0 ; Untyped ;
; VCO_CENTER ; 0 ; Untyped ;
; PFD_MIN ; 0 ; Untyped ;
; PFD_MAX ; 0 ; Untyped ;
; M_INITIAL ; 0 ; Untyped ;
; M ; 0 ; Untyped ;
; N ; 1 ; Untyped ;
; M2 ; 1 ; Untyped ;
; N2 ; 1 ; Untyped ;
; SS ; 1 ; Untyped ;
; C0_HIGH ; 0 ; Untyped ;
; C1_HIGH ; 0 ; Untyped ;
; C2_HIGH ; 0 ; Untyped ;
; C3_HIGH ; 0 ; Untyped ;
; C4_HIGH ; 0 ; Untyped ;
; C5_HIGH ; 0 ; Untyped ;
; C6_HIGH ; 0 ; Untyped ;
; C7_HIGH ; 0 ; Untyped ;
; C8_HIGH ; 0 ; Untyped ;
; C9_HIGH ; 0 ; Untyped ;
; C0_LOW ; 0 ; Untyped ;
; C1_LOW ; 0 ; Untyped ;
; C2_LOW ; 0 ; Untyped ;
; C3_LOW ; 0 ; Untyped ;
; C4_LOW ; 0 ; Untyped ;
; C5_LOW ; 0 ; Untyped ;
; C6_LOW ; 0 ; Untyped ;
; C7_LOW ; 0 ; Untyped ;
; C8_LOW ; 0 ; Untyped ;
; C9_LOW ; 0 ; Untyped ;
; C0_INITIAL ; 0 ; Untyped ;
; C1_INITIAL ; 0 ; Untyped ;
; C2_INITIAL ; 0 ; Untyped ;
; C3_INITIAL ; 0 ; Untyped ;
; C4_INITIAL ; 0 ; Untyped ;
; C5_INITIAL ; 0 ; Untyped ;
; C6_INITIAL ; 0 ; Untyped ;
; C7_INITIAL ; 0 ; Untyped ;
; C8_INITIAL ; 0 ; Untyped ;
; C9_INITIAL ; 0 ; Untyped ;
; C0_MODE ; BYPASS ; Untyped ;
; C1_MODE ; BYPASS ; Untyped ;
; C2_MODE ; BYPASS ; Untyped ;
; C3_MODE ; BYPASS ; Untyped ;
; C4_MODE ; BYPASS ; Untyped ;
; C5_MODE ; BYPASS ; Untyped ;
; C6_MODE ; BYPASS ; Untyped ;
; C7_MODE ; BYPASS ; Untyped ;
; C8_MODE ; BYPASS ; Untyped ;
; C9_MODE ; BYPASS ; Untyped ;
; C0_PH ; 0 ; Untyped ;
; C1_PH ; 0 ; Untyped ;
; C2_PH ; 0 ; Untyped ;
; C3_PH ; 0 ; Untyped ;
; C4_PH ; 0 ; Untyped ;
; C5_PH ; 0 ; Untyped ;
; C6_PH ; 0 ; Untyped ;
; C7_PH ; 0 ; Untyped ;
; C8_PH ; 0 ; Untyped ;
; C9_PH ; 0 ; Untyped ;
; L0_HIGH ; 1 ; Untyped ;
; L1_HIGH ; 1 ; Untyped ;
; G0_HIGH ; 1 ; Untyped ;
; G1_HIGH ; 1 ; Untyped ;
; G2_HIGH ; 1 ; Untyped ;
; G3_HIGH ; 1 ; Untyped ;
; E0_HIGH ; 1 ; Untyped ;
; E1_HIGH ; 1 ; Untyped ;
; E2_HIGH ; 1 ; Untyped ;
; E3_HIGH ; 1 ; Untyped ;
; L0_LOW ; 1 ; Untyped ;
; L1_LOW ; 1 ; Untyped ;
; G0_LOW ; 1 ; Untyped ;
; G1_LOW ; 1 ; Untyped ;
; G2_LOW ; 1 ; Untyped ;
; G3_LOW ; 1 ; Untyped ;
; E0_LOW ; 1 ; Untyped ;
; E1_LOW ; 1 ; Untyped ;
; E2_LOW ; 1 ; Untyped ;
; E3_LOW ; 1 ; Untyped ;
; L0_INITIAL ; 1 ; Untyped ;
; L1_INITIAL ; 1 ; Untyped ;
; G0_INITIAL ; 1 ; Untyped ;
; G1_INITIAL ; 1 ; Untyped ;
; G2_INITIAL ; 1 ; Untyped ;
; G3_INITIAL ; 1 ; Untyped ;
; E0_INITIAL ; 1 ; Untyped ;
; E1_INITIAL ; 1 ; Untyped ;
; E2_INITIAL ; 1 ; Untyped ;
; E3_INITIAL ; 1 ; Untyped ;
; L0_MODE ; BYPASS ; Untyped ;
; L1_MODE ; BYPASS ; Untyped ;
; G0_MODE ; BYPASS ; Untyped ;
; G1_MODE ; BYPASS ; Untyped ;
; G2_MODE ; BYPASS ; Untyped ;
; G3_MODE ; BYPASS ; Untyped ;
; E0_MODE ; BYPASS ; Untyped ;
; E1_MODE ; BYPASS ; Untyped ;
; E2_MODE ; BYPASS ; Untyped ;
; E3_MODE ; BYPASS ; Untyped ;
; L0_PH ; 0 ; Untyped ;
; L1_PH ; 0 ; Untyped ;
; G0_PH ; 0 ; Untyped ;
; G1_PH ; 0 ; Untyped ;
; G2_PH ; 0 ; Untyped ;
; G3_PH ; 0 ; Untyped ;
; E0_PH ; 0 ; Untyped ;
; E1_PH ; 0 ; Untyped ;
; E2_PH ; 0 ; Untyped ;
; E3_PH ; 0 ; Untyped ;
; M_PH ; 0 ; Untyped ;
; C1_USE_CASC_IN ; OFF ; Untyped ;
; C2_USE_CASC_IN ; OFF ; Untyped ;
; C3_USE_CASC_IN ; OFF ; Untyped ;
; C4_USE_CASC_IN ; OFF ; Untyped ;
; C5_USE_CASC_IN ; OFF ; Untyped ;
; C6_USE_CASC_IN ; OFF ; Untyped ;
; C7_USE_CASC_IN ; OFF ; Untyped ;
; C8_USE_CASC_IN ; OFF ; Untyped ;
; C9_USE_CASC_IN ; OFF ; Untyped ;
; CLK0_COUNTER ; G0 ; Untyped ;
; CLK1_COUNTER ; G0 ; Untyped ;
; CLK2_COUNTER ; G0 ; Untyped ;
; CLK3_COUNTER ; G0 ; Untyped ;
; CLK4_COUNTER ; G0 ; Untyped ;
; CLK5_COUNTER ; G0 ; Untyped ;
; CLK6_COUNTER ; E0 ; Untyped ;
; CLK7_COUNTER ; E1 ; Untyped ;
; CLK8_COUNTER ; E2 ; Untyped ;
; CLK9_COUNTER ; E3 ; Untyped ;
; L0_TIME_DELAY ; 0 ; Untyped ;
; L1_TIME_DELAY ; 0 ; Untyped ;
; G0_TIME_DELAY ; 0 ; Untyped ;
; G1_TIME_DELAY ; 0 ; Untyped ;
; G2_TIME_DELAY ; 0 ; Untyped ;
; G3_TIME_DELAY ; 0 ; Untyped ;
; E0_TIME_DELAY ; 0 ; Untyped ;
; E1_TIME_DELAY ; 0 ; Untyped ;
; E2_TIME_DELAY ; 0 ; Untyped ;
; E3_TIME_DELAY ; 0 ; Untyped ;
; M_TIME_DELAY ; 0 ; Untyped ;
; N_TIME_DELAY ; 0 ; Untyped ;
; EXTCLK3_COUNTER ; E3 ; Untyped ;
; EXTCLK2_COUNTER ; E2 ; Untyped ;
; EXTCLK1_COUNTER ; E1 ; Untyped ;
; EXTCLK0_COUNTER ; E0 ; Untyped ;
; ENABLE0_COUNTER ; L0 ; Untyped ;
; ENABLE1_COUNTER ; L0 ; Untyped ;
; CHARGE_PUMP_CURRENT ; 2 ; Untyped ;
; LOOP_FILTER_R ; 1.000000 ; Untyped ;
; LOOP_FILTER_C ; 5 ; Untyped ;
; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ;
; LOOP_FILTER_R_BITS ; 9999 ; Untyped ;
; LOOP_FILTER_C_BITS ; 9999 ; Untyped ;
; VCO_POST_SCALE ; 0 ; Untyped ;
; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ;
; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ;
; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ;
; INTENDED_DEVICE_FAMILY ; MAX 10 ; Untyped ;
; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA2 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ;
; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ;
; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ;
; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ;
; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ;
; PORT_CLK0 ; PORT_USED ; Untyped ;
; PORT_CLK1 ; PORT_USED ; Untyped ;
; PORT_CLK2 ; PORT_UNUSED ; Untyped ;
; PORT_CLK3 ; PORT_UNUSED ; Untyped ;
; PORT_CLK4 ; PORT_UNUSED ; Untyped ;
; PORT_CLK5 ; PORT_UNUSED ; Untyped ;
; PORT_CLK6 ; PORT_UNUSED ; Untyped ;
; PORT_CLK7 ; PORT_UNUSED ; Untyped ;
; PORT_CLK8 ; PORT_UNUSED ; Untyped ;
; PORT_CLK9 ; PORT_UNUSED ; Untyped ;
; PORT_SCANDATA ; PORT_UNUSED ; Untyped ;
; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ;
; PORT_SCANDONE ; PORT_UNUSED ; Untyped ;
; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ;
; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ;
; PORT_INCLK1 ; PORT_UNUSED ; Untyped ;
; PORT_INCLK0 ; PORT_USED ; Untyped ;
; PORT_FBIN ; PORT_UNUSED ; Untyped ;
; PORT_PLLENA ; PORT_UNUSED ; Untyped ;
; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ;
; PORT_ARESET ; PORT_UNUSED ; Untyped ;
; PORT_PFDENA ; PORT_UNUSED ; Untyped ;
; PORT_SCANCLK ; PORT_UNUSED ; Untyped ;
; PORT_SCANACLR ; PORT_UNUSED ; Untyped ;
; PORT_SCANREAD ; PORT_UNUSED ; Untyped ;
; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ;
; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ;
; PORT_LOCKED ; PORT_UNUSED ; Untyped ;
; PORT_CONFIGUPDATE ; PORT_UNUSED ; Untyped ;
; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ;
; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ;
; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ;
; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ;
; PORT_SCANCLKENA ; PORT_UNUSED ; Untyped ;
; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ;
; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ;
; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ;
; M_TEST_SOURCE ; 5 ; Untyped ;
; C0_TEST_SOURCE ; 5 ; Untyped ;
; C1_TEST_SOURCE ; 5 ; Untyped ;
; C2_TEST_SOURCE ; 5 ; Untyped ;
; C3_TEST_SOURCE ; 5 ; Untyped ;
; C4_TEST_SOURCE ; 5 ; Untyped ;
; C5_TEST_SOURCE ; 5 ; Untyped ;
; C6_TEST_SOURCE ; 5 ; Untyped ;
; C7_TEST_SOURCE ; 5 ; Untyped ;
; C8_TEST_SOURCE ; 5 ; Untyped ;
; C9_TEST_SOURCE ; 5 ; Untyped ;
; CBXI_PARAMETER ; clk_gen_altpll ; Untyped ;
; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ;
; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ;
; WIDTH_CLOCK ; 5 ; Signed Integer ;
; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ;
; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ;
; DEVICE_FAMILY ; MAX 10 ; Untyped ;
; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ;
; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+-------------------------------+---------------------------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart_tx:u_uart_pc ;
+----------------+--------+--------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+--------+--------------------------------------+
; BAUD_RATE ; 115200 ; Signed Integer ;
; CLOCK_FREQ ; 115200 ; Signed Integer ;
+----------------+--------+--------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+------------------------------------------------------------------------------+
; altpll Parameter Settings by Entity Instance ;
+-------------------------------+----------------------------------------------+
; Name ; Value ;
+-------------------------------+----------------------------------------------+
; Number of entity instances ; 1 ;
; Entity Instance ; clk_gen:clk_gen_inst|altpll:altpll_component ;
; -- OPERATION_MODE ; NORMAL ;
; -- PLL_TYPE ; AUTO ;
; -- PRIMARY_CLOCK ; INCLK0 ;
; -- INCLK0_INPUT_FREQUENCY ; 83333 ;
; -- INCLK1_INPUT_FREQUENCY ; 0 ;
; -- VCO_MULTIPLY_BY ; 0 ;
; -- VCO_DIVIDE_BY ; 0 ;
+-------------------------------+----------------------------------------------+
+---------------------------------------------------------------+
; Port Connectivity Checks: "spi_master_2164:u_spi_master_2164" ;
+------+--------+----------+------------------------------------+
; Port ; Type ; Severity ; Details ;
+------+--------+----------+------------------------------------+
; cnt ; Output ; Info ; Explicitly unconnected ;
+------+--------+----------+------------------------------------+
+----------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "clk_gen:clk_gen_inst" ;
+------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+------+--------+----------+-------------------------------------------------------------------------------------+
; c1 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+------+--------+----------+-------------------------------------------------------------------------------------+
+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-----------------------+-----------------------------+
; Type ; Count ;
+-----------------------+-----------------------------+
; boundary_port ; 13 ;
; cycloneiii_ff ; 135 ;
; CLR ; 58 ;
; CLR SCLR ; 7 ;
; ENA ; 43 ;
; ENA CLR ; 25 ;
; plain ; 2 ;
; cycloneiii_lcell_comb ; 126 ;
; arith ; 21 ;
; 2 data inputs ; 20 ;
; 3 data inputs ; 1 ;
; normal ; 105 ;
; 0 data inputs ; 2 ;
; 1 data inputs ; 7 ;
; 2 data inputs ; 7 ;
; 3 data inputs ; 29 ;
; 4 data inputs ; 60 ;
; cycloneiii_pll ; 1 ;
; ; ;
; Max LUT depth ; 8.00 ;
; Average LUT depth ; 3.04 ;
+-----------------------+-----------------------------+
+-------------------------------+
; Elapsed Time Per Partition ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top ; 00:00:00 ;
+----------------+--------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
Info: Processing started: Thu Dec 11 18:00:15 2025
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off intan_m10 -c intan_m10
Info (20032): Parallel compilation is enabled and will use up to 4 processors
Info (12021): Found 1 design units, including 1 entities, in source file spi_master_2164.v
Info (12023): Found entity 1: spi_master_2164 File: E:/FPGA/puart2/spi_master_2164.v Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file ddr_ctrl.v
Info (12023): Found entity 1: ddr_ctrl File: E:/FPGA/puart2/ddr_ctrl.v Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file clk_gen.v
Info (12023): Found entity 1: clk_gen File: E:/FPGA/puart2/clk_gen.v Line: 39
Warning (12019): Can't analyze file -- file ../../20240625.v is missing
Info (12021): Found 1 design units, including 1 entities, in source file spi_master_esp32.v
Info (12023): Found entity 1: spi_master_esp32 File: E:/FPGA/puart2/spi_master_esp32.v Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file uart_tx.v
Info (12023): Found entity 1: uart_tx File: E:/FPGA/puart2/uart_tx.v Line: 1
Info (12127): Elaborating entity "ddr_ctrl" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at ddr_ctrl.v(71): object "received_data" assigned a value but never read File: E:/FPGA/puart2/ddr_ctrl.v Line: 71
Warning (10763): Verilog HDL warning at ddr_ctrl.v(153): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness File: E:/FPGA/puart2/ddr_ctrl.v Line: 153
Warning (10208): Verilog HDL Case Statement warning at ddr_ctrl.v(153): honored full_case synthesis attribute - differences between design synthesis and simulation may occur File: E:/FPGA/puart2/ddr_ctrl.v Line: 153
Info (12128): Elaborating entity "clk_gen" for hierarchy "clk_gen:clk_gen_inst" File: E:/FPGA/puart2/ddr_ctrl.v Line: 204
Info (12128): Elaborating entity "altpll" for hierarchy "clk_gen:clk_gen_inst|altpll:altpll_component" File: E:/FPGA/puart2/clk_gen.v Line: 94
Info (12130): Elaborated megafunction instantiation "clk_gen:clk_gen_inst|altpll:altpll_component" File: E:/FPGA/puart2/clk_gen.v Line: 94
Info (12133): Instantiated megafunction "clk_gen:clk_gen_inst|altpll:altpll_component" with the following parameter: File: E:/FPGA/puart2/clk_gen.v Line: 94
Info (12134): Parameter "bandwidth_type" = "AUTO"
Info (12134): Parameter "clk0_divide_by" = "625"
Info (12134): Parameter "clk0_duty_cycle" = "50"
Info (12134): Parameter "clk0_multiply_by" = "6"
Info (12134): Parameter "clk0_phase_shift" = "0"
Info (12134): Parameter "clk1_divide_by" = "625"
Info (12134): Parameter "clk1_duty_cycle" = "50"
Info (12134): Parameter "clk1_multiply_by" = "12"
Info (12134): Parameter "clk1_phase_shift" = "0"
Info (12134): Parameter "compensate_clock" = "CLK0"
Info (12134): Parameter "inclk0_input_frequency" = "83333"
Info (12134): Parameter "intended_device_family" = "MAX 10"
Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=clk_gen"
Info (12134): Parameter "lpm_type" = "altpll"
Info (12134): Parameter "operation_mode" = "NORMAL"
Info (12134): Parameter "pll_type" = "AUTO"
Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
Info (12134): Parameter "port_areset" = "PORT_UNUSED"
Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
Info (12134): Parameter "port_inclk0" = "PORT_USED"
Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
Info (12134): Parameter "port_locked" = "PORT_UNUSED"
Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
Info (12134): Parameter "port_clk0" = "PORT_USED"
Info (12134): Parameter "port_clk1" = "PORT_USED"
Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
Info (12134): Parameter "width_clock" = "5"
Info (12021): Found 1 design units, including 1 entities, in source file db/clk_gen_altpll.v
Info (12023): Found entity 1: clk_gen_altpll File: E:/FPGA/puart2/db/clk_gen_altpll.v Line: 29
Info (12128): Elaborating entity "clk_gen_altpll" for hierarchy "clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated" File: e:/quartuslite/quartus/libraries/megafunctions/altpll.tdf Line: 897
Info (12128): Elaborating entity "spi_master_2164" for hierarchy "spi_master_2164:u_spi_master_2164" File: E:/FPGA/puart2/ddr_ctrl.v Line: 221
Info (12128): Elaborating entity "spi_master_esp32" for hierarchy "spi_master_esp32:tranfer" File: E:/FPGA/puart2/ddr_ctrl.v Line: 234
Warning (10230): Verilog HDL assignment warning at spi_master_esp32.v(50): truncated value with size 32 to match size of target (4) File: E:/FPGA/puart2/spi_master_esp32.v Line: 50
Info (12128): Elaborating entity "uart_tx" for hierarchy "uart_tx:u_uart_pc" File: E:/FPGA/puart2/ddr_ctrl.v Line: 243
Warning (10230): Verilog HDL assignment warning at uart_tx.v(32): truncated value with size 32 to match size of target (16) File: E:/FPGA/puart2/uart_tx.v Line: 32
Warning (10230): Verilog HDL assignment warning at uart_tx.v(74): truncated value with size 32 to match size of target (4) File: E:/FPGA/puart2/uart_tx.v Line: 74
Info (13000): Registers with preset signals will power-up high File: E:/FPGA/puart2/spi_master_2164.v Line: 11
Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "MOSI_ESP32" is stuck at GND File: E:/FPGA/puart2/ddr_ctrl.v Line: 12
Warning (13410): Pin "cs_ESP32" is stuck at VCC File: E:/FPGA/puart2/ddr_ctrl.v Line: 13
Warning (13410): Pin "sclk_ESP32" is stuck at GND File: E:/FPGA/puart2/ddr_ctrl.v Line: 14
Info (286030): Timing-Driven Synthesis is running
Info (17049): 6 registers lost all their fanouts during netlist optimizations.
Info (144001): Generated suppressed messages file E:/FPGA/puart2/output_files/intan_m10.map.smsg
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL
Warning (15899): PLL "clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected File: E:/FPGA/puart2/db/clk_gen_altpll.v Line: 43
Info (21057): Implemented 213 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 4 input pins
Info (21059): Implemented 9 output pins
Info (21061): Implemented 199 logic cells
Info (21065): Implemented 1 PLLs
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings
Info: Peak virtual memory: 4766 megabytes
Info: Processing ended: Thu Dec 11 18:00:25 2025
Info: Elapsed time: 00:00:10
Info: Total CPU time (on all processors): 00:00:21
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in E:/FPGA/puart2/output_files/intan_m10.map.smsg.

2
puart2/output_files/intan_m10.map.smsg Normal file
View File

@@ -0,0 +1,2 @@
Warning (10268): Verilog HDL information at ddr_ctrl.v(151): always construct contains both blocking and non-blocking assignments File: E:/FPGA/puart2/ddr_ctrl.v Line: 151
Info (10281): Verilog HDL Declaration information at spi_master_esp32.v(6): object "done" differs only in case from object "DONE" in the same scope File: E:/FPGA/puart2/spi_master_esp32.v Line: 6

16
puart2/output_files/intan_m10.map.summary Normal file
View File

@@ -0,0 +1,16 @@
Analysis & Synthesis Status : Successful - Thu Dec 11 18:00:25 2025
Quartus Prime Version : 17.1.0 Build 590 10/25/2017 SJ Lite Edition
Revision Name : intan_m10
Top-level Entity Name : ddr_ctrl
Family : MAX 10
Total logic elements : 198
Total combinational functions : 121
Dedicated logic registers : 135
Total registers : 135
Total pins : 13
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 1
UFM blocks : 0
ADC blocks : 0

222
puart2/output_files/intan_m10.pin Normal file
View File

@@ -0,0 +1,222 @@
-- Copyright (C) 2017 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details.
--
-- This is a Quartus Prime output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus Prime input file. This file cannot be used
-- to make Quartus Prime pin assignments - for instructions on how to make pin
-- assignments, please see Quartus Prime help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- DNU : Do Not Use. This pin MUST NOT be connected.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1A: 2.5V
-- Bank 1B: 2.5V
-- Bank 2: 3.3V
-- Bank 3: 3.3V
-- Bank 5: 3.3V
-- Bank 6: 3.3V
-- Bank 8: 3.3V
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
-- or leave it unconnected.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
CHIP "intan_m10" ASSIGNED TO AN: 10M08SAM153C8G
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
GND : A1 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : A2 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 8 :
MOSI_ESP32 : A14 : output : 3.3-V LVCMOS : : 8 : Y
GND : A15 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B1 : : : : 1A :
GND : B2 : gnd : : : :
VCCA3 : B3 : power : : 3.0V/3.3V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 :
VCCIO8 : B5 : power : : 3.3V : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8 :
VCCIO8 : B9 : power : : 3.3V : 8 :
VCCIO8 : B10 : power : : 3.3V : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 8 :
cs_ESP32 : B13 : output : 3.3-V LVCMOS : : 8 : Y
sclk_ESP32 : B14 : output : 3.3-V LVCMOS : : 8 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : : : : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1A :
ANAIN1 : D4 : : : : :
GND : D5 : gnd : : : :
~ALTERA_nSTATUS~ / RESERVED_INPUT : D6 : input : 3.3 V Schmitt Trigger : : 8 : N
RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 :
~ALTERA_CONFIG_SEL~ / RESERVED_INPUT : D8 : input : 3.3-V LVTTL : : 8 : N
GND : D9 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 6 :
VCCA2 : D14 : power : : 3.0V/3.3V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : : : : 1A :
REFGND : E4 : : : : :
GND : E5 : gnd : : : :
~ALTERA_CONF_DONE~ / RESERVED_INPUT : E6 : input : 3.3 V Schmitt Trigger : : 8 : N
RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8 :
~ALTERA_nCONFIG~ / RESERVED_INPUT : E8 : input : 3.3 V Schmitt Trigger : : 8 : N
RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 6 :
GND : E12 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 6 :
VCCIO1A : F2 : power : : 2.5V : 1A :
ADC_VREF : F4 : : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 6 :
VCCIO6 : F14 : power : : 3.3V : 6 :
~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : input : 2.5 V Schmitt Trigger : : 1B : N
RESERVED_INPUT_WITH_WEAK_PULLUP : G2 : : : : 1B :
GND : G4 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1A :
RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 1B :
VCC_ONE : G8 : power : : 3.0V/3.3V : :
GND : G9 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 6 :
VCCIO6 : G14 : power : : 3.3V : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 6 :
VCCIO1B : H2 : power : : 2.5V : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1B :
~ALTERA_TDO~ : H4 : output : 2.5 V : : 1B : N
~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP : H5 : input : 2.5 V Schmitt Trigger : : 1B : N
VCC_ONE : H7 : power : : 3.0V/3.3V : :
GND : H8 : gnd : : : :
VCC_ONE : H9 : power : : 3.0V/3.3V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : H11 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 6 :
GND : H14 : gnd : : : :
~ALTERA_TCK~ / RESERVED_INPUT : J1 : input : 2.5 V Schmitt Trigger : : 1B : N
RESERVED_INPUT_WITH_WEAK_PULLUP : J2 : : : : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 2 :
sys_clk : J5 : input : 3.3-V LVCMOS : : 2 : Y
GND : J7 : gnd : : : :
VCC_ONE : J8 : power : : 3.0V/3.3V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : J9 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J11 : : : : 5 :
test_flag : J12 : input : 3.3-V LVCMOS : : 6 : Y
rst_n : J14 : input : 3.3-V LVCMOS : : 5 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1B :
RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K5 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K11 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K12 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K14 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1B :
VCCIO2 : L2 : power : : 3.3V : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L5 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L6 : : : : 3 :
mosi : L7 : output : 3.3-V LVCMOS : : 3 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L9 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L10 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L11 : : : : 5 :
GND : L12 : gnd : : : :
VCCIO5 : L14 : power : : 3.3V : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L15 : : : : 5 :
GND : M2 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M5 : : : : 3 :
GND : M6 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M9 : : : : 3 :
GND : M10 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : M11 : : : : 3 :
convert_flag_led : M12 : output : 3.3-V LVCMOS : : 5 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : M14 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N1 : : : : 2 :
VCCA1 : N2 : power : : 3.0V/3.3V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N14 : : : : 5 :
test_flag_led : N15 : output : 3.3-V LVCMOS : : 5 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P3 : : : : 3 :
miso : P4 : input : 3.3-V LVCMOS : : 3 : Y
VCCIO3 : P5 : power : : 3.3V : 3 :
cs_n : P6 : output : 3.3-V LVCMOS : : 3 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : P7 : : : : 3 :
tx : P8 : output : 3.3-V LVCMOS : : 3 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : P9 : : : : 3 :
VCCIO3 : P10 : power : : 3.3V : 3 :
VCCIO3 : P11 : power : : 3.3V : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P12 : : : : 3 :
VCCA4 : P13 : power : : 3.0V/3.3V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : P14 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P15 : : : : 3 :
GND : R1 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 3 :
sclk : R5 : output : 3.3-V LVCMOS : : 3 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R9 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R11 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R13 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R14 : : : : 3 :
GND : R15 : gnd : : : :

BIN
puart2/output_files/intan_m10.pof Normal file
View File

Binary file not shown.

309
puart2/output_files/intan_m10.pow.rpt Normal file
View File

@@ -0,0 +1,309 @@
Power Analyzer report for intan_m10
Thu Dec 11 18:00:36 2025
Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Parallel Compilation
3. Power Analyzer Summary
4. Power Analyzer Settings
5. Indeterminate Toggle Rates
6. Operating Conditions Used
7. Thermal Power Dissipation by Block
8. Thermal Power Dissipation by Block Type
9. Thermal Power Dissipation by Hierarchy
10. Core Dynamic Thermal Power Dissipation by Clock Domain
11. Current Drawn from Voltage Supplies Summary
12. VCCIO Supply Current Drawn by I/O Bank
13. VCCIO Supply Current Drawn by Voltage
14. Confidence Metric Details
15. Signal Activities
16. Power Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2017 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 8 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.13 ;
; Maximum used ; 4 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processors 2-4 ; 4.3% ;
+----------------------------+-------------+
+-------------------------------------------------------------------------------------------+
; Power Analyzer Summary ;
+----------------------------------------+--------------------------------------------------+
; Power Analyzer Status ; Successful - Thu Dec 11 18:00:36 2025 ;
; Quartus Prime Version ; 17.1.0 Build 590 10/25/2017 SJ Lite Edition ;
; Revision Name ; intan_m10 ;
; Top-level Entity Name ; ddr_ctrl ;
; Family ; MAX 10 ;
; Device ; 10M08SAM153C8G ;
; Power Models ; Final ;
; Total Thermal Power Dissipation ; 149.66 mW ;
; Core Dynamic Thermal Power Dissipation ; 0.00 mW ;
; Core Static Thermal Power Dissipation ; 121.22 mW ;
; I/O Thermal Power Dissipation ; 28.44 mW ;
; Power Estimation Confidence ; Low: user provided insufficient toggle rate data ;
+----------------------------------------+--------------------------------------------------+
+------------------------------------------------------------------------------------------------------------------------------------+
; Power Analyzer Settings ;
+----------------------------------------------------------------------------+---------------------------------------+---------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------------+---------------------------------------+---------------+
; Maximum processors allowed for parallel compilation ; 4 ; ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Default Power Input I/O Toggle Rate ; 12.5% ; 12.5% ;
; Preset Cooling Solution ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; ;
; Board thermal model ; None (CONSERVATIVE) ; ;
; Default Power Toggle Rate ; 12.5% ; 12.5% ;
; Use vectorless estimation ; On ; On ;
; Use Input Files ; Off ; Off ;
; Filter Glitches in VCD File Reader ; On ; On ;
; Power Analyzer Report Signal Activity ; Off ; Off ;
; Power Analyzer Report Power Dissipation ; Off ; Off ;
; Device Power Characteristics ; TYPICAL ; TYPICAL ;
; Automatically Compute Junction Temperature ; On ; On ;
; Specified Junction Temperature ; 25 ; 25 ;
; Ambient Temperature ; 25 ; 25 ;
; Use Custom Cooling Solution ; Off ; Off ;
; Board Temperature ; 25 ; 25 ;
+----------------------------------------------------------------------------+---------------------------------------+---------------+
+-----------------------------------------------------------------------------------------------------------------------------------+
; Indeterminate Toggle Rates ;
+-----------------------------------------------------------------------------------------------------+-----------------------------+
; Node ; Reason ;
+-----------------------------------------------------------------------------------------------------+-----------------------------+
; clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|wire_pll1_clk[0] ; No valid clock domain found ;
; test_flag ; No valid clock domain found ;
; rst_n ; No valid clock domain found ;
; sys_clk ; No valid clock domain found ;
; miso ; No valid clock domain found ;
; clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|wire_pll1_clk[0]~clkctrl ; No valid clock domain found ;
; spi_master_2164:u_spi_master_2164|cs_n~clkctrl ; No valid clock domain found ;
+-----------------------------------------------------------------------------------------------------+-----------------------------+
+--------------------------------------------------------------------------+
; Operating Conditions Used ;
+---------------------------------------------+----------------------------+
; Setting ; Value ;
+---------------------------------------------+----------------------------+
; Device power characteristics ; Typical ;
; ; ;
; Voltages ; ;
; VCCA ; 3.00 V ;
; VCC_ONE ; 3.00 V ;
; 3.3-V LVTTL I/O Standard ; 3.3 V ;
; 3.3-V LVCMOS I/O Standard ; 3.3 V ;
; 2.5 V I/O Standard ; 2.5 V ;
; 3.3 V Schmitt Trigger I/O Standard ; 3.3 V ;
; 2.5 V Schmitt Trigger I/O Standard ; 2.5 V ;
; ; ;
; Auto computed junction temperature ; 28.8 degrees Celsius ;
; Ambient temperature ; 25.0 degrees Celsius ;
; Junction-to-Case thermal resistance ; 11.00 degrees Celsius/Watt ;
; Case-to-Heat Sink thermal resistance ; 0.10 degrees Celsius/Watt ;
; Heat Sink-to-Ambient thermal resistance ; 14.30 degrees Celsius/Watt ;
; ; ;
; Board model used ; None ;
+---------------------------------------------+----------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------+
; Thermal Power Dissipation by Block ;
+------------+------------+---------------------+-----------------------------+--------------------------------+-------------------------------+
; Block Name ; Block Type ; Total Thermal Power ; Block Thermal Dynamic Power ; Block Thermal Static Power (1) ; Routing Thermal Dynamic Power ;
+------------+------------+---------------------+-----------------------------+--------------------------------+-------------------------------+
(1) The "Thermal Power Dissipation by Block" Table has been hidden. To show this table, please select the "Write power dissipation by block to report file" option under "PowerPlay Power Analyzer Settings".
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Thermal Power Dissipation by Block Type ;
+---------------------+-----------------------------------+-----------------------------+--------------------------------+-------------------------------+-----------------------------------------------------------+
; Block Type ; Total Thermal Power by Block Type ; Block Thermal Dynamic Power ; Block Thermal Static Power (1) ; Routing Thermal Dynamic Power ; Block Average Toggle Rate (millions of transitions / sec) ;
+---------------------+-----------------------------------+-----------------------------+--------------------------------+-------------------------------+-----------------------------------------------------------+
; Combinational cell ; 0.00 mW ; 0.00 mW ; -- ; 0.00 mW ; 0.000 ;
; Clock control block ; 0.00 mW ; 0.00 mW ; -- ; 0.00 mW ; 0.000 ;
; Register cell ; 0.00 mW ; 0.00 mW ; -- ; 0.00 mW ; 0.000 ;
; I/O ; 0.78 mW ; 0.00 mW ; 0.78 mW ; 0.00 mW ; 0.000 ;
; Voltage Regulator ; 0.76 mW ; 0.00 mW ; 0.76 mW ; -- ; -- ;
+---------------------+-----------------------------------+-----------------------------+--------------------------------+-------------------------------+-----------------------------------------------------------+
(1) The "Block Thermal Static Power" for all block types except Pins and the Voltage Regulator, if one exists, is part of the "Core Static Thermal Power Dissipation" value found on the PowerPlay Power Analyzer-->Summary report panel. The "Core Static Thermal Power Dissipation" also contains the thermal static power dissipated by the routing.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Thermal Power Dissipation by Hierarchy ;
+--------------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+--------------------------------------------------------------------------------------+
; Compilation Hierarchy Node ; Total Thermal Power by Hierarchy (1) ; Block Thermal Dynamic Power (1) ; Block Thermal Static Power (1)(2) ; Routing Thermal Dynamic Power (1) ; Full Hierarchy Name ;
+--------------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+--------------------------------------------------------------------------------------+
; |ddr_ctrl ; 1.55 mW (1.55 mW) ; 0.00 mW (0.00 mW) ; 1.55 mW (1.55 mW) ; 0.00 mW (0.00 mW) ; |ddr_ctrl ;
; |hard_block:auto_generated_inst ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |ddr_ctrl|hard_block:auto_generated_inst ;
; |clk_gen:clk_gen_inst ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |ddr_ctrl|clk_gen:clk_gen_inst ;
; |altpll:altpll_component ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |ddr_ctrl|clk_gen:clk_gen_inst|altpll:altpll_component ;
; |clk_gen_altpll:auto_generated ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |ddr_ctrl|clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated ;
; |spi_master_esp32:tranfer ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |ddr_ctrl|spi_master_esp32:tranfer ;
; |spi_master_2164:u_spi_master_2164 ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |ddr_ctrl|spi_master_2164:u_spi_master_2164 ;
; |uart_tx:u_uart_pc ; 0.00 mW (0.00 mW) ; 0.00 mW (0.00 mW) ; -- ; 0.00 mW (0.00 mW) ; |ddr_ctrl|uart_tx:u_uart_pc ;
+--------------------------------------------+--------------------------------------+---------------------------------+-----------------------------------+-----------------------------------+--------------------------------------------------------------------------------------+
(1) Value in parentheses is the power consumed at that level of hierarchy. Value not in parentheses is the power consumed at that level of hierarchy plus the power consumed by all levels of hierarchy below it.
(2) The "Block Thermal Static Power" for all levels of hierarchy except the top-level hierarchy is part of the "Core Static Thermal Power Dissipation" value found on the PowerPlay Power Analyzer-->Summary report panel. The "Core Static Thermal Power Dissipation" also contains the thermal static power dissipated by the routing.
+--------------------------------------------------------------------+
; Core Dynamic Thermal Power Dissipation by Clock Domain ;
+-----------------+-----------------------+--------------------------+
; Clock Domain ; Clock Frequency (MHz) ; Total Core Dynamic Power ;
+-----------------+-----------------------+--------------------------+
; No clock domain ; 0.00 ; 0.00 ;
+-----------------+-----------------------+--------------------------+
+------------------------------------------------------------------------------------------------------------------------------------+
; Current Drawn from Voltage Supplies Summary ;
+----------------+-------------------------+---------------------------+--------------------------+----------------------------------+
; Voltage Supply ; Total Current Drawn (1) ; Dynamic Current Drawn (1) ; Static Current Drawn (1) ; Minimum Power Supply Current (2) ;
+----------------+-------------------------+---------------------------+--------------------------+----------------------------------+
; VCCIO ; 8.79 mA ; 0.00 mA ; 8.79 mA ; 8.79 mA ;
; VCCA ; 3.03 mA ; 0.00 mA ; 3.03 mA ; 3.03 mA ;
; VCC_ONE ; 37.38 mA ; 0.00 mA ; 37.38 mA ; 37.38 mA ;
+----------------+-------------------------+---------------------------+--------------------------+----------------------------------+
(1) Currents reported in columns "Total Current Drawn", "Dynamic Current Drawn", and "Static Current Drawn" are sufficient for user operation of the device.
(2) Currents reported in column "Minimum Power Supply Current" are sufficient for power-up, configuration, and user operation of the device.
+-----------------------------------------------------------------------------------------------+
; VCCIO Supply Current Drawn by I/O Bank ;
+----------+---------------+---------------------+-----------------------+----------------------+
; I/O Bank ; VCCIO Voltage ; Total Current Drawn ; Dynamic Current Drawn ; Static Current Drawn ;
+----------+---------------+---------------------+-----------------------+----------------------+
; 1A ; 2.5V ; 0.25 mA ; 0.00 mA ; 0.25 mA ;
; 1B ; 2.5V ; 0.26 mA ; 0.00 mA ; 0.26 mA ;
; 2 ; 3.3V ; 1.62 mA ; 0.00 mA ; 1.62 mA ;
; 3 ; 3.3V ; 1.68 mA ; 0.00 mA ; 1.68 mA ;
; 4 ; -- ; -- ; -- ; -- ;
; 5 ; 3.3V ; 1.65 mA ; 0.00 mA ; 1.65 mA ;
; 6 ; 3.3V ; 1.62 mA ; 0.00 mA ; 1.62 mA ;
; 7 ; -- ; -- ; -- ; -- ;
; 8 ; 3.3V ; 1.72 mA ; 0.00 mA ; 1.72 mA ;
+----------+---------------+---------------------+-----------------------+----------------------+
+-----------------------------------------------------------------------------------------------------------------------------------+
; VCCIO Supply Current Drawn by Voltage ;
+---------------+-------------------------+---------------------------+--------------------------+----------------------------------+
; VCCIO Voltage ; Total Current Drawn (1) ; Dynamic Current Drawn (1) ; Static Current Drawn (1) ; Minimum Power Supply Current (2) ;
+---------------+-------------------------+---------------------------+--------------------------+----------------------------------+
; 2.5V ; 0.51 mA ; 0.00 mA ; 0.51 mA ; 0.51 mA ;
; 3.3V ; 8.28 mA ; 0.00 mA ; 8.28 mA ; 8.28 mA ;
+---------------+-------------------------+---------------------------+--------------------------+----------------------------------+
(1) Currents reported in columns "Total Current Drawn", "Dynamic Current Drawn", and "Static Current Drawn" are sufficient for user operation of the device.
(2) Currents reported in column "Minimum Power Supply Current" are sufficient for power-up, configuration, and user operation of the device.
+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Confidence Metric Details ;
+----------------------------------------------------------------------------------------+-------------+------------+--------------+---------------+
; Data Source ; Total ; Pin ; Registered ; Combinational ;
+----------------------------------------------------------------------------------------+-------------+------------+--------------+---------------+
; Simulation (from file) ; ; ; ; ;
; -- Number of signals with Toggle Rate from Simulation ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ;
; -- Number of signals with Static Probability from Simulation ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ;
; ; ; ; ; ;
; Node, entity or clock assignment ; ; ; ; ;
; -- Number of signals with Toggle Rate from Node, entity or clock assignment ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ;
; -- Number of signals with Static Probability from Node, entity or clock assignment ; 2 (0.5%) ; 0 (0.0%) ; 0 (0.0%) ; 2 (1.0%) ;
; ; ; ; ; ;
; Vectorless estimation ; ; ; ; ;
; -- Number of signals with Toggle Rate from Vectorless estimation ; 355 (97.0%) ; 11 (52.4%) ; 135 (100.0%) ; 209 (99.5%) ;
; -- Number of signals with Zero toggle rate, from Vectorless estimation ; 19 (5.2%) ; 6 (28.6%) ; 0 (0.0%) ; 13 (6.2%) ;
; -- Number of signals with Static Probability from Vectorless estimation ; 353 (96.4%) ; 11 (52.4%) ; 135 (100.0%) ; 207 (98.6%) ;
; ; ; ; ; ;
; Default assignment ; ; ; ; ;
; -- Number of signals with Toggle Rate from Default assignment ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ; 0 (0.0%) ;
; -- Number of signals with Static Probability from Default assignment ; 11 (3.0%) ; 10 (47.6%) ; 0 (0.0%) ; 1 (0.5%) ;
; ; ; ; ; ;
; Assumed 0 ; ; ; ; ;
; -- Number of signals with Toggle Rate assumed 0 ; 11 (3.0%) ; 10 (47.6%) ; 0 (0.0%) ; 1 (0.5%) ;
+----------------------------------------------------------------------------------------+-------------+------------+--------------+---------------+
+---------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Activities ;
+--------+------+---------------------------------------------+-------------------------+--------------------+--------------------------------+
; Signal ; Type ; Toggle Rate (millions of transitions / sec) ; Toggle Rate Data Source ; Static Probability ; Static Probability Data Source ;
+--------+------+---------------------------------------------+-------------------------+--------------------+--------------------------------+
(1) The "Signal Activity" Table has been hidden. To show this table, please select the "Write signal activities to report file" option under "PowerPlay Power Analyzer Settings".
+-------------------------+
; Power Analyzer Messages ;
+-------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Power Analyzer
Info: Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
Info: Processing started: Thu Dec 11 18:00:35 2025
Info: Command: quartus_pow --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Critical Warning (332012): Synopsys Design Constraints File file not found: 'intan_m10.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Warning (332060): Node: sys_clk was determined to be a clock but was found without an associated clock assignment.
Info (13166): Register spi_master_2164:u_spi_master_2164|cnt[1] is being clocked by sys_clk
Warning (332060): Node: spi_master_2164:u_spi_master_2164|cs_n was determined to be a clock but was found without an associated clock assignment.
Info (13166): Register state[2] is being clocked by spi_master_2164:u_spi_master_2164|cs_n
Warning (332068): No clocks defined in design.
Warning (332056): PLL cross checking found inconsistent PLL clock settings:
Warning (332056): Node: clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 83.333
Info (223000): Starting Vectorless Power Activity Estimation
Warning (222013): Relative toggle rates could not be calculated because no clock domain could be identified for some nodes
Info (223001): Completed Vectorless Power Activity Estimation
Info (218000): Using Advanced I/O Power to simulate I/O buffers with the specified board trace model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (215049): Average toggle rate for this design is 0.000 millions of transitions / sec
Info (215031): Total thermal power estimate for the design is 149.66 mW
Info: Quartus Prime Power Analyzer was successful. 0 errors, 7 warnings
Info: Peak virtual memory: 4812 megabytes
Info: Processing ended: Thu Dec 11 18:00:37 2025
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:02

12
puart2/output_files/intan_m10.pow.summary Normal file
View File

@@ -0,0 +1,12 @@
Power Analyzer Status : Successful - Thu Dec 11 18:00:36 2025
Quartus Prime Version : 17.1.0 Build 590 10/25/2017 SJ Lite Edition
Revision Name : intan_m10
Top-level Entity Name : ddr_ctrl
Family : MAX 10
Device : 10M08SAM153C8G
Power Models : Final
Total Thermal Power Dissipation : 149.66 mW
Core Dynamic Thermal Power Dissipation : 0.00 mW
Core Static Thermal Power Dissipation : 121.22 mW
I/O Thermal Power Dissipation : 28.44 mW
Power Estimation Confidence : Low: user provided insufficient toggle rate data

1
puart2/output_files/intan_m10.sld Normal file
View File

@@ -0,0 +1 @@
<sld_project_info/>

BIN
puart2/output_files/intan_m10.sof Normal file
View File

Binary file not shown.

637
puart2/output_files/intan_m10.sta.rpt Normal file
View File

@@ -0,0 +1,637 @@
TimeQuest Timing Analyzer report for intan_m10
Thu Dec 11 18:00:41 2025
Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. TimeQuest Timing Analyzer Summary
3. Parallel Compilation
4. Clocks
5. Slow 1200mV 85C Model Fmax Summary
6. Slow 1200mV 85C Model Setup Summary
7. Slow 1200mV 85C Model Hold Summary
8. Slow 1200mV 85C Model Recovery Summary
9. Slow 1200mV 85C Model Removal Summary
10. Slow 1200mV 85C Model Minimum Pulse Width Summary
11. Slow 1200mV 85C Model Metastability Summary
12. Slow 1200mV 0C Model Fmax Summary
13. Slow 1200mV 0C Model Setup Summary
14. Slow 1200mV 0C Model Hold Summary
15. Slow 1200mV 0C Model Recovery Summary
16. Slow 1200mV 0C Model Removal Summary
17. Slow 1200mV 0C Model Minimum Pulse Width Summary
18. Slow 1200mV 0C Model Metastability Summary
19. Fast 1200mV 0C Model Setup Summary
20. Fast 1200mV 0C Model Hold Summary
21. Fast 1200mV 0C Model Recovery Summary
22. Fast 1200mV 0C Model Removal Summary
23. Fast 1200mV 0C Model Minimum Pulse Width Summary
24. Fast 1200mV 0C Model Metastability Summary
25. Multicorner Timing Analysis Summary
26. Board Trace Model Assignments
27. Input Transition Times
28. Signal Integrity Metrics (Slow 1200mv 0c Model)
29. Signal Integrity Metrics (Slow 1200mv 85c Model)
30. Signal Integrity Metrics (Fast 1200mv 0c Model)
31. Setup Transfers
32. Hold Transfers
33. Report TCCS
34. Report RSKM
35. Unconstrained Paths Summary
36. Clock Status Summary
37. Unconstrained Input Ports
38. Unconstrained Output Ports
39. Unconstrained Input Ports
40. Unconstrained Output Ports
41. TimeQuest Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2017 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
+-----------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary ;
+-----------------------+-----------------------------------------------------+
; Quartus Prime Version ; Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition ;
; Timing Analyzer ; TimeQuest ;
; Revision Name ; intan_m10 ;
; Device Family ; MAX 10 ;
; Device Name ; 10M08SAM153C8G ;
; Timing Models ; Final ;
; Delay Model ; Combined ;
; Rise/Fall Delays ; Enabled ;
+-----------------------+-----------------------------------------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 8 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.10 ;
; Maximum used ; 4 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 3.4% ;
; Processors 3-4 ; 3.4% ;
+----------------------------+-------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks ;
+----------------------------------------------------------+-----------+----------+------------+-------+----------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------+------------------------------------------------------------+--------------------------------------------------------------+
; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
+----------------------------------------------------------+-----------+----------+------------+-------+----------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------+------------------------------------------------------------+--------------------------------------------------------------+
; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 8680.520 ; 0.12 MHz ; 0.000 ; 4340.260 ; 50.00 ; 625 ; 6 ; ; ; ; ; false ; sys_clk ; clk_gen_inst|altpll_component|auto_generated|pll1|inclk[0] ; { clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] } ;
; spi_master_2164:u_spi_master_2164|cs_n ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { spi_master_2164:u_spi_master_2164|cs_n } ;
; sys_clk ; Base ; 83.333 ; 12.0 MHz ; 0.000 ; 41.666 ; ; ; ; ; ; ; ; ; ; ; { sys_clk } ;
+----------------------------------------------------------+-----------+----------+------------+-------+----------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------+------------------------------------------------------------+--------------------------------------------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary ;
+------------+-----------------+----------------------------------------------------------+------------------------------------------------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+------------+-----------------+----------------------------------------------------------+------------------------------------------------+
; 154.2 MHz ; 154.2 MHz ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; ;
; 609.01 MHz ; 402.09 MHz ; spi_master_2164:u_spi_master_2164|cs_n ; limit due to minimum period restriction (tmin) ;
+------------+-----------------+----------------------------------------------------------+------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+-----------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary ;
+----------------------------------------------------------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+----------------------------------------------------------+--------+---------------+
; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; -6.744 ; -6.744 ;
; spi_master_2164:u_spi_master_2164|cs_n ; -0.642 ; -7.912 ;
+----------------------------------------------------------+--------+---------------+
+----------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary ;
+----------------------------------------------------------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+----------------------------------------------------------+-------+---------------+
; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.362 ; 0.000 ;
; spi_master_2164:u_spi_master_2164|cs_n ; 0.363 ; 0.000 ;
+----------------------------------------------------------+-------+---------------+
------------------------------------------
; Slow 1200mV 85C Model Recovery Summary ;
------------------------------------------
No paths to report.
-----------------------------------------
; Slow 1200mV 85C Model Removal Summary ;
-----------------------------------------
No paths to report.
+-------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
+----------------------------------------------------------+----------+---------------+
; Clock ; Slack ; End Point TNS ;
+----------------------------------------------------------+----------+---------------+
; spi_master_2164:u_spi_master_2164|cs_n ; -1.487 ; -46.097 ;
; sys_clk ; 41.554 ; 0.000 ;
; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 4339.989 ; 0.000 ;
+----------------------------------------------------------+----------+---------------+
-----------------------------------------------
; Slow 1200mV 85C Model Metastability Summary ;
-----------------------------------------------
The design MTBF is not calculated because there are no specified synchronizers in the design.
Number of Synchronizer Chains Found: 1
Shortest Synchronizer Chain: 2 Registers
Fraction of Chains for which MTBFs Could Not be Calculated: 1.000
Worst Case Available Settling Time: 17358.585 ns
+------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary ;
+------------+-----------------+----------------------------------------------------------+------------------------------------------------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+------------+-----------------+----------------------------------------------------------+------------------------------------------------+
; 164.42 MHz ; 164.42 MHz ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; ;
; 642.67 MHz ; 402.09 MHz ; spi_master_2164:u_spi_master_2164|cs_n ; limit due to minimum period restriction (tmin) ;
+------------+-----------------+----------------------------------------------------------+------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+-----------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary ;
+----------------------------------------------------------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+----------------------------------------------------------+--------+---------------+
; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; -6.215 ; -6.215 ;
; spi_master_2164:u_spi_master_2164|cs_n ; -0.556 ; -5.863 ;
+----------------------------------------------------------+--------+---------------+
+----------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary ;
+----------------------------------------------------------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+----------------------------------------------------------+-------+---------------+
; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.324 ; 0.000 ;
; spi_master_2164:u_spi_master_2164|cs_n ; 0.325 ; 0.000 ;
+----------------------------------------------------------+-------+---------------+
-----------------------------------------
; Slow 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.
----------------------------------------
; Slow 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.
+-------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
+----------------------------------------------------------+----------+---------------+
; Clock ; Slack ; End Point TNS ;
+----------------------------------------------------------+----------+---------------+
; spi_master_2164:u_spi_master_2164|cs_n ; -1.487 ; -46.097 ;
; sys_clk ; 41.555 ; 0.000 ;
; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 4340.000 ; 0.000 ;
+----------------------------------------------------------+----------+---------------+
----------------------------------------------
; Slow 1200mV 0C Model Metastability Summary ;
----------------------------------------------
The design MTBF is not calculated because there are no specified synchronizers in the design.
Number of Synchronizer Chains Found: 1
Shortest Synchronizer Chain: 2 Registers
Fraction of Chains for which MTBFs Could Not be Calculated: 1.000
Worst Case Available Settling Time: 17358.726 ns
+-----------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary ;
+----------------------------------------------------------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+----------------------------------------------------------+--------+---------------+
; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; -2.312 ; -2.312 ;
; spi_master_2164:u_spi_master_2164|cs_n ; 0.304 ; 0.000 ;
+----------------------------------------------------------+--------+---------------+
+----------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary ;
+----------------------------------------------------------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+----------------------------------------------------------+-------+---------------+
; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.151 ; 0.000 ;
; spi_master_2164:u_spi_master_2164|cs_n ; 0.151 ; 0.000 ;
+----------------------------------------------------------+-------+---------------+
-----------------------------------------
; Fast 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.
----------------------------------------
; Fast 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.
+-------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
+----------------------------------------------------------+----------+---------------+
; Clock ; Slack ; End Point TNS ;
+----------------------------------------------------------+----------+---------------+
; spi_master_2164:u_spi_master_2164|cs_n ; -1.000 ; -31.000 ;
; sys_clk ; 41.180 ; 0.000 ;
; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 4340.041 ; 0.000 ;
+----------------------------------------------------------+----------+---------------+
----------------------------------------------
; Fast 1200mV 0C Model Metastability Summary ;
----------------------------------------------
The design MTBF is not calculated because there are no specified synchronizers in the design.
Number of Synchronizer Chains Found: 1
Shortest Synchronizer Chain: 2 Registers
Fraction of Chains for which MTBFs Could Not be Calculated: 1.000
Worst Case Available Settling Time: 17359.966 ns
+------------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary ;
+-----------------------------------------------------------+---------+-------+----------+---------+---------------------+
; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
+-----------------------------------------------------------+---------+-------+----------+---------+---------------------+
; Worst-case Slack ; -6.744 ; 0.151 ; N/A ; N/A ; -1.487 ;
; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; -6.744 ; 0.151 ; N/A ; N/A ; 4339.989 ;
; spi_master_2164:u_spi_master_2164|cs_n ; -0.642 ; 0.151 ; N/A ; N/A ; -1.487 ;
; sys_clk ; N/A ; N/A ; N/A ; N/A ; 41.180 ;
; Design-wide TNS ; -14.656 ; 0.0 ; 0.0 ; 0.0 ; -46.097 ;
; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; -6.744 ; 0.000 ; N/A ; N/A ; 0.000 ;
; spi_master_2164:u_spi_master_2164|cs_n ; -7.912 ; 0.000 ; N/A ; N/A ; -46.097 ;
; sys_clk ; N/A ; N/A ; N/A ; N/A ; 0.000 ;
+-----------------------------------------------------------+---------+-------+----------+---------+---------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments ;
+------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; mosi ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; cs_n ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; sclk ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; MOSI_ESP32 ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; cs_ESP32 ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; sclk_ESP32 ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; tx ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; test_flag_led ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; convert_flag_led ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; ~ALTERA_TDO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+---------------------------------------------------------------------------------+
; Input Transition Times ;
+---------------------+-----------------------+-----------------+-----------------+
; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+---------------------+-----------------------+-----------------+-----------------+
; test_flag ; 3.3-V LVCMOS ; 2640 ps ; 2640 ps ;
; rst_n ; 3.3-V LVCMOS ; 2640 ps ; 2640 ps ;
; sys_clk ; 3.3-V LVCMOS ; 2640 ps ; 2640 ps ;
; miso ; 3.3-V LVCMOS ; 2640 ps ; 2640 ps ;
; ~ALTERA_TMS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ;
; ~ALTERA_TCK~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ;
; ~ALTERA_TDI~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ;
; ~ALTERA_CONFIG_SEL~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
; ~ALTERA_nCONFIG~ ; 3.3 V Schmitt Trigger ; 2640 ps ; 2640 ps ;
; ~ALTERA_nSTATUS~ ; 3.3 V Schmitt Trigger ; 2640 ps ; 2640 ps ;
; ~ALTERA_CONF_DONE~ ; 3.3 V Schmitt Trigger ; 2640 ps ; 2640 ps ;
+---------------------+-----------------------+-----------------+-----------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
+------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; mosi ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0411 V ; 0.283 V ; 0.209 V ; 9e-10 s ; 1.03e-09 s ; No ; No ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0411 V ; 0.283 V ; 0.209 V ; 9e-10 s ; 1.03e-09 s ; No ; No ;
; cs_n ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0417 V ; 0.287 V ; 0.209 V ; 8.99e-10 s ; 1.03e-09 s ; No ; No ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0417 V ; 0.287 V ; 0.209 V ; 8.99e-10 s ; 1.03e-09 s ; No ; No ;
; sclk ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0464 V ; 0.207 V ; 0.276 V ; 8.51e-10 s ; 8.52e-10 s ; No ; No ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0464 V ; 0.207 V ; 0.276 V ; 8.51e-10 s ; 8.52e-10 s ; No ; No ;
; MOSI_ESP32 ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0463 V ; 0.208 V ; 0.277 V ; 8.5e-10 s ; 8.53e-10 s ; No ; No ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0463 V ; 0.208 V ; 0.277 V ; 8.5e-10 s ; 8.53e-10 s ; No ; No ;
; cs_ESP32 ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0464 V ; 0.207 V ; 0.276 V ; 8.51e-10 s ; 8.52e-10 s ; No ; No ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0464 V ; 0.207 V ; 0.276 V ; 8.51e-10 s ; 8.52e-10 s ; No ; No ;
; sclk_ESP32 ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0463 V ; 0.208 V ; 0.277 V ; 8.5e-10 s ; 8.53e-10 s ; No ; No ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0463 V ; 0.208 V ; 0.277 V ; 8.5e-10 s ; 8.53e-10 s ; No ; No ;
; tx ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0464 V ; 0.207 V ; 0.276 V ; 8.51e-10 s ; 8.52e-10 s ; No ; No ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0464 V ; 0.207 V ; 0.276 V ; 8.51e-10 s ; 8.52e-10 s ; No ; No ;
; test_flag_led ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0464 V ; 0.207 V ; 0.276 V ; 8.51e-10 s ; 8.52e-10 s ; No ; No ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0464 V ; 0.207 V ; 0.276 V ; 8.51e-10 s ; 8.52e-10 s ; No ; No ;
; convert_flag_led ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0464 V ; 0.207 V ; 0.276 V ; 8.51e-10 s ; 8.52e-10 s ; No ; No ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0464 V ; 0.207 V ; 0.276 V ; 8.51e-10 s ; 8.52e-10 s ; No ; No ;
; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.49e-09 V ; 2.38 V ; -0.0505 V ; 0.23 V ; 0.155 V ; 4.84e-10 s ; 6.18e-10 s ; Yes ; No ; 2.32 V ; 7.49e-09 V ; 2.38 V ; -0.0505 V ; 0.23 V ; 0.155 V ; 4.84e-10 s ; 6.18e-10 s ; Yes ; No ;
+------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
+------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; mosi ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.018 V ; 0.27 V ; 0.216 V ; 1.11e-09 s ; 1.22e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.018 V ; 0.27 V ; 0.216 V ; 1.11e-09 s ; 1.22e-09 s ; Yes ; Yes ;
; cs_n ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.018 V ; 0.27 V ; 0.217 V ; 1.11e-09 s ; 1.22e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.018 V ; 0.27 V ; 0.217 V ; 1.11e-09 s ; 1.22e-09 s ; Yes ; Yes ;
; sclk ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ;
; MOSI_ESP32 ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0199 V ; 0.191 V ; 0.262 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0199 V ; 0.191 V ; 0.262 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ;
; cs_ESP32 ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ;
; sclk_ESP32 ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0199 V ; 0.191 V ; 0.262 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0199 V ; 0.191 V ; 0.262 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ;
; tx ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ;
; test_flag_led ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ;
; convert_flag_led ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ;
; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.88e-07 V ; 2.36 V ; -0.0211 V ; 0.162 V ; 0.122 V ; 6.58e-10 s ; 7.79e-10 s ; No ; Yes ; 2.32 V ; 7.88e-07 V ; 2.36 V ; -0.0211 V ; 0.162 V ; 0.122 V ; 6.58e-10 s ; 7.79e-10 s ; No ; Yes ;
+------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
+------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; mosi ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 8.93e-07 V ; 3.52 V ; -0.0321 V ; 0.324 V ; 0.176 V ; 6.87e-10 s ; 8.14e-10 s ; No ; Yes ; 3.46 V ; 8.93e-07 V ; 3.52 V ; -0.0321 V ; 0.324 V ; 0.176 V ; 6.87e-10 s ; 8.14e-10 s ; No ; Yes ;
; cs_n ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0325 V ; 0.324 V ; 0.176 V ; 6.87e-10 s ; 8.14e-10 s ; No ; Yes ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0325 V ; 0.324 V ; 0.176 V ; 6.87e-10 s ; 8.14e-10 s ; No ; Yes ;
; sclk ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.252 V ; 6.55e-10 s ; 6.68e-10 s ; No ; Yes ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.252 V ; 6.55e-10 s ; 6.68e-10 s ; No ; Yes ;
; MOSI_ESP32 ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.251 V ; 6.54e-10 s ; 6.68e-10 s ; No ; Yes ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.251 V ; 6.54e-10 s ; 6.68e-10 s ; No ; Yes ;
; cs_ESP32 ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.252 V ; 6.55e-10 s ; 6.68e-10 s ; No ; Yes ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.252 V ; 6.55e-10 s ; 6.68e-10 s ; No ; Yes ;
; sclk_ESP32 ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.251 V ; 6.54e-10 s ; 6.68e-10 s ; No ; Yes ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.251 V ; 6.54e-10 s ; 6.68e-10 s ; No ; Yes ;
; tx ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.252 V ; 6.55e-10 s ; 6.68e-10 s ; No ; Yes ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.252 V ; 6.55e-10 s ; 6.68e-10 s ; No ; Yes ;
; test_flag_led ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.252 V ; 6.55e-10 s ; 6.68e-10 s ; No ; Yes ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.252 V ; 6.55e-10 s ; 6.68e-10 s ; No ; Yes ;
; convert_flag_led ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.252 V ; 6.55e-10 s ; 6.68e-10 s ; No ; Yes ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.252 V ; 6.55e-10 s ; 6.68e-10 s ; No ; Yes ;
; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0395 V ; 0.361 V ; 0.109 V ; 3.1e-10 s ; 4.41e-10 s ; No ; Yes ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0395 V ; 0.361 V ; 0.109 V ; 3.1e-10 s ; 4.41e-10 s ; No ; Yes ;
+------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers ;
+----------------------------------------------------------+----------------------------------------------------------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+----------------------------------------------------------+----------------------------------------------------------+----------+----------+----------+----------+
; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 1138 ; 0 ; 0 ; 0 ;
; spi_master_2164:u_spi_master_2164|cs_n ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 0 ; 179 ; 0 ; 0 ;
; spi_master_2164:u_spi_master_2164|cs_n ; spi_master_2164:u_spi_master_2164|cs_n ; 0 ; 0 ; 0 ; 31 ;
+----------------------------------------------------------+----------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers ;
+----------------------------------------------------------+----------------------------------------------------------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+----------------------------------------------------------+----------------------------------------------------------+----------+----------+----------+----------+
; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 1138 ; 0 ; 0 ; 0 ;
; spi_master_2164:u_spi_master_2164|cs_n ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 0 ; 179 ; 0 ; 0 ;
; spi_master_2164:u_spi_master_2164|cs_n ; spi_master_2164:u_spi_master_2164|cs_n ; 0 ; 0 ; 0 ; 31 ;
+----------------------------------------------------------+----------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design
---------------
; Report RSKM ;
---------------
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+------------------------------------------------+
; Unconstrained Paths Summary ;
+---------------------------------+-------+------+
; Property ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 3 ; 3 ;
; Unconstrained Input Port Paths ; 139 ; 139 ;
; Unconstrained Output Ports ; 6 ; 6 ;
; Unconstrained Output Port Paths ; 6 ; 6 ;
+---------------------------------+-------+------+
+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Status Summary ;
+----------------------------------------------------------+----------------------------------------------------------+-----------+-------------+
; Target ; Clock ; Type ; Status ;
+----------------------------------------------------------+----------------------------------------------------------+-----------+-------------+
; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; Generated ; Constrained ;
; spi_master_2164:u_spi_master_2164|cs_n ; spi_master_2164:u_spi_master_2164|cs_n ; Base ; Constrained ;
; sys_clk ; sys_clk ; Base ; Constrained ;
+----------------------------------------------------------+----------------------------------------------------------+-----------+-------------+
+---------------------------------------------------------------------------------------------------+
; Unconstrained Input Ports ;
+------------+--------------------------------------------------------------------------------------+
; Input Port ; Comment ;
+------------+--------------------------------------------------------------------------------------+
; miso ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; rst_n ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; test_flag ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+------------+--------------------------------------------------------------------------------------+
+----------------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports ;
+------------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment ;
+------------------+---------------------------------------------------------------------------------------+
; convert_flag_led ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; cs_n ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; mosi ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; sclk ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; test_flag_led ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; tx ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+------------------+---------------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------------+
; Unconstrained Input Ports ;
+------------+--------------------------------------------------------------------------------------+
; Input Port ; Comment ;
+------------+--------------------------------------------------------------------------------------+
; miso ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; rst_n ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; test_flag ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+------------+--------------------------------------------------------------------------------------+
+----------------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports ;
+------------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment ;
+------------------+---------------------------------------------------------------------------------------+
; convert_flag_led ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; cs_n ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; mosi ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; sclk ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; test_flag_led ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; tx ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+------------------+---------------------------------------------------------------------------------------+
+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime TimeQuest Timing Analyzer
Info: Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
Info: Processing started: Thu Dec 11 18:00:37 2025
Info: Command: quartus_sta intan_m10 -c intan_m10
Info: qsta_default_script.tcl version: #3
Info (20032): Parallel compilation is enabled and will use up to 4 processors
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Critical Warning (332012): Synopsys Design Constraints File file not found: 'intan_m10.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained generated clocks found in the design. Calling "derive_pll_clocks -create_base_clocks"
Info (332110): Deriving PLL clocks
Info (332110): create_clock -period 83.333 -waveform {0.000 41.666} -name sys_clk sys_clk
Info (332110): create_generated_clock -source {clk_gen_inst|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 625 -multiply_by 6 -duty_cycle 50.00 -name {clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]} {clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]}
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332105): Deriving Clocks
Info (332105): create_clock -period 1.000 -name spi_master_2164:u_spi_master_2164|cs_n spi_master_2164:u_spi_master_2164|cs_n
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Info: Can't run Report Timing Closure Recommendations. The current device family is not supported.
Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case setup slack is -6.744
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -6.744 -6.744 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]
Info (332119): -0.642 -7.912 spi_master_2164:u_spi_master_2164|cs_n
Info (332146): Worst-case hold slack is 0.362
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.362 0.000 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 0.363 0.000 spi_master_2164:u_spi_master_2164|cs_n
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -1.487
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -1.487 -46.097 spi_master_2164:u_spi_master_2164|cs_n
Info (332119): 41.554 0.000 sys_clk
Info (332119): 4339.989 0.000 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]
Info (332114): Report Metastability: Found 1 synchronizer chains.
Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.
Info (332114): Number of Synchronizer Chains Found: 1
Info (332114): Shortest Synchronizer Chain: 2 Registers
Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000
Info (332114): Worst Case Available Settling Time: 17358.585 ns
Info (332114):
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case setup slack is -6.215
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -6.215 -6.215 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]
Info (332119): -0.556 -5.863 spi_master_2164:u_spi_master_2164|cs_n
Info (332146): Worst-case hold slack is 0.324
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.324 0.000 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 0.325 0.000 spi_master_2164:u_spi_master_2164|cs_n
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -1.487
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -1.487 -46.097 spi_master_2164:u_spi_master_2164|cs_n
Info (332119): 41.555 0.000 sys_clk
Info (332119): 4340.000 0.000 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]
Info (332114): Report Metastability: Found 1 synchronizer chains.
Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.
Info (332114): Number of Synchronizer Chains Found: 1
Info (332114): Shortest Synchronizer Chain: 2 Registers
Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000
Info (332114): Worst Case Available Settling Time: 17358.726 ns
Info (332114):
Info: Analyzing Fast 1200mV 0C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case setup slack is -2.312
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -2.312 -2.312 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 0.304 0.000 spi_master_2164:u_spi_master_2164|cs_n
Info (332146): Worst-case hold slack is 0.151
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 0.151 0.000 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]
Info (332119): 0.151 0.000 spi_master_2164:u_spi_master_2164|cs_n
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is -1.000
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -1.000 -31.000 spi_master_2164:u_spi_master_2164|cs_n
Info (332119): 41.180 0.000 sys_clk
Info (332119): 4340.041 0.000 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]
Info (332114): Report Metastability: Found 1 synchronizer chains.
Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.
Info (332114): Number of Synchronizer Chains Found: 1
Info (332114): Shortest Synchronizer Chain: 2 Registers
Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000
Info (332114): Worst Case Available Settling Time: 17359.966 ns
Info (332114):
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings
Info: Peak virtual memory: 4784 megabytes
Info: Processing ended: Thu Dec 11 18:00:41 2025
Info: Elapsed time: 00:00:04
Info: Total CPU time (on all processors): 00:00:03

89
puart2/output_files/intan_m10.sta.summary Normal file
View File

@@ -0,0 +1,89 @@
------------------------------------------------------------
TimeQuest Timing Analyzer Summary
------------------------------------------------------------
Type : Slow 1200mV 85C Model Setup 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]'
Slack : -6.744
TNS : -6.744
Type : Slow 1200mV 85C Model Setup 'spi_master_2164:u_spi_master_2164|cs_n'
Slack : -0.642
TNS : -7.912
Type : Slow 1200mV 85C Model Hold 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.362
TNS : 0.000
Type : Slow 1200mV 85C Model Hold 'spi_master_2164:u_spi_master_2164|cs_n'
Slack : 0.363
TNS : 0.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'spi_master_2164:u_spi_master_2164|cs_n'
Slack : -1.487
TNS : -46.097
Type : Slow 1200mV 85C Model Minimum Pulse Width 'sys_clk'
Slack : 41.554
TNS : 0.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]'
Slack : 4339.989
TNS : 0.000
Type : Slow 1200mV 0C Model Setup 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]'
Slack : -6.215
TNS : -6.215
Type : Slow 1200mV 0C Model Setup 'spi_master_2164:u_spi_master_2164|cs_n'
Slack : -0.556
TNS : -5.863
Type : Slow 1200mV 0C Model Hold 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.324
TNS : 0.000
Type : Slow 1200mV 0C Model Hold 'spi_master_2164:u_spi_master_2164|cs_n'
Slack : 0.325
TNS : 0.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'spi_master_2164:u_spi_master_2164|cs_n'
Slack : -1.487
TNS : -46.097
Type : Slow 1200mV 0C Model Minimum Pulse Width 'sys_clk'
Slack : 41.555
TNS : 0.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]'
Slack : 4340.000
TNS : 0.000
Type : Fast 1200mV 0C Model Setup 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]'
Slack : -2.312
TNS : -2.312
Type : Fast 1200mV 0C Model Setup 'spi_master_2164:u_spi_master_2164|cs_n'
Slack : 0.304
TNS : 0.000
Type : Fast 1200mV 0C Model Hold 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]'
Slack : 0.151
TNS : 0.000
Type : Fast 1200mV 0C Model Hold 'spi_master_2164:u_spi_master_2164|cs_n'
Slack : 0.151
TNS : 0.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'spi_master_2164:u_spi_master_2164|cs_n'
Slack : -1.000
TNS : -31.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'sys_clk'
Slack : 41.180
TNS : 0.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]'
Slack : 4340.041
TNS : 0.000
------------------------------------------------------------