TJU-SUN-LAB/waveform_acquisition_FPGA_code
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2025-12-11 18:35:48 +08:00
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Fitter Status : Successful - Thu Dec 11 18:00:31 2025
Quartus Prime Version : 17.1.0 Build 590 10/25/2017 SJ Lite Edition
Revision Name : intan_m10
Top-level Entity Name : ddr_ctrl
Family : MAX 10
Device : 10M08SAM153C8G
Timing Models : Final
Total logic elements : 183 / 8,064 ( 2 % )
Total combinational functions : 123 / 8,064 ( 2 % )
Dedicated logic registers : 135 / 8,064 ( 2 % )
Total registers : 135
Total pins : 13 / 112 ( 12 % )
Total virtual pins : 0
Total memory bits : 0 / 387,072 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 48 ( 0 % )
Total PLLs : 1 / 1 ( 100 % )
UFM blocks : 0 / 1 ( 0 % )
ADC blocks : 0 / 1 ( 0 % )