TJU-SUN-LAB/waveform_acquisition_FPGA_code
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2025-12-11 18:35:48 +08:00
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Analysis & Synthesis Status : Successful - Thu Dec 11 18:00:25 2025
Quartus Prime Version : 17.1.0 Build 590 10/25/2017 SJ Lite Edition
Revision Name : intan_m10
Top-level Entity Name : ddr_ctrl
Family : MAX 10
Total logic elements : 198
Total combinational functions : 121
Dedicated logic registers : 135
Total registers : 135
Total pins : 13
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 1
UFM blocks : 0
ADC blocks : 0