TJU-SUN-LAB/waveform_acquisition_FPGA_code
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82
puart2/uart_tx_restored/Verilog1.v Normal file
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module uart_tx (
input wire clk, // 时钟信号
input wire rst, // 复位信号
input wire tx_start, // 开始发送信号
input wire [15:0] tx_data, // 顶层输入的16位待发送数据
output wire tx, // 串行输出信号
output reg tx_done // 发送完成信号
);
parameter BAUD_RATE = 115200;
parameter CLOCK_FREQ = 12000000; // 12 MHz时钟
localparam integer BAUD_TICK = CLOCK_FREQ / BAUD_RATE; // 波特率计数，计算出每个比特的时钟周期数
// 波特率计数器
reg [15:0] baud_counter;
reg [7:0] data_to_send; // 用于存储当前要发送的8位数据
reg [1:0] byte_select; // 控制发送高8位还是低8位数据
// 发送状态机定义
reg [3:0] tx_state;
reg [9:0] tx_shift_reg; // 10位移位寄存器（8位数据 + 起始位 + 停止位）
reg [3:0] tx_bit_counter; // 用于计数8位数据发送的每一位
// 波特率计数器更新
always @(posedge clk or negedge rst) begin
if (!rst)
baud_counter <= 0;
else if (baud_counter == BAUD_TICK - 1)
baud_counter <= 0;
else
baud_counter <= baud_counter + 1;
end
// UART发送逻辑
always @(posedge clk or negedge rst) begin
if (!rst) begin
tx_state <= 0;
tx_done <= 0;
byte_select <= 0;
tx_shift_reg <= 10'b1111111111; // 空闲状态（全1表示停止位）
end
else if (baud_counter == BAUD_TICK - 1) begin
case (tx_state)
0: begin
if (tx_start) begin
// 根据 byte_select 选择发送高8位或低8位数据
if (byte_select == 0)
data_to_send <= tx_data[15:8]; // 发送低8位
else
data_to_send <= tx_data[7:0]; // 发送高8位
// 将要发送的8位数据加上起始位（0）和停止位（1）
tx_shift_reg <= {1'b1, data_to_send, 1'b0}; // 1位停止位，8位数据，1位起始位
tx_bit_counter <= 0;
tx_state <= 1;
tx_done <= 0;
end
end
1: begin
// 每个波特率时钟周期发送一位
if (tx_bit_counter == 9) begin // 所有位发送完成后回到空闲状态
if (byte_select == 0)
byte_select <= 1; // 切换到发送高8位
else begin
byte_select <= 0; // 重置为低8位
tx_done <= 1; // 完成整个16位数据的发送
end
tx_state <= 0;
end
else begin
tx_shift_reg <= {1'b1, tx_shift_reg[9:1]}; // 右移移位寄存器
tx_bit_counter <= tx_bit_counter + 1;
end
end
endcase
end
end
assign tx = tx_shift_reg[0]; // 串行输出当前最低位
endmodule

812
puart2/uart_tx_restored/assignment_defaults.qdf Normal file
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# Default value changes
#
# In 16.1, the default value of assignment OCP_HW_EVAL has changed to "Enable"
# In 15.0, the default value of assignment FAMILY has changed to "Cyclone V"
# In 10.0, the default value of assignment OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING has changed to "Normal"
# In 9.1, the default value of assignment PARALLEL_SYNTHESIS has changed to "On"
# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Arria II GZ"
# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Cyclone 10 LP"
# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Cyclone IV GX"
# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Stratix IV"
# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Cyclone IV E"
# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Arria II GX"
# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Arria II GZ"
# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Cyclone 10 LP"
# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Cyclone IV GX"
# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Stratix IV"
# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Cyclone IV E"
# In 9.1, the default value of assignment SYNTH_TIMING_DRIVEN_SYNTHESIS has changed to "On" for device family "Arria II GX"
# In 9.0, the default value of assignment ENABLE_BENEFICIAL_SKEW_OPTIMIZATION has changed to "On"
# In 8.1, the default value of assignment OPTIMIZE_HOLD_TIMING has changed to "All Paths" for device family "Arria II GZ"
# In 8.1, the default value of assignment OPTIMIZE_HOLD_TIMING has changed to "All Paths" for device family "Cyclone 10 LP"
# In 8.1, the default value of assignment OPTIMIZE_HOLD_TIMING has changed to "All Paths" for device family "Cyclone IV GX"
# In 8.1, the default value of assignment OPTIMIZE_HOLD_TIMING has changed to "All Paths" for device family "Stratix IV"
# In 8.1, the default value of assignment OPTIMIZE_HOLD_TIMING has changed to "All Paths" for device family "Cyclone IV E"
# In 8.1, the default value of assignment OPTIMIZE_HOLD_TIMING has changed to "All Paths" for device family "Arria II GX"
# In 8.0, the default value of assignment USE_CONFIGURATION_DEVICE has changed to "Off" for device family "Cyclone 10 LP"
# In 8.0, the default value of assignment USE_CONFIGURATION_DEVICE has changed to "Off" for device family "Cyclone IV E"
# In 8.0, the default value of assignment USE_CONFIGURATION_DEVICE has changed to "Off" for device family "Cyclone IV GX"
# In 7.2, the default value of assignment POWER_REPORT_SIGNAL_ACTIVITY has changed to "Off"
# In 7.2, the default value of assignment POWER_REPORT_POWER_DISSIPATION has changed to "Off"
# In 5.1, the default value of assignment ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS has changed to "On"
# In 5.1, the default value of assignment STRATIXII_MRAM_COMPATIBILITY has changed to "Off"
# In 5.0, the default value of assignment SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF has changed to "On"
# In 4.1, the default value of assignment FITTER_EFFORT has changed to "Auto Fit"
set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off
set_global_assignment -name IP_COMPONENT_INTERNAL Off
set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
set_global_assignment -name HC_OUTPUT_DIR hc_output
set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
set_global_assignment -name REVISION_TYPE Base -family "Arria V"
set_global_assignment -name REVISION_TYPE Base -family "Stratix V"
set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ"
set_global_assignment -name REVISION_TYPE Base -family "Cyclone V"
set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
set_global_assignment -name DO_COMBINED_ANALYSIS Off
set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off
set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off
set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "MAX 10"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria 10"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V"
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone 10 LP"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "MAX 10"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria 10"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V"
set_global_assignment -name OPTIMIZATION_MODE Balanced
set_global_assignment -name ALLOW_REGISTER_MERGING On
set_global_assignment -name ALLOW_REGISTER_DUPLICATION On
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V"
set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Cyclone 10 LP"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX 10"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix IV"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV E"
set_global_assignment -name TIMEQUEST_SPECTRA_Q ON -family "Arria 10"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX V"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Stratix V"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria V GZ"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "MAX II"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GX"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Arria II GZ"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone IV GX"
set_global_assignment -name TIMEQUEST_SPECTRA_Q OFF -family "Cyclone V"
set_global_assignment -name MUX_RESTRUCTURE Auto
set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
set_global_assignment -name ENABLE_IP_DEBUG Off
set_global_assignment -name SAVE_DISK_SPACE On
set_global_assignment -name OCP_HW_EVAL Enable
set_global_assignment -name DEVICE_FILTER_PACKAGE Any
set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name TRUE_WYSIWYG_FLOW Off
set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
set_global_assignment -name STATE_MACHINE_PROCESSING Auto
set_global_assignment -name SAFE_STATE_MACHINE Off
set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
set_global_assignment -name PARALLEL_SYNTHESIS On
set_global_assignment -name DSP_BLOCK_BALANCING Auto
set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
set_global_assignment -name NOT_GATE_PUSH_BACK On
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
set_global_assignment -name IGNORE_CARRY_BUFFERS Off
set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
set_global_assignment -name IGNORE_LCELL_BUFFERS Off
set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
set_global_assignment -name IGNORE_SOFT_BUFFERS On
set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
set_global_assignment -name AUTO_GLOBAL_OE_MAX On
set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name ALLOW_XOR_GATE_USAGE On
set_global_assignment -name AUTO_LCELL_INSERTION On
set_global_assignment -name CARRY_CHAIN_LENGTH 48
set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
set_global_assignment -name CASCADE_CHAIN_LENGTH 2
set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
set_global_assignment -name AUTO_CARRY_CHAINS On
set_global_assignment -name AUTO_CASCADE_CHAINS On
set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
set_global_assignment -name AUTO_ROM_RECOGNITION On
set_global_assignment -name AUTO_RAM_RECOGNITION On
set_global_assignment -name AUTO_DSP_RECOGNITION On
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
set_global_assignment -name STRICT_RAM_RECOGNITION Off
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
set_global_assignment -name FORCE_SYNCH_CLEAR Off
set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
set_global_assignment -name AUTO_RESOURCE_SHARING Off
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
set_global_assignment -name MAX7000_FANIN_PER_CELL 100
set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
set_global_assignment -name REPORT_PARAMETER_SETTINGS On
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
set_global_assignment -name HDL_MESSAGE_LEVEL Level2
set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100
set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
set_global_assignment -name BLOCK_DESIGN_NAMING Auto
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
set_global_assignment -name SYNTHESIS_EFFORT Auto
set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
set_global_assignment -name MAX_LABS "-1 (Unlimited)"
set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
set_global_assignment -name PRPOF_ID Off
set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On
set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off
set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
set_global_assignment -name AUTO_MERGE_PLLS On
set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
set_global_assignment -name TXPMA_SLEW_RATE Low
set_global_assignment -name ADCE_ENABLED Auto
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
set_global_assignment -name SPECTRAQ_PHYSICAL_SYNTHESIS Off
set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
set_global_assignment -name DEVICE AUTO
set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
set_global_assignment -name ENABLE_NCEO_OUTPUT Off
set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
set_global_assignment -name STRATIX_UPDATE_MODE Standard
set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
set_global_assignment -name CVP_MODE Off
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V"
set_global_assignment -name VID_OPERATION_MODE "PMBus Slave"
set_global_assignment -name USE_CONF_DONE AUTO
set_global_assignment -name USE_PWRMGT_SCL AUTO
set_global_assignment -name USE_PWRMGT_SDA AUTO
set_global_assignment -name USE_PWRMGT_ALERT AUTO
set_global_assignment -name USE_INIT_DONE AUTO
set_global_assignment -name USE_CVP_CONFDONE AUTO
set_global_assignment -name USE_SEU_ERROR AUTO
set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name USER_START_UP_CLOCK Off
set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off
set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
set_global_assignment -name ENABLE_VREFA_PIN Off
set_global_assignment -name ENABLE_VREFB_PIN Off
set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
set_global_assignment -name INIT_DONE_OPEN_DRAIN On
set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
set_global_assignment -name ENABLE_CONFIGURATION_PINS On
set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
set_global_assignment -name ENABLE_NCE_PIN Off
set_global_assignment -name ENABLE_BOOT_SEL_PIN On
set_global_assignment -name CRC_ERROR_CHECKING Off
set_global_assignment -name INTERNAL_SCRUBBING Off
set_global_assignment -name PR_ERROR_OPEN_DRAIN On
set_global_assignment -name PR_READY_OPEN_DRAIN On
set_global_assignment -name ENABLE_CVP_CONFDONE Off
set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
set_global_assignment -name OPTIMIZE_SSN Off
set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
set_global_assignment -name ECO_OPTIMIZE_TIMING Off
set_global_assignment -name ECO_REGENERATE_REPORT Off
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
set_global_assignment -name SEED 1
set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
set_global_assignment -name SLOW_SLEW_RATE Off
set_global_assignment -name PCI_IO Off
set_global_assignment -name TURBO_BIT On
set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
set_global_assignment -name NORMAL_LCELL_INSERT On
set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
set_global_assignment -name AUTO_TURBO_BIT ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
set_global_assignment -name FITTER_EFFORT "Auto Fit"
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
set_global_assignment -name AUTO_GLOBAL_CLOCK On
set_global_assignment -name AUTO_GLOBAL_OE On
set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
set_global_assignment -name ENABLE_HOLD_BACK_OFF On
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
set_global_assignment -name PR_DONE_OPEN_DRAIN On
set_global_assignment -name NCEO_OPEN_DRAIN On
set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
set_global_assignment -name ENABLE_PR_PINS Off
set_global_assignment -name RESERVE_PR_PINS Off
set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
set_global_assignment -name PR_PINS_OPEN_DRAIN Off
set_global_assignment -name CLAMPING_DIODE Off
set_global_assignment -name TRI_STATE_SPI_PINS Off
set_global_assignment -name UNUSED_TSD_PINS_GND Off
set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
set_global_assignment -name SEU_FIT_REPORT Off
set_global_assignment -name HYPER_RETIMER Off -family "Arria 10"
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
set_global_assignment -name COMPRESSION_MODE Off
set_global_assignment -name CLOCK_SOURCE Internal
set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
set_global_assignment -name SECURITY_BIT Off
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130"
set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery"
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0
set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
set_global_assignment -name GENERATE_TTF_FILE Off
set_global_assignment -name GENERATE_RBF_FILE Off
set_global_assignment -name GENERATE_HEX_FILE Off
set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
set_global_assignment -name AUTO_RESTART_CONFIGURATION On
set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP"
set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V"
set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
set_global_assignment -name POR_SCHEME "Instant ON"
set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
set_global_assignment -name POF_VERIFY_PROTECT Off
set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
set_global_assignment -name GENERATE_PMSF_FILES On
set_global_assignment -name START_TIME 0ns
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
set_global_assignment -name SETUP_HOLD_DETECTION Off
set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
set_global_assignment -name CHECK_OUTPUTS Off
set_global_assignment -name SIMULATION_COVERAGE On
set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
set_global_assignment -name GLITCH_DETECTION Off
set_global_assignment -name GLITCH_INTERVAL 1ns
set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
set_global_assignment -name DRC_TOP_FANOUT 50
set_global_assignment -name DRC_FANOUT_EXCEEDING 30
set_global_assignment -name DRC_GATED_CLOCK_FEED 30
set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
set_global_assignment -name ENABLE_DRC_SETTINGS Off
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
set_global_assignment -name MERGE_HEX_FILE Off
set_global_assignment -name GENERATE_SVF_FILE Off
set_global_assignment -name GENERATE_ISC_FILE Off
set_global_assignment -name GENERATE_JAM_FILE Off
set_global_assignment -name GENERATE_JBC_FILE Off
set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
set_global_assignment -name HPS_EARLY_IO_RELEASE Off
set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
set_global_assignment -name POWER_USE_PVA On
set_global_assignment -name POWER_USE_INPUT_FILE "No File"
set_global_assignment -name POWER_USE_INPUT_FILES Off
set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
set_global_assignment -name POWER_TJ_VALUE 25
set_global_assignment -name POWER_USE_TA_VALUE 25
set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
set_global_assignment -name POWER_BOARD_TEMPERATURE 25
set_global_assignment -name POWER_HPS_ENABLE Off
set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
set_global_assignment -name IGNORE_PARTITIONS Off
set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
set_global_assignment -name RTLV_GROUP_RELATED_NODES On
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
set_global_assignment -name EQC_BBOX_MERGE On
set_global_assignment -name EQC_LVDS_MERGE On
set_global_assignment -name EQC_RAM_UNMERGING On
set_global_assignment -name EQC_DFF_SS_EMULATION On
set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
set_global_assignment -name EQC_STRUCTURE_MATCHING On
set_global_assignment -name EQC_AUTO_BREAK_CONE On
set_global_assignment -name EQC_POWER_UP_COMPARE Off
set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
set_global_assignment -name EQC_AUTO_INVERSION On
set_global_assignment -name EQC_AUTO_TERMINATE On
set_global_assignment -name EQC_SUB_CONE_REPORT Off
set_global_assignment -name EQC_RENAMING_RULES On
set_global_assignment -name EQC_PARAMETER_CHECK On
set_global_assignment -name EQC_AUTO_PORTSWAP On
set_global_assignment -name EQC_DETECT_DONT_CARES On
set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
set_global_assignment -name EDA_EXTRA_ELAB_OPTION "\"\"" -section_id ?
set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ?
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ?
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?

10
puart2/uart_tx_restored/clk_gen.ppf Normal file
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@@ -0,0 +1,10 @@
<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="MAX 10" variation_name="clk_gen" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="c0" direction="output" scope="external" source="clock" />
<pin name="c1" direction="output" scope="external" source="clock" />
</global>
</pinplan>

7
puart2/uart_tx_restored/clk_gen.qip Normal file
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@@ -0,0 +1,7 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "23.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "clk_gen.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clk_gen_inst.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clk_gen_bb.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clk_gen.ppf"]

332
puart2/uart_tx_restored/clk_gen.v Normal file
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@@ -0,0 +1,332 @@
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: clk_gen.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 23.1std.1 Build 993 05/14/2024 SC Lite Edition
// ************************************************************
//Copyright (C) 2024 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module clk_gen (
inclk0,
c0,
c1);
input inclk0;
output c0;
output c1;
wire [0:0] sub_wire2 = 1'h0;
wire [4:0] sub_wire3;
wire sub_wire0 = inclk0;
wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
wire [1:1] sub_wire5 = sub_wire3[1:1];
wire [0:0] sub_wire4 = sub_wire3[0:0];
wire c0 = sub_wire4;
wire c1 = sub_wire5;
altpll altpll_component (
.inclk (sub_wire1),
.clk (sub_wire3),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 625,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 6,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 625,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 12,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 83333,
altpll_component.intended_device_family = "MAX 10",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=clk_gen",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "104"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "52"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.115200"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "0.230400"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "12.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.11520000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "0.23040000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clk_gen.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "625"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "6"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "625"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "12"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "83333"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_bb.v TRUE
// Retrieval info: CBX_MODULE_PREFIX: ON

219
puart2/uart_tx_restored/clk_gen_bb.v Normal file
View File

@@ -0,0 +1,219 @@
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: clk_gen.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 23.1std.1 Build 993 05/14/2024 SC Lite Edition
// ************************************************************
//Copyright (C) 2024 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
module clk_gen (
inclk0,
c0,
c1);
input inclk0;
output c0;
output c1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "104"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "52"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.115200"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "0.230400"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "12.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.11520000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "0.23040000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clk_gen.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "625"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "6"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "625"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "12"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "83333"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_bb.v TRUE
// Retrieval info: CBX_MODULE_PREFIX: ON

5
puart2/uart_tx_restored/clk_gen_inst.v Normal file
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@@ -0,0 +1,5 @@
clk_gen clk_gen_inst (
.inclk0 ( inclk0_sig ),
.c0 ( c0_sig ),
.c1 ( c1_sig )
);

9
puart2/uart_tx_restored/clkgen.ppf Normal file
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@@ -0,0 +1,9 @@
<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="MAX 10" variation_name="clkgen" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="c0" direction="output" scope="external" source="clock" />
</global>
</pinplan>

7
puart2/uart_tx_restored/clkgen.qip Normal file
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@@ -0,0 +1,7 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "17.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "clkgen.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clkgen_inst.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clkgen_bb.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clkgen.ppf"]

305
puart2/uart_tx_restored/clkgen.v Normal file
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// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: clkgen.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.1.0 Build 590 10/25/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module clkgen (
inclk0,
c0);
input inclk0;
output c0;
wire [0:0] sub_wire2 = 1'h0;
wire [4:0] sub_wire3;
wire sub_wire0 = inclk0;
wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
wire [0:0] sub_wire4 = sub_wire3[0:0];
wire c0 = sub_wire4;
altpll altpll_component (
.inclk (sub_wire1),
.clk (sub_wire3),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 6,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 83333,
altpll_component.intended_device_family = "MAX 10",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=clkgen",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "6"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "2.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "12.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clkgen.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "6"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "83333"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

198
puart2/uart_tx_restored/clkgen_bb.v Normal file
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@@ -0,0 +1,198 @@
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: clkgen.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.1.0 Build 590 10/25/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
module clkgen (
inclk0,
c0);
input inclk0;
output c0;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "6"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "2.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "12.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clkgen.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "6"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "83333"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

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puart2/uart_tx_restored/clkgen_inst.v Normal file
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clkgen clkgen_inst (
.inclk0 ( inclk0_sig ),
.c0 ( c0_sig )
);

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puart2/uart_tx_restored/db/.ipregen.qmsg Normal file
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{ "Info" "IIPMAN_IPRGEN_BACKUP_FILE" "clk_gen.v clk_gen.BAK.v " "Backing up file \"clk_gen.v\" to \"clk_gen.BAK.v\"" { } { } 0 11902 "Backing up file \"%1!s!\" to \"%2!s!\"" 0 0 "Shell" 0 -1 1765006761527 ""}
{ "Info" "IIPMAN_IPRGEN_START" "ALTPLL clk_gen.v " "Started upgrading IP component ALTPLL with file \"clk_gen.v\"" { } { } 0 11837 "Started upgrading IP component %1!s! with file \"%2!s!\"" 0 0 "Shell" 0 -1 1765006761528 ""}
{ "Info" "IIPMAN_IPRGEN_SUCCESSFUL" "ALTPLL clk_gen.v " "Completed upgrading IP component ALTPLL with file \"clk_gen.v\"" { } { } 0 11131 "Completed upgrading IP component %1!s! with file \"%2!s!\"" 0 0 "Shell" 0 -1 1765006763502 ""}
{ "Info" "IQEXE_TCL_SCRIPT_STATUS" "f:/quartus_prime_lite/quartus/common/tcl/internal/ip_regen/ip_regen.tcl " "Evaluation of Tcl script f:/quartus_prime_lite/quartus/common/tcl/internal/ip_regen/ip_regen.tcl was successful" { } { } 0 23030 "Evaluation of Tcl script %1!s! was successful" 0 0 "Shell" 0 -1 1765006763533 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Shell 0 s 0 s Quartus Prime " "Quartus Prime Shell was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4867 " "Peak virtual memory: 4867 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1765006763533 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 6 15:39:23 2025 " "Processing ended: Sat Dec 6 15:39:23 2025" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1765006763533 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1765006763533 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1765006763533 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Shell" 0 -1 1765006763533 ""}

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//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=625 clk0_duty_cycle=50 clk0_multiply_by=6 clk0_phase_shift="0" clk1_divide_by=625 clk1_duty_cycle=50 clk1_multiply_by=12 clk1_phase_shift="0" compensate_clock="CLK0" device_family="MAX 10" inclk0_input_frequency=83333 intended_device_family="MAX 10" lpm_hint="CBX_MODULE_PREFIX=clk_gen" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 clk inclk CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
//VERSION_BEGIN 23.1 cbx_altclkbuf 2024:05:14:17:57:37:SC cbx_altiobuf_bidir 2024:05:14:17:57:38:SC cbx_altiobuf_in 2024:05:14:17:57:38:SC cbx_altiobuf_out 2024:05:14:17:57:38:SC cbx_altpll 2024:05:14:17:57:38:SC cbx_cycloneii 2024:05:14:17:57:38:SC cbx_lpm_add_sub 2024:05:14:17:57:38:SC cbx_lpm_compare 2024:05:14:17:57:38:SC cbx_lpm_counter 2024:05:14:17:57:37:SC cbx_lpm_decode 2024:05:14:17:57:37:SC cbx_lpm_mux 2024:05:14:17:57:37:SC cbx_mgl 2024:05:14:17:57:46:SC cbx_nadder 2024:05:14:17:57:38:SC cbx_stratix 2024:05:14:17:57:38:SC cbx_stratixii 2024:05:14:17:57:38:SC cbx_stratixiii 2024:05:14:17:57:38:SC cbx_stratixv 2024:05:14:17:57:38:SC cbx_util_mgl 2024:05:14:17:57:38:SC VERSION_END
//CBXI_INSTANCE_NAME="ddr_ctrl_clk_gen_clk_gen_inst_altpll_altpll_component"
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 2024 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and any partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors. Please
// refer to the applicable agreement for further details, at
// https://fpgasoftware.intel.com/eula.
//synthesis_resources = fiftyfivenm_pll 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module clk_gen_altpll
(
clk,
inclk) /* synthesis synthesis_clearbox=1 */;
output [4:0] clk;
input [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] wire_pll1_clk;
wire wire_pll1_fbout;
fiftyfivenm_pll pll1
(
.activeclock(),
.clk(wire_pll1_clk),
.clkbad(),
.fbin(wire_pll1_fbout),
.fbout(wire_pll1_fbout),
.inclk(inclk),
.locked(),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll1.bandwidth_type = "auto",
pll1.clk0_divide_by = 625,
pll1.clk0_duty_cycle = 50,
pll1.clk0_multiply_by = 6,
pll1.clk0_phase_shift = "0",
pll1.clk1_divide_by = 625,
pll1.clk1_duty_cycle = 50,
pll1.clk1_multiply_by = 12,
pll1.clk1_phase_shift = "0",
pll1.compensate_clock = "clk0",
pll1.inclk0_input_frequency = 83333,
pll1.operation_mode = "normal",
pll1.pll_type = "auto",
pll1.lpm_type = "fiftyfivenm_pll";
assign
clk = {wire_pll1_clk[4:0]};
endmodule //clk_gen_altpll
//VALID FILE

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1765010718841 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition " "Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1765010718841 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 6 16:45:18 2025 " "Processing started: Sat Dec 6 16:45:18 2025" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1765010718841 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1765010718841 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1765010718841 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1765010719500 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1765010719525 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4687 " "Peak virtual memory: 4687 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1765010719804 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 6 16:45:19 2025 " "Processing ended: Sat Dec 6 16:45:19 2025" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1765010719804 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1765010719804 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1765010719804 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1765010719804 ""}

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puart2/uart_tx_restored/db/intan_m10.asm_labs.ddb Normal file
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puart2/uart_tx_restored/db/intan_m10.cmp.logdb Normal file
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v1
IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os.,Critical,0 such failures found.,,I/O,,
IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
IO_RULES_MATRIX,Total Pass,13;0;13;0;0;13;13;0;13;13;0;3;0;0;4;0;3;4;0;0;0;3;0;0;0;0;0;13;0;0,
IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,Total Inapplicable,0;13;0;13;13;0;0;13;0;0;13;10;13;13;9;13;10;9;13;13;13;10;13;13;13;13;13;0;13;13,
IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,miso,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,mosi,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,cs_n,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,sclk,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,MOSI_ESP32,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,cs_ESP32,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,sclk_ESP32,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,tx,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,test_flag_led,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,convert_flag_led,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,test_flag,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,rst_n,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,sys_clk,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_SUMMARY,Total I/O Rules,30,
IO_RULES_SUMMARY,Number of I/O Rules Passed,12,
IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18,

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puart2/uart_tx_restored/db/intan_m10.db_info Normal file
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Quartus_Version = Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition
Version_Index = 570679552
Creation_Time = Sat Dec 6 15:42:15 2025

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puart2/uart_tx_restored/db/intan_m10.fit.qmsg Normal file
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{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "4 " "Parallel compilation is enabled and will use up to 4 processors" { } { } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Fitter" 0 -1 1765010713366 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "intan_m10 10M08SAM153C8G " "Selected device 10M08SAM153C8G for design \"intan_m10\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1765010713373 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1765010713403 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1765010713403 ""}
{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|pll1 MAX 10 PLL " "Implemented PLL \"clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|pll1\" as MAX 10 PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] 6 625 0 0 " "Implementing clock multiplication of 6, clock division of 625, and phase shift of 0 degrees (0 ps) for clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/clk_gen_altpll.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/db/clk_gen_altpll.v" 44 -1 0 } } { "" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 84 14177 15141 0 0 "" 0 "" "" } } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Design Software" 0 -1 1765010713448 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] 12 625 0 0 " "Implementing clock multiplication of 12, clock division of 625, and phase shift of 0 degrees (0 ps) for clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] port" { } { { "db/clk_gen_altpll.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/db/clk_gen_altpll.v" 44 -1 0 } } { "" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 85 14177 15141 0 0 "" 0 "" "" } } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Design Software" 0 -1 1765010713448 ""} } { { "db/clk_gen_altpll.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/db/clk_gen_altpll.v" 44 -1 0 } } { "" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 84 14177 15141 0 0 "" 0 "" "" } } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1765010713448 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1765010713496 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1765010713504 ""}
{ "Critical Warning" "WFCUDA_FCUDA_SPS_DEVICE_POWER_LIMITATION" "" "Review the Power Analyzer report file (<design>.pow.rpt) to ensure your design is within the maximum power utilization limit of the single power-supply target device and to avoid functional failures." { } { } 1 16562 "Review the Power Analyzer report file (<design>.pow.rpt) to ensure your design is within the maximum power utilization limit of the single power-supply target device and to avoid functional failures." 0 0 "Fitter" 0 -1 1765010713567 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M08SAM153C8GES " "Device 10M08SAM153C8GES is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1765010713577 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M04SAM153C8G " "Device 10M04SAM153C8G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1765010713577 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1765010713577 ""}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "8 " "Fitter converted 8 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TMS~ G1 " "Pin ~ALTERA_TMS~ is reserved at location G1" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { ~ALTERA_TMS~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 326 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765010713578 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TCK~ J1 " "Pin ~ALTERA_TCK~ is reserved at location J1" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { ~ALTERA_TCK~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 328 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765010713578 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDI~ H5 " "Pin ~ALTERA_TDI~ is reserved at location H5" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDI~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 330 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765010713578 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDO~ H4 " "Pin ~ALTERA_TDO~ is reserved at location H4" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDO~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 332 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765010713578 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONFIG_SEL~ D8 " "Pin ~ALTERA_CONFIG_SEL~ is reserved at location D8" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONFIG_SEL~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 334 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765010713578 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCONFIG~ E8 " "Pin ~ALTERA_nCONFIG~ is reserved at location E8" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCONFIG~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 336 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765010713578 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nSTATUS~ D6 " "Pin ~ALTERA_nSTATUS~ is reserved at location D6" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { ~ALTERA_nSTATUS~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 338 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765010713578 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONF_DONE~ E6 " "Pin ~ALTERA_CONF_DONE~ is reserved at location E6" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONF_DONE~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 340 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765010713578 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1765010713578 ""}
{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" { } { } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1765010713579 ""}
{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1765010713579 ""}
{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1765010713579 ""}
{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1765010713579 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1765010713579 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "intan_m10.sdc " "Synopsys Design Constraints File file not found: 'intan_m10.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1765010714019 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "generated clocks " "No user constrained generated clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1765010714020 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1765010714020 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1765010714022 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1765010714022 ""}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1765010714023 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C1 of PLL_1) " "Automatically promoted node clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C1 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1765010714038 ""} } { { "db/clk_gen_altpll.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/db/clk_gen_altpll.v" 78 -1 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 84 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1765010714038 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C3 of PLL_1) " "Automatically promoted node clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C3 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1765010714038 ""} } { { "db/clk_gen_altpll.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/db/clk_gen_altpll.v" 78 -1 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 84 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1765010714038 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "spi_master_2164:u_spi_master_2164\|cs_n " "Automatically promoted node spi_master_2164:u_spi_master_2164\|cs_n " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1765010714038 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "cs_n~output " "Destination node cs_n~output" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 9 0 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 307 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1765010714038 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1765010714038 ""} } { { "spi_master_2164.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/spi_master_2164.v" 11 -1 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 81 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1765010714038 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1765010714309 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1765010714309 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1765010714310 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1765010714310 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1765010714311 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1765010714311 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1765010714311 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1765010714311 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1765010714322 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1765010714323 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1765010714323 ""}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_tx " "Node \"UART_tx\" is assigned to location or region, but does not exist in design" { } { { "f:/quartus_prime_lite/quartus/bin64/Assignment Editor.qase" "" { Assignment "f:/quartus_prime_lite/quartus/bin64/Assignment Editor.qase" 1 { { 0 "UART_tx" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1765010714344 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1765010714344 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1765010714344 ""}
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1765010714347 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1765010714788 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1765010714827 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1765010714838 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1765010715223 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1765010715223 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1765010715586 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X21_Y0 X31_Y12 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X21_Y0 to location X31_Y12" { } { { "loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X21_Y0 to location X31_Y12"} { { 12 { 0 ""} 21 0 11 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1765010715945 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1765010715945 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1765010716265 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1765010716265 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1765010716268 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.21 " "Total time spent on timing analysis during the Fitter is 0.21 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1765010716415 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1765010716423 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1765010716604 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1765010716605 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1765010716881 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1765010717319 ""}
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1765010717431 ""}
{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "4 MAX 10 " "4 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing MAX 10 Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "miso 3.3-V LVCMOS R3 " "Pin miso uses I/O standard 3.3-V LVCMOS at R3" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { miso } } } { "f:/quartus_prime_lite/quartus/bin64/Assignment Editor.qase" "" { Assignment "f:/quartus_prime_lite/quartus/bin64/Assignment Editor.qase" 1 { { 0 "miso" } } } } { "ddr_ctrl.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 7 0 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 12 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1765010717433 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "test_flag 3.3-V LVCMOS J12 " "Pin test_flag uses I/O standard 3.3-V LVCMOS at J12" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { test_flag } } } { "f:/quartus_prime_lite/quartus/bin64/Assignment Editor.qase" "" { Assignment "f:/quartus_prime_lite/quartus/bin64/Assignment Editor.qase" 1 { { 0 "test_flag" } } } } { "ddr_ctrl.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 4 0 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 11 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1765010717433 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "rst_n 3.3-V LVCMOS J14 " "Pin rst_n uses I/O standard 3.3-V LVCMOS at J14" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { rst_n } } } { "f:/quartus_prime_lite/quartus/bin64/Assignment Editor.qase" "" { Assignment "f:/quartus_prime_lite/quartus/bin64/Assignment Editor.qase" 1 { { 0 "rst_n" } } } } { "ddr_ctrl.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 3 0 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 10 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1765010717433 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "sys_clk 3.3-V LVCMOS J5 " "Pin sys_clk uses I/O standard 3.3-V LVCMOS at J5" { } { { "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "f:/quartus_prime_lite/quartus/bin64/pin_planner.ppl" { sys_clk } } } { "f:/quartus_prime_lite/quartus/bin64/Assignment Editor.qase" "" { Assignment "f:/quartus_prime_lite/quartus/bin64/Assignment Editor.qase" 1 { { 0 "sys_clk" } } } } { "ddr_ctrl.v" "" { Text "E:/FPGA/20240726/uart_tx_restored/ddr_ctrl.v" 2 0 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/20240726/uart_tx_restored/" { { 0 { 0 ""} 0 9 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1765010717433 ""} } { } 0 169177 "%1!d! pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1765010717433 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/FPGA/20240726/uart_tx_restored/output_files/intan_m10.fit.smsg " "Generated suppressed messages file E:/FPGA/20240726/uart_tx_restored/output_files/intan_m10.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1765010717473 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 8 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5534 " "Peak virtual memory: 5534 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1765010717809 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 6 16:45:17 2025 " "Processing ended: Sat Dec 6 16:45:17 2025" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1765010717809 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1765010717809 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1765010717809 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1765010717809 ""}

471
puart2/uart_tx_restored/db/intan_m10.hier_info Normal file
View File

@@ -0,0 +1,471 @@
|ddr_ctrl
sys_clk => sys_clk.IN1
rst_n => rst_n.IN2
test_flag => Selector7.IN4
test_flag => test_flag_led.DATAIN
test_flag => convert_flag_led.DATAIN
miso => miso.IN1
mosi <= spi_master_2164:u_spi_master_2164.mosi
cs_n <= spi_master_2164:u_spi_master_2164.cs_n
sclk <= spi_master_2164:u_spi_master_2164.sclk
MOSI_ESP32 <= spi_master_esp32:tranfer.mosi
cs_ESP32 <= spi_master_esp32:tranfer.cs
sclk_ESP32 <= spi_master_esp32:tranfer.sclk
tx <= uart_tx:u_uart_pc.tx
test_flag_led <= test_flag.DB_MAX_OUTPUT_PORT_TYPE
convert_flag_led <= test_flag.DB_MAX_OUTPUT_PORT_TYPE
|ddr_ctrl|clk_gen:clk_gen_inst
inclk0 => sub_wire1[0].IN1
c0 <= altpll:altpll_component.clk
c1 <= altpll:altpll_component.clk
|ddr_ctrl|clk_gen:clk_gen_inst|altpll:altpll_component
inclk[0] => clk_gen_altpll:auto_generated.inclk[0]
inclk[1] => clk_gen_altpll:auto_generated.inclk[1]
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanclkena => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
phasecounterselect[0] => ~NO_FANOUT~
phasecounterselect[1] => ~NO_FANOUT~
phasecounterselect[2] => ~NO_FANOUT~
phasecounterselect[3] => ~NO_FANOUT~
phaseupdown => ~NO_FANOUT~
phasestep => ~NO_FANOUT~
configupdate => ~NO_FANOUT~
fbmimicbidir <> <GND>
clk[0] <= clk[0].DB_MAX_OUTPUT_PORT_TYPE
clk[1] <= clk[1].DB_MAX_OUTPUT_PORT_TYPE
clk[2] <= clk[2].DB_MAX_OUTPUT_PORT_TYPE
clk[3] <= clk[3].DB_MAX_OUTPUT_PORT_TYPE
clk[4] <= clk[4].DB_MAX_OUTPUT_PORT_TYPE
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= <GND>
phasedone <= <GND>
vcooverrange <= <GND>
vcounderrange <= <GND>
fbout <= <GND>
fref <= <GND>
icdrclk <= <GND>
|ddr_ctrl|clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated
clk[0] <= pll1.CLK
clk[1] <= pll1.CLK1
clk[2] <= pll1.CLK2
clk[3] <= pll1.CLK3
clk[4] <= pll1.CLK4
inclk[0] => pll1.CLK
inclk[1] => pll1.CLK1
|ddr_ctrl|spi_master_2164:u_spi_master_2164
sys_clk => dout[0]~reg0.CLK
sys_clk => dout[1]~reg0.CLK
sys_clk => dout[2]~reg0.CLK
sys_clk => dout[3]~reg0.CLK
sys_clk => dout[4]~reg0.CLK
sys_clk => dout[5]~reg0.CLK
sys_clk => dout[6]~reg0.CLK
sys_clk => dout[7]~reg0.CLK
sys_clk => dout[8]~reg0.CLK
sys_clk => dout[9]~reg0.CLK
sys_clk => dout[10]~reg0.CLK
sys_clk => dout[11]~reg0.CLK
sys_clk => dout[12]~reg0.CLK
sys_clk => dout[13]~reg0.CLK
sys_clk => dout[14]~reg0.CLK
sys_clk => dout[15]~reg0.CLK
sys_clk => done~reg0.CLK
sys_clk => dout_r[0].CLK
sys_clk => dout_r[1].CLK
sys_clk => dout_r[2].CLK
sys_clk => dout_r[3].CLK
sys_clk => dout_r[4].CLK
sys_clk => dout_r[5].CLK
sys_clk => dout_r[6].CLK
sys_clk => dout_r[7].CLK
sys_clk => dout_r[8].CLK
sys_clk => dout_r[9].CLK
sys_clk => dout_r[10].CLK
sys_clk => dout_r[11].CLK
sys_clk => dout_r[12].CLK
sys_clk => dout_r[13].CLK
sys_clk => dout_r[14].CLK
sys_clk => dout_r[15].CLK
sys_clk => mosi~reg0.CLK
sys_clk => cs_n~reg0.CLK
sys_clk => sclk~reg0.CLK
sys_clk => cnt[0]~reg0.CLK
sys_clk => cnt[1]~reg0.CLK
sys_clk => cnt[2]~reg0.CLK
sys_clk => cnt[3]~reg0.CLK
sys_clk => cnt[4]~reg0.CLK
sys_clk => cnt[5]~reg0.CLK
sys_clk => cnt[6]~reg0.CLK
rst_n => mosi~reg0.ACLR
rst_n => cs_n~reg0.PRESET
rst_n => sclk~reg0.ACLR
rst_n => dout[0]~reg0.ACLR
rst_n => dout[1]~reg0.ACLR
rst_n => dout[2]~reg0.ACLR
rst_n => dout[3]~reg0.ACLR
rst_n => dout[4]~reg0.ACLR
rst_n => dout[5]~reg0.ACLR
rst_n => dout[6]~reg0.ACLR
rst_n => dout[7]~reg0.ACLR
rst_n => dout[8]~reg0.ACLR
rst_n => dout[9]~reg0.ACLR
rst_n => dout[10]~reg0.ACLR
rst_n => dout[11]~reg0.ACLR
rst_n => dout[12]~reg0.ACLR
rst_n => dout[13]~reg0.ACLR
rst_n => dout[14]~reg0.ACLR
rst_n => dout[15]~reg0.ACLR
rst_n => done~reg0.ACLR
rst_n => cnt[0]~reg0.ACLR
rst_n => cnt[1]~reg0.ACLR
rst_n => cnt[2]~reg0.ACLR
rst_n => cnt[3]~reg0.ACLR
rst_n => cnt[4]~reg0.ACLR
rst_n => cnt[5]~reg0.ACLR
rst_n => cnt[6]~reg0.ACLR
rst_n => dout_r[15].ENA
rst_n => dout_r[14].ENA
rst_n => dout_r[13].ENA
rst_n => dout_r[12].ENA
rst_n => dout_r[11].ENA
rst_n => dout_r[10].ENA
rst_n => dout_r[9].ENA
rst_n => dout_r[8].ENA
rst_n => dout_r[7].ENA
rst_n => dout_r[6].ENA
rst_n => dout_r[5].ENA
rst_n => dout_r[4].ENA
rst_n => dout_r[3].ENA
rst_n => dout_r[2].ENA
rst_n => dout_r[1].ENA
rst_n => dout_r[0].ENA
din[0] => Selector0.IN33
din[1] => Selector0.IN32
din[2] => Selector0.IN31
din[3] => Selector0.IN30
din[4] => Selector0.IN29
din[5] => Selector0.IN28
din[6] => Selector0.IN27
din[7] => Selector0.IN26
din[8] => Selector0.IN25
din[9] => Selector0.IN24
din[10] => Selector0.IN23
din[11] => Selector0.IN22
din[12] => Selector0.IN21
din[13] => Selector0.IN20
din[14] => Selector0.IN19
din[15] => Selector0.IN18
start => dout_r.OUTPUTSELECT
start => dout_r.OUTPUTSELECT
start => dout_r.OUTPUTSELECT
start => dout_r.OUTPUTSELECT
start => dout_r.OUTPUTSELECT
start => dout_r.OUTPUTSELECT
start => dout_r.OUTPUTSELECT
start => dout_r.OUTPUTSELECT
start => dout_r.OUTPUTSELECT
start => dout_r.OUTPUTSELECT
start => dout_r.OUTPUTSELECT
start => dout_r.OUTPUTSELECT
start => dout_r.OUTPUTSELECT
start => dout_r.OUTPUTSELECT
start => dout_r.OUTPUTSELECT
start => dout_r.OUTPUTSELECT
start => sclk~reg0.ENA
start => cs_n~reg0.ENA
start => mosi~reg0.ENA
dout[0] <= dout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= dout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= dout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= dout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= dout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= dout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= dout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= dout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[8] <= dout[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[9] <= dout[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[10] <= dout[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[11] <= dout[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[12] <= dout[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[13] <= dout[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[14] <= dout[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[15] <= dout[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
done <= done~reg0.DB_MAX_OUTPUT_PORT_TYPE
sclk <= sclk~reg0.DB_MAX_OUTPUT_PORT_TYPE
cs_n <= cs_n~reg0.DB_MAX_OUTPUT_PORT_TYPE
mosi <= mosi~reg0.DB_MAX_OUTPUT_PORT_TYPE
miso => dout_r.DATAB
cnt[0] <= cnt[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[1] <= cnt[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[2] <= cnt[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[3] <= cnt[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[4] <= cnt[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[5] <= cnt[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[6] <= cnt[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|ddr_ctrl|spi_master_esp32:tranfer
clk => done~reg0.CLK
clk => shift_reg[0].CLK
clk => shift_reg[1].CLK
clk => shift_reg[2].CLK
clk => shift_reg[3].CLK
clk => shift_reg[4].CLK
clk => shift_reg[5].CLK
clk => shift_reg[6].CLK
clk => shift_reg[7].CLK
clk => shift_reg[8].CLK
clk => shift_reg[9].CLK
clk => shift_reg[10].CLK
clk => shift_reg[11].CLK
clk => shift_reg[12].CLK
clk => shift_reg[13].CLK
clk => shift_reg[14].CLK
clk => shift_reg[15].CLK
clk => bit_cnt[0].CLK
clk => bit_cnt[1].CLK
clk => bit_cnt[2].CLK
clk => bit_cnt[3].CLK
clk => sclk_reg.CLK
clk => cs~reg0.CLK
clk => state~4.DATAIN
rst_n => done~reg0.ACLR
rst_n => shift_reg[0].ACLR
rst_n => shift_reg[1].ACLR
rst_n => shift_reg[2].ACLR
rst_n => shift_reg[3].ACLR
rst_n => shift_reg[4].ACLR
rst_n => shift_reg[5].ACLR
rst_n => shift_reg[6].ACLR
rst_n => shift_reg[7].ACLR
rst_n => shift_reg[8].ACLR
rst_n => shift_reg[9].ACLR
rst_n => shift_reg[10].ACLR
rst_n => shift_reg[11].ACLR
rst_n => shift_reg[12].ACLR
rst_n => shift_reg[13].ACLR
rst_n => shift_reg[14].ACLR
rst_n => shift_reg[15].ACLR
rst_n => bit_cnt[0].ACLR
rst_n => bit_cnt[1].ACLR
rst_n => bit_cnt[2].ACLR
rst_n => bit_cnt[3].ACLR
rst_n => sclk_reg.ACLR
rst_n => cs~reg0.PRESET
rst_n => state~6.DATAIN
start => state.OUTPUTSELECT
start => state.OUTPUTSELECT
start => state.OUTPUTSELECT
start => done~reg0.ENA
start => cs~reg0.ENA
start => sclk_reg.ENA
start => bit_cnt[3].ENA
start => bit_cnt[2].ENA
start => bit_cnt[1].ENA
start => bit_cnt[0].ENA
start => shift_reg[15].ENA
start => shift_reg[14].ENA
start => shift_reg[13].ENA
start => shift_reg[12].ENA
start => shift_reg[11].ENA
start => shift_reg[10].ENA
start => shift_reg[9].ENA
start => shift_reg[8].ENA
start => shift_reg[7].ENA
start => shift_reg[6].ENA
start => shift_reg[5].ENA
start => shift_reg[4].ENA
start => shift_reg[3].ENA
start => shift_reg[2].ENA
start => shift_reg[1].ENA
start => shift_reg[0].ENA
din[0] => Selector18.IN1
din[1] => Selector17.IN1
din[2] => Selector16.IN1
din[3] => Selector15.IN1
din[4] => Selector14.IN1
din[5] => Selector13.IN1
din[6] => Selector12.IN1
din[7] => Selector11.IN1
din[8] => Selector10.IN1
din[9] => Selector9.IN1
din[10] => Selector8.IN1
din[11] => Selector7.IN1
din[12] => Selector6.IN1
din[13] => Selector5.IN1
din[14] => Selector4.IN1
din[15] => Selector3.IN1
done <= done~reg0.DB_MAX_OUTPUT_PORT_TYPE
sclk <= sclk_reg.DB_MAX_OUTPUT_PORT_TYPE
mosi <= shift_reg[15].DB_MAX_OUTPUT_PORT_TYPE
cs <= cs~reg0.DB_MAX_OUTPUT_PORT_TYPE
|ddr_ctrl|uart_tx:u_uart_pc
clk => tx_bit_counter[0].CLK
clk => tx_bit_counter[1].CLK
clk => tx_bit_counter[2].CLK
clk => tx_bit_counter[3].CLK
clk => data_to_send[0].CLK
clk => data_to_send[1].CLK
clk => data_to_send[2].CLK
clk => data_to_send[3].CLK
clk => data_to_send[4].CLK
clk => data_to_send[5].CLK
clk => data_to_send[6].CLK
clk => data_to_send[7].CLK
clk => tx_shift_reg[0].CLK
clk => tx_shift_reg[1].CLK
clk => tx_shift_reg[2].CLK
clk => tx_shift_reg[3].CLK
clk => tx_shift_reg[4].CLK
clk => tx_shift_reg[5].CLK
clk => tx_shift_reg[6].CLK
clk => tx_shift_reg[7].CLK
clk => tx_shift_reg[8].CLK
clk => tx_shift_reg[9].CLK
clk => tx_done~reg0.CLK
clk => baud_counter[0].CLK
clk => baud_counter[1].CLK
clk => baud_counter[2].CLK
clk => baud_counter[3].CLK
clk => baud_counter[4].CLK
clk => baud_counter[5].CLK
clk => baud_counter[6].CLK
clk => baud_counter[7].CLK
clk => baud_counter[8].CLK
clk => baud_counter[9].CLK
clk => baud_counter[10].CLK
clk => baud_counter[11].CLK
clk => baud_counter[12].CLK
clk => baud_counter[13].CLK
clk => baud_counter[14].CLK
clk => baud_counter[15].CLK
clk => byte_select~2.DATAIN
clk => tx_state~3.DATAIN
rst => tx_shift_reg[0].PRESET
rst => tx_shift_reg[1].PRESET
rst => tx_shift_reg[2].PRESET
rst => tx_shift_reg[3].PRESET
rst => tx_shift_reg[4].PRESET
rst => tx_shift_reg[5].PRESET
rst => tx_shift_reg[6].PRESET
rst => tx_shift_reg[7].PRESET
rst => tx_shift_reg[8].PRESET
rst => tx_shift_reg[9].PRESET
rst => tx_done~reg0.ACLR
rst => baud_counter[0].ACLR
rst => baud_counter[1].ACLR
rst => baud_counter[2].ACLR
rst => baud_counter[3].ACLR
rst => baud_counter[4].ACLR
rst => baud_counter[5].ACLR
rst => baud_counter[6].ACLR
rst => baud_counter[7].ACLR
rst => baud_counter[8].ACLR
rst => baud_counter[9].ACLR
rst => baud_counter[10].ACLR
rst => baud_counter[11].ACLR
rst => baud_counter[12].ACLR
rst => baud_counter[13].ACLR
rst => baud_counter[14].ACLR
rst => baud_counter[15].ACLR
rst => byte_select~4.DATAIN
rst => tx_state~5.DATAIN
rst => tx_bit_counter[0].ENA
rst => data_to_send[7].ENA
rst => data_to_send[6].ENA
rst => data_to_send[5].ENA
rst => data_to_send[4].ENA
rst => data_to_send[3].ENA
rst => data_to_send[2].ENA
rst => data_to_send[1].ENA
rst => data_to_send[0].ENA
rst => tx_bit_counter[3].ENA
rst => tx_bit_counter[2].ENA
rst => tx_bit_counter[1].ENA
tx_start => data_to_send.OUTPUTSELECT
tx_start => data_to_send.OUTPUTSELECT
tx_start => data_to_send.OUTPUTSELECT
tx_start => data_to_send.OUTPUTSELECT
tx_start => data_to_send.OUTPUTSELECT
tx_start => data_to_send.OUTPUTSELECT
tx_start => data_to_send.OUTPUTSELECT
tx_start => data_to_send.OUTPUTSELECT
tx_start => tx_shift_reg.OUTPUTSELECT
tx_start => tx_shift_reg.OUTPUTSELECT
tx_start => tx_shift_reg.OUTPUTSELECT
tx_start => tx_shift_reg.OUTPUTSELECT
tx_start => tx_shift_reg.OUTPUTSELECT
tx_start => tx_shift_reg.OUTPUTSELECT
tx_start => tx_shift_reg.OUTPUTSELECT
tx_start => tx_shift_reg.OUTPUTSELECT
tx_start => tx_shift_reg.OUTPUTSELECT
tx_start => tx_shift_reg.OUTPUTSELECT
tx_start => tx_bit_counter.OUTPUTSELECT
tx_start => tx_bit_counter.OUTPUTSELECT
tx_start => tx_bit_counter.OUTPUTSELECT
tx_start => tx_bit_counter.OUTPUTSELECT
tx_start => tx_state.OUTPUTSELECT
tx_start => tx_state.OUTPUTSELECT
tx_start => tx_done.OUTPUTSELECT
tx_data[0] => data_to_send.DATAA
tx_data[1] => data_to_send.DATAA
tx_data[2] => data_to_send.DATAA
tx_data[3] => data_to_send.DATAA
tx_data[4] => data_to_send.DATAA
tx_data[5] => data_to_send.DATAA
tx_data[6] => data_to_send.DATAA
tx_data[7] => data_to_send.DATAA
tx_data[8] => data_to_send.DATAB
tx_data[9] => data_to_send.DATAB
tx_data[10] => data_to_send.DATAB
tx_data[11] => data_to_send.DATAB
tx_data[12] => data_to_send.DATAB
tx_data[13] => data_to_send.DATAB
tx_data[14] => data_to_send.DATAB
tx_data[15] => data_to_send.DATAB
tx <= tx_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE
tx_done <= tx_done~reg0.DB_MAX_OUTPUT_PORT_TYPE

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<TABLE>
<TR bgcolor="#C0C0C0">
<TH>Hierarchy</TH>
<TH>Input</TH>
<TH>Constant Input</TH>
<TH>Unused Input</TH>
<TH>Floating Input</TH>
<TH>Output</TH>
<TH>Constant Output</TH>
<TH>Unused Output</TH>
<TH>Floating Output</TH>
<TH>Bidir</TH>
<TH>Constant Bidir</TH>
<TH>Unused Bidir</TH>
<TH>Input only Bidir</TH>
<TH>Output only Bidir</TH>
</TR>
<TR >
<TD >u_uart_pc</TD>
<TD >19</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >tranfer</TD>
<TD >19</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >4</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >u_spi_master_2164</TD>
<TD >20</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >20</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >clk_gen_inst|altpll_component|auto_generated</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >5</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >clk_gen_inst</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
</TABLE>

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+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+----------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+----------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; u_uart_pc ; 19 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; tranfer ; 19 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; u_spi_master_2164 ; 20 ; 0 ; 0 ; 0 ; 20 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; clk_gen_inst|altpll_component|auto_generated ; 2 ; 0 ; 0 ; 0 ; 5 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; clk_gen_inst ; 1 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+----------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

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v1

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1765010725981 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Power Analyzer Quartus Prime " "Running Quartus Prime Power Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition " "Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1765010725981 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 6 16:45:25 2025 " "Processing started: Sat Dec 6 16:45:25 2025" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1765010725981 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Power Analyzer" 0 -1 1765010725981 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_pow --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10 " "Command: quartus_pow --read_settings_files=off --write_settings_files=off intan_m10 -c intan_m10" { } { } 0 0 "Command: %1!s!" 0 0 "Power Analyzer" 0 -1 1765010725981 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Power Analyzer" 0 -1 1765010726325 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Power Analyzer" 0 -1 1765010726325 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "intan_m10.sdc " "Synopsys Design Constraints File file not found: 'intan_m10.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Power Analyzer" 0 -1 1765010726566 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "sys_clk " "Node: sys_clk was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register spi_master_2164:u_spi_master_2164\|cnt\[0\] sys_clk " "Register spi_master_2164:u_spi_master_2164\|cnt\[0\] is being clocked by sys_clk" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1765010726567 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Power Analyzer" 0 -1 1765010726567 "|ddr_ctrl|sys_clk"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "spi_master_2164:u_spi_master_2164\|cs_n " "Node: spi_master_2164:u_spi_master_2164\|cs_n was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register state\[7\] spi_master_2164:u_spi_master_2164\|cs_n " "Register state\[7\] is being clocked by spi_master_2164:u_spi_master_2164\|cs_n" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1765010726567 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Power Analyzer" 0 -1 1765010726567 "|ddr_ctrl|spi_master_2164:u_spi_master_2164|cs_n"}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Power Analyzer" 0 -1 1765010726567 ""}
{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Node: clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 83.333 " "Node: clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 83.333" { } { } 0 332056 "%1!s!" 0 0 "Design Software" 0 -1 1765010726569 ""} { "Warning" "WSTA_GENERIC_WARNING" "Node: clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] was found missing 1 generated clock that corresponds to a base clock with a period of: 83.333 " "Node: clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] was found missing 1 generated clock that corresponds to a base clock with a period of: 83.333" { } { } 0 332056 "%1!s!" 0 0 "Design Software" 0 -1 1765010726569 ""} } { } 0 332056 "%1!s!" 0 0 "Power Analyzer" 0 -1 1765010726569 ""}
{ "Info" "IPVA_PVA_START_CALCULATION" "" "Starting Vectorless Power Activity Estimation" { } { } 0 223000 "Starting Vectorless Power Activity Estimation" 0 0 "Power Analyzer" 0 -1 1765010726573 ""}
{ "Warning" "WPUTIL_PUTIL_NO_CLK_DOMAINS_FOUND" "" "Relative toggle rates could not be calculated because no clock domain could be identified for some nodes" { } { } 0 222013 "Relative toggle rates could not be calculated because no clock domain could be identified for some nodes" 0 0 "Power Analyzer" 0 -1 1765010726574 ""}
{ "Info" "IPVA_PVA_END_CALCULATION" "" "Completed Vectorless Power Activity Estimation" { } { } 0 223001 "Completed Vectorless Power Activity Estimation" 0 0 "Power Analyzer" 0 -1 1765010726577 ""}
{ "Info" "IPATFAM_USING_ADVANCED_IO_POWER" "" "Using Advanced I/O Power to simulate I/O buffers with the specified board trace model" { } { } 0 218000 "Using Advanced I/O Power to simulate I/O buffers with the specified board trace model" 0 0 "Power Analyzer" 0 -1 1765010726758 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Power Analyzer" 0 -1 1765010726790 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Power Analyzer" 0 -1 1765010727104 ""}
{ "Info" "IPAN_AVG_TOGGLE_RATE_PER_DESIGN" "0.000 millions of transitions / sec " "Average toggle rate for this design is 0.000 millions of transitions / sec" { } { } 0 215049 "Average toggle rate for this design is %1!s!" 0 0 "Power Analyzer" 0 -1 1765010727308 ""}
{ "Info" "IPAN_PAN_TOTAL_POWER_ESTIMATION" "144.69 mW " "Total thermal power estimate for the design is 144.69 mW" { } { { "f:/quartus_prime_lite/quartus/bin64/Report_Window_01.qrpt" "" { Report "f:/quartus_prime_lite/quartus/bin64/Report_Window_01.qrpt" "Compiler" "" "" "" "" { } "PowerPlay Power Analyzer Summary" } } } 0 215031 "Total thermal power estimate for the design is %1!s!" 0 0 "Power Analyzer" 0 -1 1765010727374 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Power Analyzer 0 s 8 s Quartus Prime " "Quartus Prime Power Analyzer was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4814 " "Peak virtual memory: 4814 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1765010727559 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 6 16:45:27 2025 " "Processing ended: Sat Dec 6 16:45:27 2025" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1765010727559 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1765010727559 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1765010727559 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Power Analyzer" 0 -1 1765010727559 ""}

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{ "Info" "0" "" "Successfully restored 'E:/FPGA/20240726/uart_tx.qar' into the 'E:/FPGA/20240726/uart_tx_restored/' directory" { } { } 0 0 "Successfully restored 'E:/FPGA/20240726/uart_tx.qar' into the 'E:/FPGA/20240726/uart_tx_restored/' directory" 0 0 "Shell" 0 0 1765006933692 ""}
{ "Info" "0" "" "Generated report 'intan_m10.restore.rpt'" { } { } 0 0 "Generated report 'intan_m10.restore.rpt'" 0 0 "Shell" 0 0 1765006933693 ""}
{ "Info" "IQEXE_TCL_SCRIPT_STATUS" "f:/quartus_prime_lite/quartus/common/tcl/apps/qpm/qar.tcl " "Evaluation of Tcl script f:/quartus_prime_lite/quartus/common/tcl/apps/qpm/qar.tcl was successful" { } { } 0 23030 "Evaluation of Tcl script %1!s! was successful" 0 0 "Shell" 0 -1 1765006933705 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Shell 0 s 41 s Quartus Prime " "Quartus Prime Shell was successful. 0 errors, 41 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4822 " "Peak virtual memory: 4822 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1765006933705 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 6 15:42:13 2025 " "Processing ended: Sat Dec 6 15:42:13 2025" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1765006933705 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1765006933705 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1765006933705 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Shell" 0 -1 1765006933705 ""}

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DONE

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State Machine - |ddr_ctrl|state_top
Name state_top.SEND3 state_top.SEND2 state_top.SEND1 state_top.IDLE
state_top.IDLE 0 0 0 0
state_top.SEND1 0 0 1 1
state_top.SEND2 0 1 0 1
state_top.SEND3 1 0 0 1
State Machine - |ddr_ctrl|uart_tx:u_uart_pc|byte_select
Name byte_select.01
byte_select.00 0
byte_select.01 1
State Machine - |ddr_ctrl|uart_tx:u_uart_pc|tx_state
Name tx_state.0001
tx_state.0000 0
tx_state.0001 1
State Machine - |ddr_ctrl|spi_master_esp32:tranfer|state
Name state.IDLE state.DONE state.TRANSFER
state.IDLE 0 0 0
state.TRANSFER 1 0 1
state.DONE 1 1 0

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1765010728861 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition " "Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1765010728861 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 6 16:45:28 2025 " "Processing started: Sat Dec 6 16:45:28 2025" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1765010728861 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1765010728861 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta intan_m10 -c intan_m10 " "Command: quartus_sta intan_m10 -c intan_m10" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1765010728861 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1765010728984 ""}
{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "4 " "Parallel compilation is enabled and will use up to 4 processors" { } { } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Timing Analyzer" 0 -1 1765010729129 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1765010729160 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1765010729160 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "intan_m10.sdc " "Synopsys Design Constraints File file not found: 'intan_m10.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1765010729265 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "generated clocks \"derive_pll_clocks -create_base_clocks\" " "No user constrained generated clocks found in the design. Calling \"derive_pll_clocks -create_base_clocks\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1765010729265 ""}
{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_clock -period 83.333 -waveform \{0.000 41.666\} -name sys_clk sys_clk " "create_clock -period 83.333 -waveform \{0.000 41.666\} -name sys_clk sys_clk" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1765010729266 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 625 -multiply_by 6 -duty_cycle 50.00 -name \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 625 -multiply_by 6 -duty_cycle 50.00 -name \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1765010729266 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 625 -multiply_by 12 -duty_cycle 50.00 -name \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 625 -multiply_by 12 -duty_cycle 50.00 -name \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "Design Software" 0 -1 1765010729266 ""} } { } 0 332110 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1765010729266 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1765010729266 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name spi_master_2164:u_spi_master_2164\|cs_n spi_master_2164:u_spi_master_2164\|cs_n " "create_clock -period 1.000 -name spi_master_2164:u_spi_master_2164\|cs_n spi_master_2164:u_spi_master_2164\|cs_n" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1765010729266 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1765010729266 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1765010729267 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1765010729268 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1765010729268 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1765010729275 ""}
{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1765010729278 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1765010729280 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -6.111 " "Worst-case setup slack is -6.111" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729287 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729287 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.111 -6.111 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -6.111 -6.111 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729287 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.600 -7.693 spi_master_2164:u_spi_master_2164\|cs_n " " -0.600 -7.693 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729287 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4335.838 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4335.838 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729287 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1765010729287 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.362 " "Worst-case hold slack is 0.362" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.362 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.362 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.362 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.362 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.362 0.000 spi_master_2164:u_spi_master_2164\|cs_n " " 0.362 0.000 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729292 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1765010729292 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1765010729301 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1765010729306 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.487 " "Worst-case minimum pulse width slack is -1.487" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729315 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729315 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.487 -46.097 spi_master_2164:u_spi_master_2164\|cs_n " " -1.487 -46.097 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729315 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 41.541 0.000 sys_clk " " 41.541 0.000 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729315 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2169.851 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 2169.851 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729315 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4339.991 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4339.991 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729315 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1765010729315 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1765010729325 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1765010729347 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1765010729661 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1765010729716 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1765010729722 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -5.633 " "Worst-case setup slack is -5.633" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729735 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729735 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -5.633 -5.633 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -5.633 -5.633 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729735 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.518 -5.401 spi_master_2164:u_spi_master_2164\|cs_n " " -0.518 -5.401 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729735 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4336.023 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4336.023 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729735 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1765010729735 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.324 " "Worst-case hold slack is 0.324" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729738 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729738 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.324 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.324 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729738 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.324 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.324 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729738 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.324 0.000 spi_master_2164:u_spi_master_2164\|cs_n " " 0.324 0.000 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729738 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1765010729738 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1765010729751 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1765010729754 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.487 " "Worst-case minimum pulse width slack is -1.487" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729764 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729764 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.487 -46.097 spi_master_2164:u_spi_master_2164\|cs_n " " -1.487 -46.097 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729764 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 41.545 0.000 sys_clk " " 41.545 0.000 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729764 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2169.828 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 2169.828 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729764 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4340.001 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4340.001 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729764 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1765010729764 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1765010729774 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1765010729916 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1765010729917 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.102 " "Worst-case setup slack is -2.102" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729918 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729918 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.102 -2.102 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " -2.102 -2.102 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729918 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.320 0.000 spi_master_2164:u_spi_master_2164\|cs_n " " 0.320 0.000 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729918 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4338.451 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4338.451 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729918 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1765010729918 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.150 " "Worst-case hold slack is 0.150" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729930 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729930 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.150 0.000 spi_master_2164:u_spi_master_2164\|cs_n " " 0.150 0.000 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729930 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.152 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.152 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729930 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.152 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 0.152 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729930 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1765010729930 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1765010729932 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1765010729942 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.000 " "Worst-case minimum pulse width slack is -1.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729951 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729951 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.000 -31.000 spi_master_2164:u_spi_master_2164\|cs_n " " -1.000 -31.000 spi_master_2164:u_spi_master_2164\|cs_n " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729951 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 41.170 0.000 sys_clk " " 41.170 0.000 sys_clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729951 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2169.891 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 2169.891 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729951 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4340.042 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4340.042 0.000 clk_gen_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1765010729951 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1765010729951 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1765010730630 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1765010730630 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 4 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4783 " "Peak virtual memory: 4783 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1765010730715 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 6 16:45:30 2025 " "Processing ended: Sat Dec 6 16:45:30 2025" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1765010730715 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1765010730715 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1765010730715 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1765010730715 ""}

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start_full_compilation:s:00:00:29
start_analysis_synthesis:s:00:00:10-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:06-start_full_compilation
start_assembler:s:00:00:07-start_full_compilation
start_timing_analyzer:s:00:00:03-start_full_compilation

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{
"partitions" : [
{
"name" : "Top",
"pins" : [
{
"name" : "mosi",
"strict" : false
},
{
"name" : "cs_n",
"strict" : false
},
{
"name" : "sclk",
"strict" : false
},
{
"name" : "tx",
"strict" : false
},
{
"name" : "test_flag_led",
"strict" : false
},
{
"name" : "convert_flag_led",
"strict" : false
},
{
"name" : "test_flag",
"strict" : false
},
{
"name" : "rst_n",
"strict" : false
}
]
}
]
}

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puart2/uart_tx_restored/ddr_ctrl.v Normal file
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module ddr_ctrl(
input sys_clk, // 12M on-board oscillator
input rst_n,
input test_flag, // 1: read register, 0: start convert data
// 2132
input miso,
output mosi,
output cs_n,
output sclk,
//esp32
output MOSI_ESP32,
output cs_ESP32,
output sclk_ESP32,
//uart
output wire tx, // 串行输出信号
output test_flag_led,
output convert_flag_led
// for simulation
// output reg [25:0] state,
// output reg [25:0] next,
//output [15:0] dout
);
reg start1, start2,start_uart;
wire done1,done2,done_uart;
localparam [4:0] s0 = 0,
s1 = 1,
s2 = 2,
s3 = 3,
s4 = 4,
s5 = 5,
s6 = 6,
s7 = 7,
s8 = 8,
s9 = 9,
s10 = 10,
s11 = 11,
s12 = 12,
s13 = 13,
s14 = 14,
s15 = 15,
s16 = 16,
s17 = 17,
s18 = 18,
s19 = 19,
s20 = 20,
s21 = 21,
s22 = 22,
s23 = 23,
s24 = 24,
s25 = 25,
s26 = 26,
s27 = 27,
s28 = 28,
s29 = 29,
s30 = 30;
reg [30:0] state, next;
reg [15:0] din_r;
wire [15:0] din;
reg [15:0] received_data; // 存储从从机1接收到的数据
reg [15:0] sent_data; // 要发送到从机2的数据
assign din = din_r;
assign test_flag_led = test_flag;
assign convert_flag_led = ~test_flag;
// 定义状态编码
parameter IDLE = 2'b00,
SEND1 = 2'b01,
SEND2 = 2'b10,
SEND3 = 2'b11;
// 定义状态变量
reg [1:0] state_top;
//状态机，用于控制两个SPI模块的启动
always @(posedge clk_230400 or negedge rst_n) begin
if (!rst_n) begin
start1 <= 0;
start2 <= 0;
state_top <= IDLE;
end
else begin
case (state_top)
IDLE: begin
start1 <= 1; // 启动SPI主机1
start2 <= 0;
state_top <= SEND1;
end
SEND1: begin
// if (done1) begin // SPI主机1完成接收
start1 <= 0;
received_data <= {2'b00,6'd00,8'h01}; // dout1存储接收到的数据
sent_data <={2'b00,6'd00,8'h01} ; //dout1 将接收到的数据准备好发送
start_uart <= 1; // 启动SPI主机2，发送数据给从机2
state_top <= SEND3;
//end
end
SEND3: begin
if (done_uart) begin // uart完成发送
start_uart <= 0;
//start2 <= 1;
state_top <= SEND1; // SEND2;
end
end
SEND2: begin
if (done2) begin // SPI主机2完成发送
start2 <= 0;
state_top <= IDLE; // 回到初始状态，等待下一轮传输
end
end
default: state_top <= IDLE;
endcase
end
end
//时序逻辑加组合逻辑完成din命令的有序发送
always @ (posedge cs_n or negedge rst_n) begin
if(!rst_n) begin
state <= 31'd0;
state[s0] <= 1'b1;
end
else state <= next;
end
always @ (*) begin
next = 31'd0;
din_r = {2'b11,6'd63,8'h00};
case(1'b1) // synthesis parallel_case full_case
state[s0]: begin din_r<={2'b11,6'd63,8'h00}; next[s1] = 1'b1; end
state[s1]: begin din_r<={2'b11,6'd63,8'h00}; next[s2] = 1'b1; end
state[s2]: begin din_r<={2'b10,6'd0,8'hDE}; next[s3] = 1'b1; end
state[s3]: begin din_r<={2'b10,6'd1,8'h20}; next[s4] = 1'b1; end //8'h20
state[s4]: begin din_r<={2'b10,6'd2,8'h28}; next[s5] = 1'b1; end //8'h28
state[s5]: begin din_r<={2'b10,6'd3,8'h00}; next[s6] = 1'b1; end
state[s6]: begin din_r<={2'b10,6'd4,8'hD6}; next[s7] = 1'b1; end
state[s7]: begin din_r<={2'b10,6'd5,8'h00}; next[s8] = 1'b1; end
state[s8]: begin din_r<={2'b10,6'd6,8'h80}; next[s9] = 1'b1; end
state[s9]: begin din_r<={2'b10,6'd7,8'h00}; next[s10] = 1'b1; end
state[s10]: begin din_r<={2'b10,6'd8,8'h16}; next[s11] = 1'b1; end
state[s11]: begin din_r<={2'b10,6'd9,8'h80}; next[s12] = 1'b1; end
state[s12]: begin din_r<={2'b10,6'd10,8'h17}; next[s13] = 1'b1; end
state[s13]: begin din_r<={2'b10,6'd11,8'h80}; next[s14] = 1'b1; end
state[s14]: begin din_r<={2'b10,6'd12,8'h2C}; next[s15] = 1'b1; end
state[s15]: begin din_r<={2'b10,6'd13,8'h86}; next[s16] = 1'b1; end
state[s16]: begin din_r<={2'b10,6'd14,8'hFF}; next[s17] = 1'b1; end
state[s17]: begin din_r<={2'b10,6'd15,8'hFF}; next[s18] = 1'b1; end
state[s18]: begin din_r<={2'b10,6'd16,8'hFF}; next[s19] = 1'b1; end
state[s19]: begin din_r<={2'b10,6'd17,8'hFF}; next[s20] = 1'b1; end
state[s20]: begin din_r<={2'b01,6'd21,8'h00}; next[s21] = 1'b1; end // CALIBRATE, {01,010101,8h00}
state[s21]: begin din_r<={2'b11,6'd63,8'h00}; next[s22] = 1'b1; end // dummy 1
state[s22]: begin din_r<={2'b11,6'd63,8'h00}; next[s23] = 1'b1; end // dummy 2
state[s23]: begin din_r<={2'b11,6'd63,8'h00}; next[s24] = 1'b1; end // dummy 3
state[s24]: begin din_r<={2'b11,6'd63,8'h00}; next[s25] = 1'b1; end // dummy 4
state[s25]: begin din_r<={2'b11,6'd63,8'h00}; next[s26] = 1'b1; end // dummy 5
state[s26]: begin din_r<={2'b11,6'd63,8'h00}; next[s27] = 1'b1; end // dummy 6
state[s27]: begin din_r<={2'b11,6'd63,8'h00}; next[s28] = 1'b1; end // dummy 7
state[s28]: begin din_r<={2'b11,6'd63,8'h00}; next[s29] = 1'b1; end // dummy 8
state[s29]: begin din_r<={2'b11,6'd62,8'h00}; next[s30] = 1'b1; end // dummy 9
state[s30]: begin
if (test_flag) begin din_r<={2'b11,6'd63,8'h00}; end // read(63)
else begin din_r<={2'b11,6'd62,8'h00}; end // convert(3) din_r<={2'b00,6'd3,8'h00};
next[s30] = 1'b1;
end
endcase
end
wire clk_115200;
wire clk_230400;
clk_gen clk_gen_inst (
.inclk0 ( sys_clk ),
.c0 ( clk_115200 ),
.c1 ( clk_230400 )
);
wire [15:0] dout1;
spi_master_2164 u_spi_master_2164(
.sys_clk(clk_230400),
.rst_n(rst_n),
.din(din),
.start(start1),
.dout(dout1),
.done(done1),
.sclk(sclk),
.cs_n(cs_n),
.mosi(mosi),
.miso(miso),
.cnt()
);
spi_master_esp32 tranfer(
.clk(clk_230400),
.rst_n(rst_n),
.start(start2),
.din(sent_data),
.done(done2),
.sclk(sclk_ESP32),
.mosi(MOSI_ESP32),
.cs(cs_ESP32)
);
uart_tx u_uart_pc(
.clk(clk_115200), // 时钟信号
.rst(~rst_n), // 复位信号
.tx_start(start_uart), // 开始发送信号
.tx_data(sent_data), // 顶层输入的16位待发送数据
.tx(tx), // 串行输出信号
.tx_done(done_uart) // 发送完成信号
);
endmodule

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puart2/uart_tx_restored/ddr_ctrl.v.bak Normal file
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module ddr_ctrl(
input sys_clk, // 12M on-board oscillator
input rst_n,
input test_flag, // 1: read register, 0: start convert data
// 2132
input miso,
output mosi,
output cs_n,
output sclk,
//esp32
output MOSI_ESP32,
output cs_ESP32,
output sclk_ESP32,
//uart
output wire tx, // 串行输出信号
output test_flag_led,
output convert_flag_led
// for simulation
// output reg [25:0] state,
// output reg [25:0] next,
//output [15:0] dout
);
reg start1, start2,start_uart;
wire done1,done2,done_uart;
localparam [4:0] s0 = 0,
s1 = 1,
s2 = 2,
s3 = 3,
s4 = 4,
s5 = 5,
s6 = 6,
s7 = 7,
s8 = 8,
s9 = 9,
s10 = 10,
s11 = 11,
s12 = 12,
s13 = 13,
s14 = 14,
s15 = 15,
s16 = 16,
s17 = 17,
s18 = 18,
s19 = 19,
s20 = 20,
s21 = 21,
s22 = 22,
s23 = 23,
s24 = 24,
s25 = 25,
s26 = 26,
s27 = 27,
s28 = 28,
s29 = 29,
s30 = 30;
reg [30:0] state, next;
reg [15:0] din_r;
wire [15:0] din;
reg [15:0] received_data; // 存储从从机1接收到的数据
reg [15:0] sent_data; // 要发送到从机2的数据
assign din = din_r;
assign test_flag_led = test_flag;
assign convert_flag_led = ~test_flag;
// 定义状态编码
parameter IDLE = 2'b00,
SEND1 = 2'b01,
SEND2 = 2'b10,
SEND_uart =2'b11;
// 定义状态变量
reg [1:0] state_top;
//状态机，用于控制两个SPI模块的启动
always @(posedge clk_230400 or negedge rst_n) begin
if (!rst_n) begin
start1 <= 0;
start2 <= 0;
state_top <= IDLE;
end
else begin
case (state_top)
IDLE: begin
start1 <= 1; // 启动SPI主机1
start2 <= 0;
state_top <= SEND1;
end
SEND1: begin
if (done1) begin // SPI主机1完成接收
start1 <= 0;
received_data <= dout1; // 存储接收到的数据
sent_data <= dout1; // 将接收到的数据准备好发送
start_uart <= 1; // 启动SPI主机2，发送数据给从机2
state_top <= SEND_uart;
end
end
SEND_uart: begin
if (done_uart) begin // uart完成发送
start_uart <= 0;
start2 <= 1;
state_top <= SEND2;
end
end
SEND2: begin
if (done2) begin // SPI主机2完成发送
start2 <= 0;
state_top <= IDLE; // 回到初始状态，等待下一轮传输
end
end
default: state_top <= IDLE;
endcase
end
end
//时序逻辑加组合逻辑完成din命令的有序发送
always @ (posedge cs_n or negedge rst_n) begin
if(!rst_n) begin
state <= 31'd0;
state[s0] <= 1'b1;
end
else state <= next;
end
always @ (*) begin
next = 31'd0;
din_r = {2'b11,6'd63,8'h00};
case(1'b1) // synthesis parallel_case full_case
state[s0]: begin din_r<={2'b11,6'd63,8'h00}; next[s1] = 1'b1; end
state[s1]: begin din_r<={2'b11,6'd63,8'h00}; next[s2] = 1'b1; end
state[s2]: begin din_r<={2'b10,6'd0,8'hDE}; next[s3] = 1'b1; end
state[s3]: begin din_r<={2'b10,6'd1,8'h20}; next[s4] = 1'b1; end //8'h20
state[s4]: begin din_r<={2'b10,6'd2,8'h28}; next[s5] = 1'b1; end //8'h28
state[s5]: begin din_r<={2'b10,6'd3,8'h00}; next[s6] = 1'b1; end
state[s6]: begin din_r<={2'b10,6'd4,8'hD6}; next[s7] = 1'b1; end
state[s7]: begin din_r<={2'b10,6'd5,8'h00}; next[s8] = 1'b1; end
state[s8]: begin din_r<={2'b10,6'd6,8'h80}; next[s9] = 1'b1; end
state[s9]: begin din_r<={2'b10,6'd7,8'h00}; next[s10] = 1'b1; end
state[s10]: begin din_r<={2'b10,6'd8,8'h16}; next[s11] = 1'b1; end
state[s11]: begin din_r<={2'b10,6'd9,8'h80}; next[s12] = 1'b1; end
state[s12]: begin din_r<={2'b10,6'd10,8'h17}; next[s13] = 1'b1; end
state[s13]: begin din_r<={2'b10,6'd11,8'h80}; next[s14] = 1'b1; end
state[s14]: begin din_r<={2'b10,6'd12,8'h2C}; next[s15] = 1'b1; end
state[s15]: begin din_r<={2'b10,6'd13,8'h86}; next[s16] = 1'b1; end
state[s16]: begin din_r<={2'b10,6'd14,8'hFF}; next[s17] = 1'b1; end
state[s17]: begin din_r<={2'b10,6'd15,8'hFF}; next[s18] = 1'b1; end
state[s18]: begin din_r<={2'b10,6'd16,8'hFF}; next[s19] = 1'b1; end
state[s19]: begin din_r<={2'b10,6'd17,8'hFF}; next[s20] = 1'b1; end
state[s20]: begin din_r<={2'b01,6'd21,8'h00}; next[s21] = 1'b1; end // CALIBRATE, {01,010101,8h00}
state[s21]: begin din_r<={2'b11,6'd63,8'h00}; next[s22] = 1'b1; end // dummy 1
state[s22]: begin din_r<={2'b11,6'd63,8'h00}; next[s23] = 1'b1; end // dummy 2
state[s23]: begin din_r<={2'b11,6'd63,8'h00}; next[s24] = 1'b1; end // dummy 3
state[s24]: begin din_r<={2'b11,6'd63,8'h00}; next[s25] = 1'b1; end // dummy 4
state[s25]: begin din_r<={2'b11,6'd63,8'h00}; next[s26] = 1'b1; end // dummy 5
state[s26]: begin din_r<={2'b11,6'd63,8'h00}; next[s27] = 1'b1; end // dummy 6
state[s27]: begin din_r<={2'b11,6'd63,8'h00}; next[s28] = 1'b1; end // dummy 7
state[s28]: begin din_r<={2'b11,6'd63,8'h00}; next[s29] = 1'b1; end // dummy 8
state[s29]: begin din_r<={2'b11,6'd62,8'h00}; next[s30] = 1'b1; end // dummy 9
state[s30]: begin
if (test_flag) begin din_r<={2'b11,6'd63,8'h00}; end // read(63)
else begin din_r<={2'b11,6'd62,8'h00}; end // convert(3) din_r<={2'b00,6'd3,8'h00};
next[s30] = 1'b1;
end
endcase
end
wire clk_115200;
wire clk_230400;
clk_gen clk_gen_inst (
.inclk0 ( sys_clk ),
.c0 ( clk_115200 ),
.c1 ( clk_230400 )
);
wire [15:0] dout1;
spi_master_2164 u_spi_master_2164(
.sys_clk(clk_230400),
.rst_n(rst_n),
.din(din),
.start(start1),
.dout(dout1),
.done(done1),
.sclk(sclk),
.cs_n(cs_n),
.mosi(mosi),
.miso(miso),
.cnt()
);
spi_master_esp32 tranfer(
.clk(clk_230400),
.rst_n(rst_n),
.start(start2),
.din(sent_data),
.done(done2),
.sclk(sclk_ESP32),
.mosi(MOSI_ESP32),
.cs(cs_ESP32)
);
uart_tx u_uart_pc(
.clk(sys_clk), // 时钟信号
.rst(rst_n), // 复位信号
.tx_start(start_uart), // 开始发送信号
.tx_data(sent_data), // 顶层输入的16位待发送数据
.tx(tx), // 串行输出信号
.tx_done(done_uart) // 发送完成信号
);
endmodule

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puart2/uart_tx_restored/ddr_ctrl_tb.v Normal file
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module ddr_ctrl_tb();
reg sys_clk;
reg rst_n;
reg miso;
wire mosi;
wire cs_n;
wire sclk;
wire [24:0] state;
wire [24:0] next;
wire [31:0] dout;
ddr_ctrl uut(
.sys_clk(sys_clk),
.rst_n(rst_n),
.miso(miso),
.mosi(mosi),
.cs_n(cs_n),
.sclk(sclk),
.state(state),
.next(next),
.dout(dout)
);
initial
begin
rst_n = 0;
miso = 0;
#50 rst_n = 1;
#12000 $finish;
end
initial begin
forever begin
#5 sys_clk = 0;
#5 sys_clk = 1;
end
end
initial begin
forever begin
#50 miso = 0;
#50 miso = 1;
end
end
initial begin
$fsdbDumpfile("ddr_ctrl.fsdb");
$fsdbDumpvars();
end
endmodule

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puart2/uart_tx_restored/greybox_tmp/cbx_args.txt Normal file
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BANDWIDTH_TYPE=AUTO
CLK0_DIVIDE_BY=625
CLK0_DUTY_CYCLE=50
CLK0_MULTIPLY_BY=6
CLK0_PHASE_SHIFT=0
CLK1_DIVIDE_BY=625
CLK1_DUTY_CYCLE=50
CLK1_MULTIPLY_BY=12
CLK1_PHASE_SHIFT=0
COMPENSATE_CLOCK=CLK0
INCLK0_INPUT_FREQUENCY=83333
INTENDED_DEVICE_FAMILY="MAX 10"
LPM_TYPE=altpll
OPERATION_MODE=NORMAL
PLL_TYPE=AUTO
PORT_ACTIVECLOCK=PORT_UNUSED
PORT_ARESET=PORT_UNUSED
PORT_CLKBAD0=PORT_UNUSED
PORT_CLKBAD1=PORT_UNUSED
PORT_CLKLOSS=PORT_UNUSED
PORT_CLKSWITCH=PORT_UNUSED
PORT_CONFIGUPDATE=PORT_UNUSED
PORT_FBIN=PORT_UNUSED
PORT_INCLK0=PORT_USED
PORT_INCLK1=PORT_UNUSED
PORT_LOCKED=PORT_UNUSED
PORT_PFDENA=PORT_UNUSED
PORT_PHASECOUNTERSELECT=PORT_UNUSED
PORT_PHASEDONE=PORT_UNUSED
PORT_PHASESTEP=PORT_UNUSED
PORT_PHASEUPDOWN=PORT_UNUSED
PORT_PLLENA=PORT_UNUSED
PORT_SCANACLR=PORT_UNUSED
PORT_SCANCLK=PORT_UNUSED
PORT_SCANCLKENA=PORT_UNUSED
PORT_SCANDATA=PORT_UNUSED
PORT_SCANDATAOUT=PORT_UNUSED
PORT_SCANDONE=PORT_UNUSED
PORT_SCANREAD=PORT_UNUSED
PORT_SCANWRITE=PORT_UNUSED
PORT_clk0=PORT_USED
PORT_clk1=PORT_USED
PORT_clk2=PORT_UNUSED
PORT_clk3=PORT_UNUSED
PORT_clk4=PORT_UNUSED
PORT_clk5=PORT_UNUSED
PORT_clkena0=PORT_UNUSED
PORT_clkena1=PORT_UNUSED
PORT_clkena2=PORT_UNUSED
PORT_clkena3=PORT_UNUSED
PORT_clkena4=PORT_UNUSED
PORT_clkena5=PORT_UNUSED
PORT_extclk0=PORT_UNUSED
PORT_extclk1=PORT_UNUSED
PORT_extclk2=PORT_UNUSED
PORT_extclk3=PORT_UNUSED
WIDTH_CLOCK=5
DEVICE_FAMILY="MAX 10"
CBX_AUTO_BLACKBOX=ALL
inclk
inclk
clk
clk

11
puart2/uart_tx_restored/incremental_db/README Normal file
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This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.

3
puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.db_info Normal file
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Quartus_Version = Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition
Version_Index = 570679552
Creation_Time = Sat Dec 6 15:50:23 2025

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puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.ammdb Normal file
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puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.cdb Normal file
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puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.dfp Normal file
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puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.hdb Normal file
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1
puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.logdb Normal file
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v1

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puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.cmp.rcfdb Normal file
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puart2/uart_tx_restored/incremental_db/compiled_partitions/intan_m10.root_partition.map.cdb Normal file
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