{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1765447215980 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition " "Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1765447215990 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 11 18:00:15 2025 " "Processing started: Thu Dec 11 18:00:15 2025" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1765447215990 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765447215990 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off intan_m10 -c intan_m10 " "Command: quartus_map --read_settings_files=on --write_settings_files=off intan_m10 -c intan_m10" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765447215990 ""}
{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "4 " "Parallel compilation is enabled and will use up to 4 processors" {  } {  } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Analysis & Synthesis" 0 -1 1765447216375 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spi_master_2164.v 1 1 " "Found 1 design units, including 1 entities, in source file spi_master_2164.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi_master_2164 " "Found entity 1: spi_master_2164" {  } { { "spi_master_2164.v" "" { Text "E:/FPGA/puart2/spi_master_2164.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1765447224728 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765447224728 ""}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "ddr_ctrl.v(151) " "Verilog HDL information at ddr_ctrl.v(151): always construct contains both blocking and non-blocking assignments" {  } { { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 151 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1765447224731 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr_ctrl.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr_ctrl.v" { { "Info" "ISGN_ENTITY_NAME" "1 ddr_ctrl " "Found entity 1: ddr_ctrl" {  } { { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1765447224732 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765447224732 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clk_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file clk_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_gen " "Found entity 1: clk_gen" {  } { { "clk_gen.v" "" { Text "E:/FPGA/puart2/clk_gen.v" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1765447224734 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765447224734 ""}
{ "Warning" "WSGN_FILE_IS_MISSING" "../../20240625.v " "Can't analyze file -- file ../../20240625.v is missing" {  } {  } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Analysis & Synthesis" 0 -1 1765447224737 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "done DONE spi_master_esp32.v(6) " "Verilog HDL Declaration information at spi_master_esp32.v(6): object \"done\" differs only in case from object \"DONE\" in the same scope" {  } { { "spi_master_esp32.v" "" { Text "E:/FPGA/puart2/spi_master_esp32.v" 6 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1765447224740 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "spi_master_esp32.v 1 1 " "Found 1 design units, including 1 entities, in source file spi_master_esp32.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi_master_esp32 " "Found entity 1: spi_master_esp32" {  } { { "spi_master_esp32.v" "" { Text "E:/FPGA/puart2/spi_master_esp32.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1765447224740 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765447224740 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_tx.v 1 1 " "Found 1 design units, including 1 entities, in source file uart_tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart_tx " "Found entity 1: uart_tx" {  } { { "uart_tx.v" "" { Text "E:/FPGA/puart2/uart_tx.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1765447224743 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765447224743 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "ddr_ctrl " "Elaborating entity \"ddr_ctrl\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1765447224790 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "received_data ddr_ctrl.v(71) " "Verilog HDL or VHDL warning at ddr_ctrl.v(71): object \"received_data\" assigned a value but never read" {  } { { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 71 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1765447224791 "|ddr_ctrl"}
{ "Warning" "WVRFX_L2_VERI_ASSUMED_INCOMPLETE_CASE" "ddr_ctrl.v(153) " "Verilog HDL warning at ddr_ctrl.v(153): case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness" {  } { { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 153 0 0 } }  } 0 10763 "Verilog HDL warning at %1!s!: case statement has overlapping case item expressions with non-constant or don't care bits - unable to check case statement for completeness" 0 0 "Analysis & Synthesis" 0 -1 1765447224793 "|ddr_ctrl"}
{ "Warning" "WVRFX_L2_VERI_FULL_CASE_DIRECTIVE_EFFECTIVE" "ddr_ctrl.v(153) " "Verilog HDL Case Statement warning at ddr_ctrl.v(153): honored full_case synthesis attribute - differences between design synthesis and simulation may occur" {  } { { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 153 0 0 } }  } 0 10208 "Verilog HDL Case Statement warning at %1!s!: honored full_case synthesis attribute - differences between design synthesis and simulation may occur" 0 0 "Analysis & Synthesis" 0 -1 1765447224793 "|ddr_ctrl"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_gen clk_gen:clk_gen_inst " "Elaborating entity \"clk_gen\" for hierarchy \"clk_gen:clk_gen_inst\"" {  } { { "ddr_ctrl.v" "clk_gen_inst" { Text "E:/FPGA/puart2/ddr_ctrl.v" 204 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765447224811 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll clk_gen:clk_gen_inst\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"clk_gen:clk_gen_inst\|altpll:altpll_component\"" {  } { { "clk_gen.v" "altpll_component" { Text "E:/FPGA/puart2/clk_gen.v" 94 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765447224854 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "clk_gen:clk_gen_inst\|altpll:altpll_component " "Elaborated megafunction instantiation \"clk_gen:clk_gen_inst\|altpll:altpll_component\"" {  } { { "clk_gen.v" "" { Text "E:/FPGA/puart2/clk_gen.v" 94 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765447224855 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "clk_gen:clk_gen_inst\|altpll:altpll_component " "Instantiated megafunction \"clk_gen:clk_gen_inst\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 625 " "Parameter \"clk0_divide_by\" = \"625\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 6 " "Parameter \"clk0_multiply_by\" = \"6\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 625 " "Parameter \"clk1_divide_by\" = \"625\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 12 " "Parameter \"clk1_multiply_by\" = \"12\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 0 " "Parameter \"clk1_phase_shift\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 83333 " "Parameter \"inclk0_input_frequency\" = \"83333\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family MAX 10 " "Parameter \"intended_device_family\" = \"MAX 10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=clk_gen " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=clk_gen\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_UNUSED " "Parameter \"port_locked\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Parameter \"port_clk2\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1765447224856 ""}  } { { "clk_gen.v" "" { Text "E:/FPGA/puart2/clk_gen.v" 94 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1765447224856 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/clk_gen_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/clk_gen_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_gen_altpll " "Found entity 1: clk_gen_altpll" {  } { { "db/clk_gen_altpll.v" "" { Text "E:/FPGA/puart2/db/clk_gen_altpll.v" 29 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1765447224906 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765447224906 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_gen_altpll clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated " "Elaborating entity \"clk_gen_altpll\" for hierarchy \"clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\"" {  } { { "altpll.tdf" "auto_generated" { Text "e:/quartuslite/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765447224906 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi_master_2164 spi_master_2164:u_spi_master_2164 " "Elaborating entity \"spi_master_2164\" for hierarchy \"spi_master_2164:u_spi_master_2164\"" {  } { { "ddr_ctrl.v" "u_spi_master_2164" { Text "E:/FPGA/puart2/ddr_ctrl.v" 221 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765447224910 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi_master_esp32 spi_master_esp32:tranfer " "Elaborating entity \"spi_master_esp32\" for hierarchy \"spi_master_esp32:tranfer\"" {  } { { "ddr_ctrl.v" "tranfer" { Text "E:/FPGA/puart2/ddr_ctrl.v" 234 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765447224911 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 spi_master_esp32.v(50) " "Verilog HDL assignment warning at spi_master_esp32.v(50): truncated value with size 32 to match size of target (4)" {  } { { "spi_master_esp32.v" "" { Text "E:/FPGA/puart2/spi_master_esp32.v" 50 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1765447224912 "|ddr_ctrl|spi_master_esp32:tranfer"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_tx uart_tx:u_uart_pc " "Elaborating entity \"uart_tx\" for hierarchy \"uart_tx:u_uart_pc\"" {  } { { "ddr_ctrl.v" "u_uart_pc" { Text "E:/FPGA/puart2/ddr_ctrl.v" 243 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765447224913 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 uart_tx.v(32) " "Verilog HDL assignment warning at uart_tx.v(32): truncated value with size 32 to match size of target (16)" {  } { { "uart_tx.v" "" { Text "E:/FPGA/puart2/uart_tx.v" 32 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1765447224914 "|ddr_ctrl|uart_tx:u_uart_pc"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 uart_tx.v(74) " "Verilog HDL assignment warning at uart_tx.v(74): truncated value with size 32 to match size of target (4)" {  } { { "uart_tx.v" "" { Text "E:/FPGA/puart2/uart_tx.v" 74 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1765447224914 "|ddr_ctrl|uart_tx:u_uart_pc"}
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "spi_master_2164.v" "" { Text "E:/FPGA/puart2/spi_master_2164.v" 11 -1 0 } } { "uart_tx.v" "" { Text "E:/FPGA/puart2/uart_tx.v" 43 -1 0 } } { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 146 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 -1 1765447225299 ""}
{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Analysis & Synthesis" 0 -1 1765447225299 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "MOSI_ESP32 GND " "Pin \"MOSI_ESP32\" is stuck at GND" {  } { { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 12 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1765447225343 "|ddr_ctrl|MOSI_ESP32"} { "Warning" "WMLS_MLS_STUCK_PIN" "cs_ESP32 VCC " "Pin \"cs_ESP32\" is stuck at VCC" {  } { { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 13 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1765447225343 "|ddr_ctrl|cs_ESP32"} { "Warning" "WMLS_MLS_STUCK_PIN" "sclk_ESP32 GND " "Pin \"sclk_ESP32\" is stuck at GND" {  } { { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 14 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1765447225343 "|ddr_ctrl|sclk_ESP32"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1765447225343 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1765447225397 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "6 " "6 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1765447225805 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/FPGA/puart2/output_files/intan_m10.map.smsg " "Generated suppressed messages file E:/FPGA/puart2/output_files/intan_m10.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1765447225846 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "1 0 1 0 0 " "Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1765447225934 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1765447225934 ""}
{ "Warning" "WCUT_PLL_MULT_DIV_SPECIFIED_CLOCK_NOT_CONNECTED" "clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|pll1 CLK\[1\] clk1_multiply_by clk1_divide_by " "PLL \"clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|pll1\" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK\[1\] is not connected" {  } { { "db/clk_gen_altpll.v" "" { Text "E:/FPGA/puart2/db/clk_gen_altpll.v" 43 -1 0 } } { "altpll.tdf" "" { Text "e:/quartuslite/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "clk_gen.v" "" { Text "E:/FPGA/puart2/clk_gen.v" 94 0 0 } } { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 204 0 0 } }  } 0 15899 "PLL \"%1!s!\" has parameters %3!s! and %4!s! specified but port %2!s! is not connected" 0 0 "Analysis & Synthesis" 0 -1 1765447225956 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "213 " "Implemented 213 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Implemented 4 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1765447225973 ""} { "Info" "ICUT_CUT_TM_OPINS" "9 " "Implemented 9 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1765447225973 ""} { "Info" "ICUT_CUT_TM_LCELLS" "199 " "Implemented 199 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1765447225973 ""} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Implemented 1 PLLs" {  } {  } 0 21065 "Implemented %1!d! PLLs" 0 0 "Design Software" 0 -1 1765447225973 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1765447225973 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4766 " "Peak virtual memory: 4766 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1765447225990 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 11 18:00:25 2025 " "Processing ended: Thu Dec 11 18:00:25 2025" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1765447225990 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1765447225990 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1765447225990 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1765447225990 ""}