module ddr_ctrl_tb();

reg sys_clk;
reg rst_n;
reg miso;

wire mosi;
wire cs_n;
wire sclk;

wire [24:0] state;
wire [24:0] next;
wire [31:0] dout;



ddr_ctrl uut(
	.sys_clk(sys_clk),
	.rst_n(rst_n),
	.miso(miso),
	.mosi(mosi),
	.cs_n(cs_n),
	.sclk(sclk),
	.state(state),
	.next(next),
	.dout(dout)
);



initial
begin
	rst_n = 0;
	miso = 0;
	#50 rst_n = 1;
	#12000 $finish;
end



initial begin
	forever begin
		#5 sys_clk = 0;
		#5 sys_clk = 1;
	end
end



initial begin
	forever begin
		#50 miso = 0;
		#50 miso = 1;
	end
end


initial begin
	$fsdbDumpfile("ddr_ctrl.fsdb");
	$fsdbDumpvars();
end




endmodule