# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017  Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Intel Program License 
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors.  Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
# Date created = 20:28:17  April 12, 2024
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		intan_m10_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus Prime software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M08SAM153C8G
set_global_assignment -name TOP_LEVEL_ENTITY ddr_ctrl
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:28:17  APRIL 12, 2024"
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
set_location_assignment PIN_J5 -to sys_clk
set_location_assignment PIN_P6 -to cs_n
set_location_assignment PIN_P4 -to miso
set_location_assignment PIN_L7 -to mosi
set_location_assignment PIN_J14 -to rst_n
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cs_n
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to miso
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to mosi
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to rst_n
set_location_assignment PIN_R5 -to sclk
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sclk
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sys_clk
set_location_assignment PIN_J12 -to test_flag
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to test_flag
set_location_assignment PIN_N15 -to test_flag_led
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to test_flag_led
set_location_assignment PIN_M12 -to convert_flag_led
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to convert_flag_led
set_global_assignment -name NUM_PARALLEL_PROCESSORS 4
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_B14 -to sclk_ESP32
set_location_assignment PIN_B13 -to cs_ESP32
set_location_assignment PIN_A14 -to MOSI_ESP32
set_global_assignment -name VERILOG_FILE spi_master_2164.v
set_global_assignment -name VERILOG_FILE ddr_ctrl.v
set_global_assignment -name QIP_FILE clk_gen.qip
set_global_assignment -name VERILOG_FILE ../../20240625.v
set_global_assignment -name VERILOG_FILE spi_master_esp32.v
set_global_assignment -name VERILOG_FILE uart_tx.v
set_location_assignment PIN_P8 -to tx
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to tx
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cs_ESP32
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MOSI_ESP32
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sclk_ESP32
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top