TimeQuest Timing Analyzer report for intan_m10 Thu Dec 11 18:00:41 2025 Quartus Prime Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. TimeQuest Timing Analyzer Summary 3. Parallel Compilation 4. Clocks 5. Slow 1200mV 85C Model Fmax Summary 6. Slow 1200mV 85C Model Setup Summary 7. Slow 1200mV 85C Model Hold Summary 8. Slow 1200mV 85C Model Recovery Summary 9. Slow 1200mV 85C Model Removal Summary 10. Slow 1200mV 85C Model Minimum Pulse Width Summary 11. Slow 1200mV 85C Model Metastability Summary 12. Slow 1200mV 0C Model Fmax Summary 13. Slow 1200mV 0C Model Setup Summary 14. Slow 1200mV 0C Model Hold Summary 15. Slow 1200mV 0C Model Recovery Summary 16. Slow 1200mV 0C Model Removal Summary 17. Slow 1200mV 0C Model Minimum Pulse Width Summary 18. Slow 1200mV 0C Model Metastability Summary 19. Fast 1200mV 0C Model Setup Summary 20. Fast 1200mV 0C Model Hold Summary 21. Fast 1200mV 0C Model Recovery Summary 22. Fast 1200mV 0C Model Removal Summary 23. Fast 1200mV 0C Model Minimum Pulse Width Summary 24. Fast 1200mV 0C Model Metastability Summary 25. Multicorner Timing Analysis Summary 26. Board Trace Model Assignments 27. Input Transition Times 28. Signal Integrity Metrics (Slow 1200mv 0c Model) 29. Signal Integrity Metrics (Slow 1200mv 85c Model) 30. Signal Integrity Metrics (Fast 1200mv 0c Model) 31. Setup Transfers 32. Hold Transfers 33. Report TCCS 34. Report RSKM 35. Unconstrained Paths Summary 36. Clock Status Summary 37. Unconstrained Input Ports 38. Unconstrained Output Ports 39. Unconstrained Input Ports 40. Unconstrained Output Ports 41. TimeQuest Timing Analyzer Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 2017 Intel Corporation. All rights reserved. Your use of Intel Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Intel Program License Subscription Agreement, the Intel Quartus Prime License Agreement, the Intel FPGA IP License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Intel and sold by Intel or its authorized distributors. Please refer to the applicable agreement for further details. +-----------------------------------------------------------------------------+ ; TimeQuest Timing Analyzer Summary ; +-----------------------+-----------------------------------------------------+ ; Quartus Prime Version ; Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition ; ; Timing Analyzer ; TimeQuest ; ; Revision Name ; intan_m10 ; ; Device Family ; MAX 10 ; ; Device Name ; 10M08SAM153C8G ; ; Timing Models ; Final ; ; Delay Model ; Combined ; ; Rise/Fall Delays ; Enabled ; +-----------------------+-----------------------------------------------------+ +------------------------------------------+ ; Parallel Compilation ; +----------------------------+-------------+ ; Processors ; Number ; +----------------------------+-------------+ ; Number detected on machine ; 8 ; ; Maximum allowed ; 4 ; ; ; ; ; Average used ; 1.10 ; ; Maximum used ; 4 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; ; Processor 2 ; 3.4% ; ; Processors 3-4 ; 3.4% ; +----------------------------+-------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Clocks ; +----------------------------------------------------------+-----------+----------+------------+-------+----------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------+------------------------------------------------------------+--------------------------------------------------------------+ ; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; +----------------------------------------------------------+-----------+----------+------------+-------+----------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------+------------------------------------------------------------+--------------------------------------------------------------+ ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 8680.520 ; 0.12 MHz ; 0.000 ; 4340.260 ; 50.00 ; 625 ; 6 ; ; ; ; ; false ; sys_clk ; clk_gen_inst|altpll_component|auto_generated|pll1|inclk[0] ; { clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] } ; ; spi_master_2164:u_spi_master_2164|cs_n ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { spi_master_2164:u_spi_master_2164|cs_n } ; ; sys_clk ; Base ; 83.333 ; 12.0 MHz ; 0.000 ; 41.666 ; ; ; ; ; ; ; ; ; ; ; { sys_clk } ; +----------------------------------------------------------+-----------+----------+------------+-------+----------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------+------------------------------------------------------------+--------------------------------------------------------------+ +------------------------------------------------------------------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Fmax Summary ; +------------+-----------------+----------------------------------------------------------+------------------------------------------------+ ; Fmax ; Restricted Fmax ; Clock Name ; Note ; +------------+-----------------+----------------------------------------------------------+------------------------------------------------+ ; 154.2 MHz ; 154.2 MHz ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; ; ; 609.01 MHz ; 402.09 MHz ; spi_master_2164:u_spi_master_2164|cs_n ; limit due to minimum period restriction (tmin) ; +------------+-----------------+----------------------------------------------------------+------------------------------------------------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. +-----------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Setup Summary ; +----------------------------------------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------+--------+---------------+ ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; -6.744 ; -6.744 ; ; spi_master_2164:u_spi_master_2164|cs_n ; -0.642 ; -7.912 ; +----------------------------------------------------------+--------+---------------+ +----------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Hold Summary ; +----------------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------+-------+---------------+ ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.362 ; 0.000 ; ; spi_master_2164:u_spi_master_2164|cs_n ; 0.363 ; 0.000 ; +----------------------------------------------------------+-------+---------------+ ------------------------------------------ ; Slow 1200mV 85C Model Recovery Summary ; ------------------------------------------ No paths to report. ----------------------------------------- ; Slow 1200mV 85C Model Removal Summary ; ----------------------------------------- No paths to report. +-------------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Minimum Pulse Width Summary ; +----------------------------------------------------------+----------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------+----------+---------------+ ; spi_master_2164:u_spi_master_2164|cs_n ; -1.487 ; -46.097 ; ; sys_clk ; 41.554 ; 0.000 ; ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 4339.989 ; 0.000 ; +----------------------------------------------------------+----------+---------------+ ----------------------------------------------- ; Slow 1200mV 85C Model Metastability Summary ; ----------------------------------------------- The design MTBF is not calculated because there are no specified synchronizers in the design. Number of Synchronizer Chains Found: 1 Shortest Synchronizer Chain: 2 Registers Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 Worst Case Available Settling Time: 17358.585 ns +------------------------------------------------------------------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Fmax Summary ; +------------+-----------------+----------------------------------------------------------+------------------------------------------------+ ; Fmax ; Restricted Fmax ; Clock Name ; Note ; +------------+-----------------+----------------------------------------------------------+------------------------------------------------+ ; 164.42 MHz ; 164.42 MHz ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; ; ; 642.67 MHz ; 402.09 MHz ; spi_master_2164:u_spi_master_2164|cs_n ; limit due to minimum period restriction (tmin) ; +------------+-----------------+----------------------------------------------------------+------------------------------------------------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. +-----------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Setup Summary ; +----------------------------------------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------+--------+---------------+ ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; -6.215 ; -6.215 ; ; spi_master_2164:u_spi_master_2164|cs_n ; -0.556 ; -5.863 ; +----------------------------------------------------------+--------+---------------+ +----------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Hold Summary ; +----------------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------+-------+---------------+ ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.324 ; 0.000 ; ; spi_master_2164:u_spi_master_2164|cs_n ; 0.325 ; 0.000 ; +----------------------------------------------------------+-------+---------------+ ----------------------------------------- ; Slow 1200mV 0C Model Recovery Summary ; ----------------------------------------- No paths to report. ---------------------------------------- ; Slow 1200mV 0C Model Removal Summary ; ---------------------------------------- No paths to report. +-------------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Minimum Pulse Width Summary ; +----------------------------------------------------------+----------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------+----------+---------------+ ; spi_master_2164:u_spi_master_2164|cs_n ; -1.487 ; -46.097 ; ; sys_clk ; 41.555 ; 0.000 ; ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 4340.000 ; 0.000 ; +----------------------------------------------------------+----------+---------------+ ---------------------------------------------- ; Slow 1200mV 0C Model Metastability Summary ; ---------------------------------------------- The design MTBF is not calculated because there are no specified synchronizers in the design. Number of Synchronizer Chains Found: 1 Shortest Synchronizer Chain: 2 Registers Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 Worst Case Available Settling Time: 17358.726 ns +-----------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Setup Summary ; +----------------------------------------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------+--------+---------------+ ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; -2.312 ; -2.312 ; ; spi_master_2164:u_spi_master_2164|cs_n ; 0.304 ; 0.000 ; +----------------------------------------------------------+--------+---------------+ +----------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Hold Summary ; +----------------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------+-------+---------------+ ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.151 ; 0.000 ; ; spi_master_2164:u_spi_master_2164|cs_n ; 0.151 ; 0.000 ; +----------------------------------------------------------+-------+---------------+ ----------------------------------------- ; Fast 1200mV 0C Model Recovery Summary ; ----------------------------------------- No paths to report. ---------------------------------------- ; Fast 1200mV 0C Model Removal Summary ; ---------------------------------------- No paths to report. +-------------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Minimum Pulse Width Summary ; +----------------------------------------------------------+----------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------+----------+---------------+ ; spi_master_2164:u_spi_master_2164|cs_n ; -1.000 ; -31.000 ; ; sys_clk ; 41.180 ; 0.000 ; ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 4340.041 ; 0.000 ; +----------------------------------------------------------+----------+---------------+ ---------------------------------------------- ; Fast 1200mV 0C Model Metastability Summary ; ---------------------------------------------- The design MTBF is not calculated because there are no specified synchronizers in the design. Number of Synchronizer Chains Found: 1 Shortest Synchronizer Chain: 2 Registers Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 Worst Case Available Settling Time: 17359.966 ns +------------------------------------------------------------------------------------------------------------------------+ ; Multicorner Timing Analysis Summary ; +-----------------------------------------------------------+---------+-------+----------+---------+---------------------+ ; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; +-----------------------------------------------------------+---------+-------+----------+---------+---------------------+ ; Worst-case Slack ; -6.744 ; 0.151 ; N/A ; N/A ; -1.487 ; ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; -6.744 ; 0.151 ; N/A ; N/A ; 4339.989 ; ; spi_master_2164:u_spi_master_2164|cs_n ; -0.642 ; 0.151 ; N/A ; N/A ; -1.487 ; ; sys_clk ; N/A ; N/A ; N/A ; N/A ; 41.180 ; ; Design-wide TNS ; -14.656 ; 0.0 ; 0.0 ; 0.0 ; -46.097 ; ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; -6.744 ; 0.000 ; N/A ; N/A ; 0.000 ; ; spi_master_2164:u_spi_master_2164|cs_n ; -7.912 ; 0.000 ; N/A ; N/A ; -46.097 ; ; sys_clk ; N/A ; N/A ; N/A ; N/A ; 0.000 ; +-----------------------------------------------------------+---------+-------+----------+---------+---------------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Board Trace Model Assignments ; +------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ ; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; +------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ ; mosi ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; cs_n ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; sclk ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; MOSI_ESP32 ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; cs_ESP32 ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; sclk_ESP32 ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; tx ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; test_flag_led ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; convert_flag_led ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; ~ALTERA_TDO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +---------------------------------------------------------------------------------+ ; Input Transition Times ; +---------------------+-----------------------+-----------------+-----------------+ ; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; +---------------------+-----------------------+-----------------+-----------------+ ; test_flag ; 3.3-V LVCMOS ; 2640 ps ; 2640 ps ; ; rst_n ; 3.3-V LVCMOS ; 2640 ps ; 2640 ps ; ; sys_clk ; 3.3-V LVCMOS ; 2640 ps ; 2640 ps ; ; miso ; 3.3-V LVCMOS ; 2640 ps ; 2640 ps ; ; ~ALTERA_TMS~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; ; ~ALTERA_TCK~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; ; ~ALTERA_TDI~ ; 2.5 V Schmitt Trigger ; 2000 ps ; 2000 ps ; ; ~ALTERA_CONFIG_SEL~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; ~ALTERA_nCONFIG~ ; 3.3 V Schmitt Trigger ; 2640 ps ; 2640 ps ; ; ~ALTERA_nSTATUS~ ; 3.3 V Schmitt Trigger ; 2640 ps ; 2640 ps ; ; ~ALTERA_CONF_DONE~ ; 3.3 V Schmitt Trigger ; 2640 ps ; 2640 ps ; +---------------------+-----------------------+-----------------+-----------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Signal Integrity Metrics (Slow 1200mv 0c Model) ; +------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; mosi ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0411 V ; 0.283 V ; 0.209 V ; 9e-10 s ; 1.03e-09 s ; No ; No ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0411 V ; 0.283 V ; 0.209 V ; 9e-10 s ; 1.03e-09 s ; No ; No ; ; cs_n ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0417 V ; 0.287 V ; 0.209 V ; 8.99e-10 s ; 1.03e-09 s ; No ; No ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0417 V ; 0.287 V ; 0.209 V ; 8.99e-10 s ; 1.03e-09 s ; No ; No ; ; sclk ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0464 V ; 0.207 V ; 0.276 V ; 8.51e-10 s ; 8.52e-10 s ; No ; No ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0464 V ; 0.207 V ; 0.276 V ; 8.51e-10 s ; 8.52e-10 s ; No ; No ; ; MOSI_ESP32 ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0463 V ; 0.208 V ; 0.277 V ; 8.5e-10 s ; 8.53e-10 s ; No ; No ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0463 V ; 0.208 V ; 0.277 V ; 8.5e-10 s ; 8.53e-10 s ; No ; No ; ; cs_ESP32 ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0464 V ; 0.207 V ; 0.276 V ; 8.51e-10 s ; 8.52e-10 s ; No ; No ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0464 V ; 0.207 V ; 0.276 V ; 8.51e-10 s ; 8.52e-10 s ; No ; No ; ; sclk_ESP32 ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0463 V ; 0.208 V ; 0.277 V ; 8.5e-10 s ; 8.53e-10 s ; No ; No ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0463 V ; 0.208 V ; 0.277 V ; 8.5e-10 s ; 8.53e-10 s ; No ; No ; ; tx ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0464 V ; 0.207 V ; 0.276 V ; 8.51e-10 s ; 8.52e-10 s ; No ; No ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0464 V ; 0.207 V ; 0.276 V ; 8.51e-10 s ; 8.52e-10 s ; No ; No ; ; test_flag_led ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0464 V ; 0.207 V ; 0.276 V ; 8.51e-10 s ; 8.52e-10 s ; No ; No ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0464 V ; 0.207 V ; 0.276 V ; 8.51e-10 s ; 8.52e-10 s ; No ; No ; ; convert_flag_led ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0464 V ; 0.207 V ; 0.276 V ; 8.51e-10 s ; 8.52e-10 s ; No ; No ; 3.08 V ; 3.68e-08 V ; 3.12 V ; -0.0464 V ; 0.207 V ; 0.276 V ; 8.51e-10 s ; 8.52e-10 s ; No ; No ; ; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.49e-09 V ; 2.38 V ; -0.0505 V ; 0.23 V ; 0.155 V ; 4.84e-10 s ; 6.18e-10 s ; Yes ; No ; 2.32 V ; 7.49e-09 V ; 2.38 V ; -0.0505 V ; 0.23 V ; 0.155 V ; 4.84e-10 s ; 6.18e-10 s ; Yes ; No ; +------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Signal Integrity Metrics (Slow 1200mv 85c Model) ; +------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; mosi ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.018 V ; 0.27 V ; 0.216 V ; 1.11e-09 s ; 1.22e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.018 V ; 0.27 V ; 0.216 V ; 1.11e-09 s ; 1.22e-09 s ; Yes ; Yes ; ; cs_n ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.018 V ; 0.27 V ; 0.217 V ; 1.11e-09 s ; 1.22e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.018 V ; 0.27 V ; 0.217 V ; 1.11e-09 s ; 1.22e-09 s ; Yes ; Yes ; ; sclk ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; ; MOSI_ESP32 ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0199 V ; 0.191 V ; 0.262 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0199 V ; 0.191 V ; 0.262 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; ; cs_ESP32 ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; ; sclk_ESP32 ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0199 V ; 0.191 V ; 0.262 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0199 V ; 0.191 V ; 0.262 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; ; tx ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; ; test_flag_led ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; ; convert_flag_led ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; 3.08 V ; 2.3e-06 V ; 3.1 V ; -0.0196 V ; 0.191 V ; 0.261 V ; 1.03e-09 s ; 1.05e-09 s ; Yes ; Yes ; ; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.88e-07 V ; 2.36 V ; -0.0211 V ; 0.162 V ; 0.122 V ; 6.58e-10 s ; 7.79e-10 s ; No ; Yes ; 2.32 V ; 7.88e-07 V ; 2.36 V ; -0.0211 V ; 0.162 V ; 0.122 V ; 6.58e-10 s ; 7.79e-10 s ; No ; Yes ; +------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Signal Integrity Metrics (Fast 1200mv 0c Model) ; +------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; mosi ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 8.93e-07 V ; 3.52 V ; -0.0321 V ; 0.324 V ; 0.176 V ; 6.87e-10 s ; 8.14e-10 s ; No ; Yes ; 3.46 V ; 8.93e-07 V ; 3.52 V ; -0.0321 V ; 0.324 V ; 0.176 V ; 6.87e-10 s ; 8.14e-10 s ; No ; Yes ; ; cs_n ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0325 V ; 0.324 V ; 0.176 V ; 6.87e-10 s ; 8.14e-10 s ; No ; Yes ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0325 V ; 0.324 V ; 0.176 V ; 6.87e-10 s ; 8.14e-10 s ; No ; Yes ; ; sclk ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.252 V ; 6.55e-10 s ; 6.68e-10 s ; No ; Yes ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.252 V ; 6.55e-10 s ; 6.68e-10 s ; No ; Yes ; ; MOSI_ESP32 ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.251 V ; 6.54e-10 s ; 6.68e-10 s ; No ; Yes ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.251 V ; 6.54e-10 s ; 6.68e-10 s ; No ; Yes ; ; cs_ESP32 ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.252 V ; 6.55e-10 s ; 6.68e-10 s ; No ; Yes ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.252 V ; 6.55e-10 s ; 6.68e-10 s ; No ; Yes ; ; sclk_ESP32 ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.251 V ; 6.54e-10 s ; 6.68e-10 s ; No ; Yes ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.251 V ; 6.54e-10 s ; 6.68e-10 s ; No ; Yes ; ; tx ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.252 V ; 6.55e-10 s ; 6.68e-10 s ; No ; Yes ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.252 V ; 6.55e-10 s ; 6.68e-10 s ; No ; Yes ; ; test_flag_led ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.252 V ; 6.55e-10 s ; 6.68e-10 s ; No ; Yes ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.252 V ; 6.55e-10 s ; 6.68e-10 s ; No ; Yes ; ; convert_flag_led ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.252 V ; 6.55e-10 s ; 6.68e-10 s ; No ; Yes ; 3.46 V ; 8.93e-07 V ; 3.53 V ; -0.0306 V ; 0.247 V ; 0.252 V ; 6.55e-10 s ; 6.68e-10 s ; No ; Yes ; ; ~ALTERA_TDO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0395 V ; 0.361 V ; 0.109 V ; 3.1e-10 s ; 4.41e-10 s ; No ; Yes ; 2.62 V ; 1.68e-07 V ; 2.73 V ; -0.0395 V ; 0.361 V ; 0.109 V ; 3.1e-10 s ; 4.41e-10 s ; No ; Yes ; +------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Setup Transfers ; +----------------------------------------------------------+----------------------------------------------------------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +----------------------------------------------------------+----------------------------------------------------------+----------+----------+----------+----------+ ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 1138 ; 0 ; 0 ; 0 ; ; spi_master_2164:u_spi_master_2164|cs_n ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 0 ; 179 ; 0 ; 0 ; ; spi_master_2164:u_spi_master_2164|cs_n ; spi_master_2164:u_spi_master_2164|cs_n ; 0 ; 0 ; 0 ; 31 ; +----------------------------------------------------------+----------------------------------------------------------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. +-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Hold Transfers ; +----------------------------------------------------------+----------------------------------------------------------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +----------------------------------------------------------+----------------------------------------------------------+----------+----------+----------+----------+ ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 1138 ; 0 ; 0 ; 0 ; ; spi_master_2164:u_spi_master_2164|cs_n ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; 0 ; 179 ; 0 ; 0 ; ; spi_master_2164:u_spi_master_2164|cs_n ; spi_master_2164:u_spi_master_2164|cs_n ; 0 ; 0 ; 0 ; 31 ; +----------------------------------------------------------+----------------------------------------------------------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. --------------- ; Report TCCS ; --------------- No dedicated SERDES Transmitter circuitry present in device or used in design --------------- ; Report RSKM ; --------------- No non-DPA dedicated SERDES Receiver circuitry present in device or used in design +------------------------------------------------+ ; Unconstrained Paths Summary ; +---------------------------------+-------+------+ ; Property ; Setup ; Hold ; +---------------------------------+-------+------+ ; Illegal Clocks ; 0 ; 0 ; ; Unconstrained Clocks ; 0 ; 0 ; ; Unconstrained Input Ports ; 3 ; 3 ; ; Unconstrained Input Port Paths ; 139 ; 139 ; ; Unconstrained Output Ports ; 6 ; 6 ; ; Unconstrained Output Port Paths ; 6 ; 6 ; +---------------------------------+-------+------+ +-----------------------------------------------------------------------------------------------------------------------------------------------+ ; Clock Status Summary ; +----------------------------------------------------------+----------------------------------------------------------+-----------+-------------+ ; Target ; Clock ; Type ; Status ; +----------------------------------------------------------+----------------------------------------------------------+-----------+-------------+ ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] ; Generated ; Constrained ; ; spi_master_2164:u_spi_master_2164|cs_n ; spi_master_2164:u_spi_master_2164|cs_n ; Base ; Constrained ; ; sys_clk ; sys_clk ; Base ; Constrained ; +----------------------------------------------------------+----------------------------------------------------------+-----------+-------------+ +---------------------------------------------------------------------------------------------------+ ; Unconstrained Input Ports ; +------------+--------------------------------------------------------------------------------------+ ; Input Port ; Comment ; +------------+--------------------------------------------------------------------------------------+ ; miso ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; rst_n ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; test_flag ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +------------+--------------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------+ ; Unconstrained Output Ports ; +------------------+---------------------------------------------------------------------------------------+ ; Output Port ; Comment ; +------------------+---------------------------------------------------------------------------------------+ ; convert_flag_led ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; cs_n ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; mosi ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; sclk ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; test_flag_led ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; tx ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +------------------+---------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------------------+ ; Unconstrained Input Ports ; +------------+--------------------------------------------------------------------------------------+ ; Input Port ; Comment ; +------------+--------------------------------------------------------------------------------------+ ; miso ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; rst_n ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ; test_flag ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +------------+--------------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------+ ; Unconstrained Output Ports ; +------------------+---------------------------------------------------------------------------------------+ ; Output Port ; Comment ; +------------------+---------------------------------------------------------------------------------------+ ; convert_flag_led ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; cs_n ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; mosi ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; sclk ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; test_flag_led ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ; tx ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +------------------+---------------------------------------------------------------------------------------+ +------------------------------------+ ; TimeQuest Timing Analyzer Messages ; +------------------------------------+ Info: ******************************************************************* Info: Running Quartus Prime TimeQuest Timing Analyzer Info: Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition Info: Processing started: Thu Dec 11 18:00:37 2025 Info: Command: quartus_sta intan_m10 -c intan_m10 Info: qsta_default_script.tcl version: #3 Info (20032): Parallel compilation is enabled and will use up to 4 processors Info (21077): Low junction temperature is 0 degrees C Info (21077): High junction temperature is 85 degrees C Critical Warning (332012): Synopsys Design Constraints File file not found: 'intan_m10.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. Info (332142): No user constrained generated clocks found in the design. Calling "derive_pll_clocks -create_base_clocks" Info (332110): Deriving PLL clocks Info (332110): create_clock -period 83.333 -waveform {0.000 41.666} -name sys_clk sys_clk Info (332110): create_generated_clock -source {clk_gen_inst|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 625 -multiply_by 6 -duty_cycle 50.00 -name {clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]} {clk_gen_inst|altpll_component|auto_generated|pll1|clk[0]} Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" Info (332105): Deriving Clocks Info (332105): create_clock -period 1.000 -name spi_master_2164:u_spi_master_2164|cs_n spi_master_2164:u_spi_master_2164|cs_n Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Analyzing Slow 1200mV 85C Model Info: Can't run Report Timing Closure Recommendations. The current device family is not supported. Critical Warning (332148): Timing requirements not met Info (332146): Worst-case setup slack is -6.744 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -6.744 -6.744 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] Info (332119): -0.642 -7.912 spi_master_2164:u_spi_master_2164|cs_n Info (332146): Worst-case hold slack is 0.362 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.362 0.000 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] Info (332119): 0.363 0.000 spi_master_2164:u_spi_master_2164|cs_n Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is -1.487 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -1.487 -46.097 spi_master_2164:u_spi_master_2164|cs_n Info (332119): 41.554 0.000 sys_clk Info (332119): 4339.989 0.000 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] Info (332114): Report Metastability: Found 1 synchronizer chains. Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design. Info (332114): Number of Synchronizer Chains Found: 1 Info (332114): Shortest Synchronizer Chain: 2 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 Info (332114): Worst Case Available Settling Time: 17358.585 ns Info (332114): Info: Analyzing Slow 1200mV 0C Model Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Critical Warning (332148): Timing requirements not met Info (332146): Worst-case setup slack is -6.215 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -6.215 -6.215 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] Info (332119): -0.556 -5.863 spi_master_2164:u_spi_master_2164|cs_n Info (332146): Worst-case hold slack is 0.324 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.324 0.000 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] Info (332119): 0.325 0.000 spi_master_2164:u_spi_master_2164|cs_n Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is -1.487 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -1.487 -46.097 spi_master_2164:u_spi_master_2164|cs_n Info (332119): 41.555 0.000 sys_clk Info (332119): 4340.000 0.000 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] Info (332114): Report Metastability: Found 1 synchronizer chains. Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design. Info (332114): Number of Synchronizer Chains Found: 1 Info (332114): Shortest Synchronizer Chain: 2 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 Info (332114): Worst Case Available Settling Time: 17358.726 ns Info (332114): Info: Analyzing Fast 1200mV 0C Model Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Critical Warning (332148): Timing requirements not met Info (332146): Worst-case setup slack is -2.312 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -2.312 -2.312 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] Info (332119): 0.304 0.000 spi_master_2164:u_spi_master_2164|cs_n Info (332146): Worst-case hold slack is 0.151 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): 0.151 0.000 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] Info (332119): 0.151 0.000 spi_master_2164:u_spi_master_2164|cs_n Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is -1.000 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== Info (332119): -1.000 -31.000 spi_master_2164:u_spi_master_2164|cs_n Info (332119): 41.180 0.000 sys_clk Info (332119): 4340.041 0.000 clk_gen_inst|altpll_component|auto_generated|pll1|clk[0] Info (332114): Report Metastability: Found 1 synchronizer chains. Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design. Info (332114): Number of Synchronizer Chains Found: 1 Info (332114): Shortest Synchronizer Chain: 2 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 Info (332114): Worst Case Available Settling Time: 17359.966 ns Info (332114): Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings Info: Peak virtual memory: 4784 megabytes Info: Processing ended: Thu Dec 11 18:00:41 2025 Info: Elapsed time: 00:00:04 Info: Total CPU time (on all processors): 00:00:03