module spi_master_2164(
	input 						sys_clk,
	input 						rst_n,
	input 			[15:0] 	din,
	input    wire           start,
	output 	reg 	[15:0] 	dout,
	output 	reg 				done,
	
	// connect to 2164
	output	reg				sclk,
	output 	reg				cs_n,
	output 	reg				mosi,
	input 						miso,
	
	// for test only
	output reg [6:0]	cnt	// count to 47
);

	localparam cnt_total = 'd42;

	reg [15:0] dout_r;

	
//================== cnt =====================//
	always @ (posedge sys_clk or negedge rst_n) begin
		if(!rst_n)
			cnt <= 'd0;
		else if(cnt == cnt_total)
			cnt <= 'd0;
		else
		if (start) begin
			cnt <= cnt + 1'b1;
	end
end
	
	
//================== send data ===============//
	always @ (posedge sys_clk or negedge rst_n) begin
		if(!rst_n) begin
			sclk <= 1'b0;
			cs_n <= 1'b1;
			mosi <= 1'b0;
		end
		else begin
		
			case(cnt)
				6'd0: 	begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end
				6'd1: 	begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end
				6'd2: 	begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= 1'b0; end
				6'd3:		begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= 1'b0; end
				6'd4: 	begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[15]; end
				6'd5: 	begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[15]; dout_r <= {dout_r[14:0],miso}; end
				6'd6: 	begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[14]; end
				6'd7: 	begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[14]; dout_r <= {dout_r[14:0],miso}; end
				6'd8: 	begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[13]; end
				6'd9: 	begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[13]; dout_r <= {dout_r[14:0],miso}; end
				6'd10: 	begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[12]; end
				6'd11: 	begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[12]; dout_r <= {dout_r[14:0],miso}; end
				6'd12: 	begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[11]; end
				6'd13: 	begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[11]; dout_r <= {dout_r[14:0],miso}; end
				6'd14: 	begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[10]; end
				6'd15: 	begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[10]; dout_r <= {dout_r[14:0],miso}; end
				6'd16: 	begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[9]; end
				6'd17: 	begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[9]; dout_r <= {dout_r[14:0],miso}; end
				6'd18: 	begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[8]; end
				6'd19: 	begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[8]; dout_r <= {dout_r[14:0],miso}; end
				6'd20: 	begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[7]; end
				6'd21: 	begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[7]; dout_r <= {dout_r[14:0],miso}; end
				6'd22: 	begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[6]; end
				6'd23: 	begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[6]; dout_r <= {dout_r[14:0],miso}; end
				6'd24: 	begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[5]; end
				6'd25: 	begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[5]; dout_r <= {dout_r[14:0],miso}; end
				6'd26: 	begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[4]; end
				6'd27: 	begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[4]; dout_r <= {dout_r[14:0],miso}; end
				6'd28: 	begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[3]; end
				6'd29: 	begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[3]; dout_r <= {dout_r[14:0],miso}; end
				6'd30: 	begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[2]; end
				6'd31: 	begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[2]; dout_r <= {dout_r[14:0],miso}; end
				6'd32: 	begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[1]; end
				6'd33: 	begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[1]; dout_r <= {dout_r[14:0],miso}; end
				6'd34: 	begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[0]; end
				6'd35: 	begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[0]; dout_r <= {dout_r[14:0],miso}; end
				6'd36: 	begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= 1'b0; end
				6'd37: 	begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= 1'b0; end
				6'd38: 	begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= 1'b0; end
				6'd39: 	begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= 1'b0; end
				6'd40: 	begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end
				6'd41: 	begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end
				6'd42: 	begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end
				6'd43: 	begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end
				6'd44: 	begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end
				6'd45: 	begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end
				6'd46: 	begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end
				6'd47: 	begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end
				default:	begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end
			endcase
		
	end
	end


//================ done =================//
	always @ (posedge sys_clk or negedge rst_n) begin
		if(!rst_n)
			done <= 1'b0;
		else if(cnt == cnt_total) 
		begin
			done <= 1'b1;
			
		end
		else
			done <= 1'b0;
	end


	
//================ dout =================//
	always@(posedge sys_clk or negedge rst_n) begin
		if(!rst_n)
			dout <= 'd0;
		else if(cnt == 'd38)
			dout <= dout_r;
		else
			dout <= dout;
	end	
	
	

endmodule