|ddr_ctrl sys_clk => sys_clk.IN2 rst_n => rst_n.IN3 test_flag => Selector12.IN4 test_flag => test_flag_led.DATAIN test_flag => convert_flag_led.DATAIN test_flag => Selector8.IN2 test_flag => Selector9.IN2 test_flag => Selector10.IN2 test_flag => Selector11.IN2 test_flag => Selector7.IN2 miso => miso.IN1 mosi <= spi_master_2164:u_spi_master_2164.mosi cs_n <= spi_master_2164:u_spi_master_2164.cs_n sclk <= spi_master_2164:u_spi_master_2164.sclk MOSI_ESP32 <= spi_master_esp32:tranfer.mosi cs_ESP32 <= spi_master_esp32:tranfer.cs sclk_ESP32 <= spi_master_esp32:tranfer.sclk tx <= uart_tx:u_uart_pc.tx test_flag_led <= test_flag.DB_MAX_OUTPUT_PORT_TYPE convert_flag_led <= test_flag.DB_MAX_OUTPUT_PORT_TYPE |ddr_ctrl|clk_gen:clk_gen_inst inclk0 => sub_wire1[0].IN1 c0 <= altpll:altpll_component.clk c1 <= altpll:altpll_component.clk |ddr_ctrl|clk_gen:clk_gen_inst|altpll:altpll_component inclk[0] => clk_gen_altpll:auto_generated.inclk[0] inclk[1] => clk_gen_altpll:auto_generated.inclk[1] fbin => ~NO_FANOUT~ pllena => ~NO_FANOUT~ clkswitch => ~NO_FANOUT~ areset => ~NO_FANOUT~ pfdena => ~NO_FANOUT~ clkena[0] => ~NO_FANOUT~ clkena[1] => ~NO_FANOUT~ clkena[2] => ~NO_FANOUT~ clkena[3] => ~NO_FANOUT~ clkena[4] => ~NO_FANOUT~ clkena[5] => ~NO_FANOUT~ extclkena[0] => ~NO_FANOUT~ extclkena[1] => ~NO_FANOUT~ extclkena[2] => ~NO_FANOUT~ extclkena[3] => ~NO_FANOUT~ scanclk => ~NO_FANOUT~ scanclkena => ~NO_FANOUT~ scanaclr => ~NO_FANOUT~ scanread => ~NO_FANOUT~ scanwrite => ~NO_FANOUT~ scandata => ~NO_FANOUT~ phasecounterselect[0] => ~NO_FANOUT~ phasecounterselect[1] => ~NO_FANOUT~ phasecounterselect[2] => ~NO_FANOUT~ phasecounterselect[3] => ~NO_FANOUT~ phaseupdown => ~NO_FANOUT~ phasestep => ~NO_FANOUT~ configupdate => ~NO_FANOUT~ fbmimicbidir <> clk[0] <= clk[0].DB_MAX_OUTPUT_PORT_TYPE clk[1] <= clk[1].DB_MAX_OUTPUT_PORT_TYPE clk[2] <= clk[2].DB_MAX_OUTPUT_PORT_TYPE clk[3] <= clk[3].DB_MAX_OUTPUT_PORT_TYPE clk[4] <= clk[4].DB_MAX_OUTPUT_PORT_TYPE extclk[0] <= extclk[1] <= extclk[2] <= extclk[3] <= clkbad[0] <= clkbad[1] <= enable1 <= enable0 <= activeclock <= clkloss <= locked <= scandataout <= scandone <= sclkout0 <= sclkout1 <= phasedone <= vcooverrange <= vcounderrange <= fbout <= fref <= icdrclk <= |ddr_ctrl|clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated clk[0] <= pll1.CLK clk[1] <= pll1.CLK1 clk[2] <= pll1.CLK2 clk[3] <= pll1.CLK3 clk[4] <= pll1.CLK4 inclk[0] => pll1.CLK inclk[1] => pll1.CLK1 |ddr_ctrl|spi_master_2164:u_spi_master_2164 sys_clk => dout[0]~reg0.CLK sys_clk => dout[1]~reg0.CLK sys_clk => dout[2]~reg0.CLK sys_clk => dout[3]~reg0.CLK sys_clk => dout[4]~reg0.CLK sys_clk => dout[5]~reg0.CLK sys_clk => dout[6]~reg0.CLK sys_clk => dout[7]~reg0.CLK sys_clk => dout[8]~reg0.CLK sys_clk => dout[9]~reg0.CLK sys_clk => dout[10]~reg0.CLK sys_clk => dout[11]~reg0.CLK sys_clk => dout[12]~reg0.CLK sys_clk => dout[13]~reg0.CLK sys_clk => dout[14]~reg0.CLK sys_clk => dout[15]~reg0.CLK sys_clk => done~reg0.CLK sys_clk => dout_r[0].CLK sys_clk => dout_r[1].CLK sys_clk => dout_r[2].CLK sys_clk => dout_r[3].CLK sys_clk => dout_r[4].CLK sys_clk => dout_r[5].CLK sys_clk => dout_r[6].CLK sys_clk => dout_r[7].CLK sys_clk => dout_r[8].CLK sys_clk => dout_r[9].CLK sys_clk => dout_r[10].CLK sys_clk => dout_r[11].CLK sys_clk => dout_r[12].CLK sys_clk => dout_r[13].CLK sys_clk => dout_r[14].CLK sys_clk => dout_r[15].CLK sys_clk => mosi~reg0.CLK sys_clk => cs_n~reg0.CLK sys_clk => sclk~reg0.CLK sys_clk => cnt[0]~reg0.CLK sys_clk => cnt[1]~reg0.CLK sys_clk => cnt[2]~reg0.CLK sys_clk => cnt[3]~reg0.CLK sys_clk => cnt[4]~reg0.CLK sys_clk => cnt[5]~reg0.CLK sys_clk => cnt[6]~reg0.CLK rst_n => mosi~reg0.ACLR rst_n => cs_n~reg0.PRESET rst_n => sclk~reg0.ACLR rst_n => dout[0]~reg0.ACLR rst_n => dout[1]~reg0.ACLR rst_n => dout[2]~reg0.ACLR rst_n => dout[3]~reg0.ACLR rst_n => dout[4]~reg0.ACLR rst_n => dout[5]~reg0.ACLR rst_n => dout[6]~reg0.ACLR rst_n => dout[7]~reg0.ACLR rst_n => dout[8]~reg0.ACLR rst_n => dout[9]~reg0.ACLR rst_n => dout[10]~reg0.ACLR rst_n => dout[11]~reg0.ACLR rst_n => dout[12]~reg0.ACLR rst_n => dout[13]~reg0.ACLR rst_n => dout[14]~reg0.ACLR rst_n => dout[15]~reg0.ACLR rst_n => done~reg0.ACLR rst_n => cnt[0]~reg0.ACLR rst_n => cnt[1]~reg0.ACLR rst_n => cnt[2]~reg0.ACLR rst_n => cnt[3]~reg0.ACLR rst_n => cnt[4]~reg0.ACLR rst_n => cnt[5]~reg0.ACLR rst_n => cnt[6]~reg0.ACLR rst_n => dout_r[15].ENA rst_n => dout_r[14].ENA rst_n => dout_r[13].ENA rst_n => dout_r[12].ENA rst_n => dout_r[11].ENA rst_n => dout_r[10].ENA rst_n => dout_r[9].ENA rst_n => dout_r[8].ENA rst_n => dout_r[7].ENA rst_n => dout_r[6].ENA rst_n => dout_r[5].ENA rst_n => dout_r[4].ENA rst_n => dout_r[3].ENA rst_n => dout_r[2].ENA rst_n => dout_r[1].ENA rst_n => dout_r[0].ENA din[0] => Selector0.IN33 din[1] => Selector0.IN32 din[2] => Selector0.IN31 din[3] => Selector0.IN30 din[4] => Selector0.IN29 din[5] => Selector0.IN28 din[6] => Selector0.IN27 din[7] => Selector0.IN26 din[8] => Selector0.IN25 din[9] => Selector0.IN24 din[10] => Selector0.IN23 din[11] => Selector0.IN22 din[12] => Selector0.IN21 din[13] => Selector0.IN20 din[14] => Selector0.IN19 din[15] => Selector0.IN18 start => cnt.OUTPUTSELECT start => cnt.OUTPUTSELECT start => cnt.OUTPUTSELECT start => cnt.OUTPUTSELECT start => cnt.OUTPUTSELECT start => cnt.OUTPUTSELECT start => cnt.OUTPUTSELECT dout[0] <= dout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE dout[1] <= dout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE dout[2] <= dout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE dout[3] <= dout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE dout[4] <= dout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE dout[5] <= dout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE dout[6] <= dout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE dout[7] <= dout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE dout[8] <= dout[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE dout[9] <= dout[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE dout[10] <= dout[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE dout[11] <= dout[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE dout[12] <= dout[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE dout[13] <= dout[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE dout[14] <= dout[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE dout[15] <= dout[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE done <= done~reg0.DB_MAX_OUTPUT_PORT_TYPE sclk <= sclk~reg0.DB_MAX_OUTPUT_PORT_TYPE cs_n <= cs_n~reg0.DB_MAX_OUTPUT_PORT_TYPE mosi <= mosi~reg0.DB_MAX_OUTPUT_PORT_TYPE miso => dout_r.DATAB cnt[0] <= cnt[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE cnt[1] <= cnt[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE cnt[2] <= cnt[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE cnt[3] <= cnt[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE cnt[4] <= cnt[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE cnt[5] <= cnt[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE cnt[6] <= cnt[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE |ddr_ctrl|spi_master_esp32:tranfer clk => done~reg0.CLK clk => shift_reg[0].CLK clk => shift_reg[1].CLK clk => shift_reg[2].CLK clk => shift_reg[3].CLK clk => shift_reg[4].CLK clk => shift_reg[5].CLK clk => shift_reg[6].CLK clk => shift_reg[7].CLK clk => shift_reg[8].CLK clk => shift_reg[9].CLK clk => shift_reg[10].CLK clk => shift_reg[11].CLK clk => shift_reg[12].CLK clk => shift_reg[13].CLK clk => shift_reg[14].CLK clk => shift_reg[15].CLK clk => bit_cnt[0].CLK clk => bit_cnt[1].CLK clk => bit_cnt[2].CLK clk => bit_cnt[3].CLK clk => sclk_reg.CLK clk => cs~reg0.CLK clk => state~4.DATAIN rst_n => done~reg0.ACLR rst_n => shift_reg[0].ACLR rst_n => shift_reg[1].ACLR rst_n => shift_reg[2].ACLR rst_n => shift_reg[3].ACLR rst_n => shift_reg[4].ACLR rst_n => shift_reg[5].ACLR rst_n => shift_reg[6].ACLR rst_n => shift_reg[7].ACLR rst_n => shift_reg[8].ACLR rst_n => shift_reg[9].ACLR rst_n => shift_reg[10].ACLR rst_n => shift_reg[11].ACLR rst_n => shift_reg[12].ACLR rst_n => shift_reg[13].ACLR rst_n => shift_reg[14].ACLR rst_n => shift_reg[15].ACLR rst_n => bit_cnt[0].ACLR rst_n => bit_cnt[1].ACLR rst_n => bit_cnt[2].ACLR rst_n => bit_cnt[3].ACLR rst_n => sclk_reg.ACLR rst_n => cs~reg0.PRESET rst_n => state~6.DATAIN start => state.OUTPUTSELECT start => state.OUTPUTSELECT start => state.OUTPUTSELECT start => done~reg0.ENA start => cs~reg0.ENA start => sclk_reg.ENA start => bit_cnt[3].ENA start => bit_cnt[2].ENA start => bit_cnt[1].ENA start => bit_cnt[0].ENA start => shift_reg[15].ENA start => shift_reg[14].ENA start => shift_reg[13].ENA start => shift_reg[12].ENA start => shift_reg[11].ENA start => shift_reg[10].ENA start => shift_reg[9].ENA start => shift_reg[8].ENA start => shift_reg[7].ENA start => shift_reg[6].ENA start => shift_reg[5].ENA start => shift_reg[4].ENA start => shift_reg[3].ENA start => shift_reg[2].ENA start => shift_reg[1].ENA start => shift_reg[0].ENA din[0] => Selector18.IN1 din[1] => Selector17.IN1 din[2] => Selector16.IN1 din[3] => Selector15.IN1 din[4] => Selector14.IN1 din[5] => Selector13.IN1 din[6] => Selector12.IN1 din[7] => Selector11.IN1 din[8] => Selector10.IN1 din[9] => Selector9.IN1 din[10] => Selector8.IN1 din[11] => Selector7.IN1 din[12] => Selector6.IN1 din[13] => Selector5.IN1 din[14] => Selector4.IN1 din[15] => Selector3.IN1 done <= done~reg0.DB_MAX_OUTPUT_PORT_TYPE sclk <= sclk_reg.DB_MAX_OUTPUT_PORT_TYPE mosi <= shift_reg[15].DB_MAX_OUTPUT_PORT_TYPE cs <= cs~reg0.DB_MAX_OUTPUT_PORT_TYPE |ddr_ctrl|uart_tx:u_uart_pc clk => tx_bit_counter[0].CLK clk => tx_bit_counter[1].CLK clk => tx_bit_counter[2].CLK clk => tx_bit_counter[3].CLK clk => data_to_send[0].CLK clk => data_to_send[1].CLK clk => data_to_send[2].CLK clk => data_to_send[3].CLK clk => data_to_send[4].CLK clk => data_to_send[5].CLK clk => data_to_send[6].CLK clk => data_to_send[7].CLK clk => tx_shift_reg[0].CLK clk => tx_shift_reg[1].CLK clk => tx_shift_reg[2].CLK clk => tx_shift_reg[3].CLK clk => tx_shift_reg[4].CLK clk => tx_shift_reg[5].CLK clk => tx_shift_reg[6].CLK clk => tx_shift_reg[7].CLK clk => tx_shift_reg[8].CLK clk => tx_shift_reg[9].CLK clk => tx_done~reg0.CLK clk => baud_counter[0].CLK clk => baud_counter[1].CLK clk => baud_counter[2].CLK clk => baud_counter[3].CLK clk => baud_counter[4].CLK clk => baud_counter[5].CLK clk => baud_counter[6].CLK clk => baud_counter[7].CLK clk => baud_counter[8].CLK clk => baud_counter[9].CLK clk => baud_counter[10].CLK clk => baud_counter[11].CLK clk => baud_counter[12].CLK clk => baud_counter[13].CLK clk => baud_counter[14].CLK clk => baud_counter[15].CLK clk => byte_select~2.DATAIN clk => tx_state~3.DATAIN rst => tx_shift_reg[0].PRESET rst => tx_shift_reg[1].PRESET rst => tx_shift_reg[2].PRESET rst => tx_shift_reg[3].PRESET rst => tx_shift_reg[4].PRESET rst => tx_shift_reg[5].PRESET rst => tx_shift_reg[6].PRESET rst => tx_shift_reg[7].PRESET rst => tx_shift_reg[8].PRESET rst => tx_shift_reg[9].PRESET rst => tx_done~reg0.ACLR rst => baud_counter[0].ACLR rst => baud_counter[1].ACLR rst => baud_counter[2].ACLR rst => baud_counter[3].ACLR rst => baud_counter[4].ACLR rst => baud_counter[5].ACLR rst => baud_counter[6].ACLR rst => baud_counter[7].ACLR rst => baud_counter[8].ACLR rst => baud_counter[9].ACLR rst => baud_counter[10].ACLR rst => baud_counter[11].ACLR rst => baud_counter[12].ACLR rst => baud_counter[13].ACLR rst => baud_counter[14].ACLR rst => baud_counter[15].ACLR rst => byte_select~4.DATAIN rst => tx_state~5.DATAIN rst => tx_bit_counter[0].ENA rst => data_to_send[7].ENA rst => data_to_send[6].ENA rst => data_to_send[5].ENA rst => data_to_send[4].ENA rst => data_to_send[3].ENA rst => data_to_send[2].ENA rst => data_to_send[1].ENA rst => data_to_send[0].ENA rst => tx_bit_counter[3].ENA rst => tx_bit_counter[2].ENA rst => tx_bit_counter[1].ENA tx_start => data_to_send.OUTPUTSELECT tx_start => data_to_send.OUTPUTSELECT tx_start => data_to_send.OUTPUTSELECT tx_start => data_to_send.OUTPUTSELECT tx_start => data_to_send.OUTPUTSELECT tx_start => data_to_send.OUTPUTSELECT tx_start => data_to_send.OUTPUTSELECT tx_start => data_to_send.OUTPUTSELECT tx_start => tx_shift_reg.OUTPUTSELECT tx_start => tx_shift_reg.OUTPUTSELECT tx_start => tx_shift_reg.OUTPUTSELECT tx_start => tx_shift_reg.OUTPUTSELECT tx_start => tx_shift_reg.OUTPUTSELECT tx_start => tx_shift_reg.OUTPUTSELECT tx_start => tx_shift_reg.OUTPUTSELECT tx_start => tx_shift_reg.OUTPUTSELECT tx_start => tx_shift_reg.OUTPUTSELECT tx_start => tx_shift_reg.OUTPUTSELECT tx_start => tx_state.OUTPUTSELECT tx_start => tx_state.OUTPUTSELECT tx_start => tx_done.OUTPUTSELECT tx_data[0] => data_to_send.DATAA tx_data[1] => data_to_send.DATAA tx_data[2] => data_to_send.DATAA tx_data[3] => data_to_send.DATAA tx_data[4] => data_to_send.DATAA tx_data[5] => data_to_send.DATAA tx_data[6] => data_to_send.DATAA tx_data[7] => data_to_send.DATAA tx_data[8] => data_to_send.DATAB tx_data[9] => data_to_send.DATAB tx_data[10] => data_to_send.DATAB tx_data[11] => data_to_send.DATAB tx_data[12] => data_to_send.DATAB tx_data[13] => data_to_send.DATAB tx_data[14] => data_to_send.DATAB tx_data[15] => data_to_send.DATAB tx <= tx_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE tx_done <= tx_done~reg0.DB_MAX_OUTPUT_PORT_TYPE