248 lines
6.8 KiB
Verilog
248 lines
6.8 KiB
Verilog
module ddr_ctrl(
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input sys_clk, // 12M on-board oscillator
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input rst_n,
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input test_flag, // 1: read register, 0: start convert data
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// 2132
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input miso,
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output mosi,
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output cs_n,
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output sclk,
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//esp32
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output MOSI_ESP32,
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output cs_ESP32,
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output sclk_ESP32,
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//uart
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output wire tx, // 串行输出信号
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output test_flag_led,
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output convert_flag_led
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// for simulation
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// output reg [25:0] state,
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// output reg [25:0] next,
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//output [15:0] dout
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);
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reg start1, start2,start_uart;
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wire done1,done2,done_uart;
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localparam [4:0] s0 = 0,
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s1 = 1,
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s2 = 2,
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s3 = 3,
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s4 = 4,
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s5 = 5,
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s6 = 6,
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s7 = 7,
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s8 = 8,
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s9 = 9,
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s10 = 10,
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s11 = 11,
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s12 = 12,
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s13 = 13,
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s14 = 14,
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s15 = 15,
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s16 = 16,
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s17 = 17,
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s18 = 18,
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s19 = 19,
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s20 = 20,
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s21 = 21,
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s22 = 22,
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s23 = 23,
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s24 = 24,
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s25 = 25,
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s26 = 26,
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s27 = 27,
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s28 = 28,
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s29 = 29,
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s30 = 30;
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reg [30:0] state, next;
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reg [15:0] din_r;
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wire [15:0] din;
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reg [15:0] received_data; // 存储从从机1接收到的数据
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reg [15:0] sent_data; // 要发送到从机2的数据
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assign din = din_r;
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assign test_flag_led = test_flag;
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assign convert_flag_led = ~test_flag;
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// 定义状态编码
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parameter IDLE = 2'b00,
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SEND1 = 2'b01,
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SEND2 = 2'b10,
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SEND_uart =2'b11;
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// 定义状态变量
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reg [1:0] state_top;
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//状态机，用于控制两个SPI模块的启动
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always @(posedge clk_115200 or negedge rst_n) begin
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if (!rst_n) begin
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start1 <= 0;
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start2 <= 0;
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state_top <= IDLE;
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end
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else begin
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case (state_top)
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IDLE: begin
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start1 <= 1; // 启动SPI主机1
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start2 <= 0;
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state_top <= SEND1;
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end
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SEND1: begin
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if (done1) begin // SPI主机1完成接收
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start1 <= 0;
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received_data <= dout1; // 存储接收到的数据
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sent_data <= dout1; // 将接收到的数据准备好发送
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start_uart <= 1; // 启动SPI主机2，发送数据给从机2
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state_top <= SEND_uart;
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end
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end
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SEND_uart: begin
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if (done_uart) begin // uart完成发送
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start_uart <= 0;
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//start2 <= 1;
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state_top <= IDLE;
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end
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end
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SEND2: begin
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if (done2) begin // SPI主机2完成发送
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start2 <= 0;
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state_top <= IDLE; // 回到初始状态，等待下一轮传输
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end
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end
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default: state_top <= IDLE;
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endcase
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end
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end
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//时序逻辑加组合逻辑完成din命令的有序发送
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always @ (posedge cs_n or negedge rst_n) begin
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if(!rst_n) begin
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state <= 31'd0;
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state[s0] <= 1'b1;
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end
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else state <= next;
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end
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always @ (*) begin
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next = 31'd0;
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din_r = {2'b11,6'd63,8'h00};
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case(1'b1) // synthesis parallel_case full_case
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state[s0]: begin din_r<={2'b11,6'd63,8'h00}; next[s1] = 1'b1; end
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state[s1]: begin din_r<={2'b11,6'd63,8'h00}; next[s2] = 1'b1; end
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state[s2]: begin din_r<={2'b10,6'd0,8'hDE}; next[s3] = 1'b1; end
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state[s3]: begin din_r<={2'b10,6'd1,8'h20}; next[s4] = 1'b1; end //8'h20
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state[s4]: begin din_r<={2'b10,6'd2,8'h28}; next[s5] = 1'b1; end //8'h28
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state[s5]: begin din_r<={2'b10,6'd3,8'h00}; next[s6] = 1'b1; end
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state[s6]: begin din_r<={2'b10,6'd4,8'hD6}; next[s7] = 1'b1; end
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state[s7]: begin din_r<={2'b10,6'd5,8'h00}; next[s8] = 1'b1; end
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state[s8]: begin din_r<={2'b10,6'd6,8'h80}; next[s9] = 1'b1; end
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state[s9]: begin din_r<={2'b10,6'd7,8'h00}; next[s10] = 1'b1; end
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state[s10]: begin din_r<={2'b10,6'd8,8'h16}; next[s11] = 1'b1; end
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state[s11]: begin din_r<={2'b10,6'd9,8'h80}; next[s12] = 1'b1; end
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state[s12]: begin din_r<={2'b10,6'd10,8'h17}; next[s13] = 1'b1; end
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state[s13]: begin din_r<={2'b10,6'd11,8'h80}; next[s14] = 1'b1; end
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state[s14]: begin din_r<={2'b10,6'd12,8'h2C}; next[s15] = 1'b1; end
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state[s15]: begin din_r<={2'b10,6'd13,8'h86}; next[s16] = 1'b1; end
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state[s16]: begin din_r<={2'b10,6'd14,8'hFF}; next[s17] = 1'b1; end
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state[s17]: begin din_r<={2'b10,6'd15,8'hFF}; next[s18] = 1'b1; end
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state[s18]: begin din_r<={2'b10,6'd16,8'hFF}; next[s19] = 1'b1; end
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state[s19]: begin din_r<={2'b10,6'd17,8'hFF}; next[s20] = 1'b1; end
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state[s20]: begin din_r<={2'b01,6'd21,8'h00}; next[s21] = 1'b1; end // CALIBRATE, {01,010101,8h00}
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state[s21]: begin din_r<={2'b11,6'd63,8'h00}; next[s22] = 1'b1; end // dummy 1
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state[s22]: begin din_r<={2'b11,6'd63,8'h00}; next[s23] = 1'b1; end // dummy 2
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state[s23]: begin din_r<={2'b11,6'd63,8'h00}; next[s24] = 1'b1; end // dummy 3
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state[s24]: begin din_r<={2'b11,6'd63,8'h00}; next[s25] = 1'b1; end // dummy 4
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state[s25]: begin din_r<={2'b11,6'd63,8'h00}; next[s26] = 1'b1; end // dummy 5
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state[s26]: begin din_r<={2'b11,6'd63,8'h00}; next[s27] = 1'b1; end // dummy 6
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state[s27]: begin din_r<={2'b11,6'd63,8'h00}; next[s28] = 1'b1; end // dummy 7
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state[s28]: begin din_r<={2'b11,6'd63,8'h00}; next[s29] = 1'b1; end // dummy 8
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state[s29]: begin din_r<={2'b11,6'd62,8'h00}; next[s30] = 1'b1; end // dummy 9
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state[s30]: begin
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if (test_flag) begin din_r<={2'b00,6'd21,8'h00}; end // convert(3)
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else begin din_r<={2'b11,6'd62,8'h00}; end // read(63)
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next[s30] = 1'b1;
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end
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endcase
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end
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wire clk_115200;
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wire clk_230400;
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clk_gen clk_gen_inst (
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.inclk0 ( sys_clk ),
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.c0 ( clk_115200 ),
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.c1 ( clk_230400 )
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);
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wire [15:0] dout1;
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spi_master_2164 u_spi_master_2164(
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.sys_clk(clk_115200 ),
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.rst_n(rst_n),
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.din(din),
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.start(start1),
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.dout(dout1),
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.done(done1),
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.sclk(sclk),
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.cs_n(cs_n),
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.mosi(mosi),
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.miso(miso),
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.cnt()
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);
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spi_master_esp32 tranfer(
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.clk(sys_clk),
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.rst_n(rst_n),
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.start(start2),
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.din(sent_data),
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.done(done2),
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.sclk(sclk_ESP32),
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.mosi(MOSI_ESP32),
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.cs(cs_ESP32)
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);
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uart_tx u_uart_pc(
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.clk(clk_115200), // 时钟信号
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.rst(rst_n), // 复位信号
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.tx_start(start_uart), // 开始发送信号
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.tx_data(sent_data), // 顶层输入的16位待发送数据
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.tx(tx), // 串行输出信号
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.tx_done(done_uart) // 发送完成信号
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);
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endmodule
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