68 lines
1.6 KiB
Verilog
68 lines
1.6 KiB
Verilog
module spi_master_esp32(
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input wire clk,
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input wire rst_n,
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input wire start,
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input wire [15:0] din,
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output reg done,
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output wire sclk,
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output wire mosi,
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output reg cs
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);
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reg [3:0] bit_cnt;
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reg [15:0] shift_reg;
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reg sclk_reg;
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reg [1:0] state;
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localparam IDLE = 2'b00, TRANSFER = 2'b01, DONE = 2'b10;
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assign sclk = sclk_reg;
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assign mosi = shift_reg[15];
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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state <= IDLE;
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cs <= 1;
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sclk_reg <= 0;
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bit_cnt <= 0;
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shift_reg <= 0;
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done <= 0;
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end
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else begin
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if (start) begin
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case (state)
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IDLE: begin
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state <= TRANSFER;
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cs <= 0; // 选择从机
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shift_reg <= din;
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bit_cnt <= 0;
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done <= 0;
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end
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TRANSFER: begin
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sclk_reg <= ~sclk_reg; //这样也是一个系统时钟周期新的sclk反转一次，所以sclk的频率也是115200.
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if (sclk_reg) begin //看上面的assign mosi = shift_reg[15]; 所以每个sclk高电平mosi输出要输出的值。
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shift_reg <= {shift_reg[14:0], 1'b0};
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bit_cnt <= bit_cnt + 1;
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if (bit_cnt == 15) begin
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state <= DONE;
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end
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end
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end
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DONE: begin
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state <= IDLE;
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cs <= 1; // 取消选择从机
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done <= 1;
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end
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endcase
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end
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end
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end
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endmodule |