55 lines
26 KiB
Plaintext
55 lines
26 KiB
Plaintext
{ "Info" "IQCU_PARALLEL_SHOW_MANUAL_NUM_PROCS" "4 " "Parallel compilation is enabled and will use up to 4 processors" { } { } 0 20032 "Parallel compilation is enabled and will use up to %1!i! processors" 0 0 "Fitter" 0 -1 1765447227432 ""}
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{ "Info" "IMPP_MPP_USER_DEVICE" "intan_m10 10M08SAM153C8G " "Selected device 10M08SAM153C8G for design \"intan_m10\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1765447227440 ""}
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{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1765447227474 ""}
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{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1765447227474 ""}
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{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|pll1 MAX 10 PLL " "Implemented PLL \"clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|pll1\" as MAX 10 PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] 6 625 0 0 " "Implementing clock multiplication of 6, clock division of 625, and phase shift of 0 degrees (0 ps) for clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/clk_gen_altpll.v" "" { Text "E:/FPGA/puart2/db/clk_gen_altpll.v" 43 -1 0 } } { "" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 124 14177 15141 0 0 "" 0 "" "" } } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Design Software" 0 -1 1765447227517 ""} } { { "db/clk_gen_altpll.v" "" { Text "E:/FPGA/puart2/db/clk_gen_altpll.v" 43 -1 0 } } { "" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 124 14177 15141 0 0 "" 0 "" "" } } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1765447227517 ""}
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{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1765447227564 ""}
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{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1765447227572 ""}
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{ "Critical Warning" "WFCUDA_FCUDA_SPS_DEVICE_POWER_LIMITATION" "" "Review the Power Analyzer report file (<design>.pow.rpt) to ensure your design is within the maximum power utilization limit of the single power-supply target device and to avoid functional failures." { } { } 1 16562 "Review the Power Analyzer report file (<design>.pow.rpt) to ensure your design is within the maximum power utilization limit of the single power-supply target device and to avoid functional failures." 0 0 "Fitter" 0 -1 1765447227690 ""}
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{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M08SAM153C8GES " "Device 10M08SAM153C8GES is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1765447227701 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M04SAM153C8G " "Device 10M04SAM153C8G is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1765447227701 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1765447227701 ""}
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{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "8 " "Fitter converted 8 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TMS~ G1 " "Pin ~ALTERA_TMS~ is reserved at location G1" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { ~ALTERA_TMS~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 395 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765447227702 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TCK~ J1 " "Pin ~ALTERA_TCK~ is reserved at location J1" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { ~ALTERA_TCK~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 397 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765447227702 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDI~ H5 " "Pin ~ALTERA_TDI~ is reserved at location H5" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDI~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 399 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765447227702 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_TDO~ H4 " "Pin ~ALTERA_TDO~ is reserved at location H4" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { ~ALTERA_TDO~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 401 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765447227702 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONFIG_SEL~ D8 " "Pin ~ALTERA_CONFIG_SEL~ is reserved at location D8" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONFIG_SEL~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 403 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765447227702 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCONFIG~ E8 " "Pin ~ALTERA_nCONFIG~ is reserved at location E8" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCONFIG~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 405 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765447227702 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nSTATUS~ D6 " "Pin ~ALTERA_nSTATUS~ is reserved at location D6" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { ~ALTERA_nSTATUS~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 407 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765447227702 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONF_DONE~ E6 " "Pin ~ALTERA_CONF_DONE~ is reserved at location E6" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONF_DONE~ } } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 409 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1765447227702 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1765447227702 ""}
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{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" { } { } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1765447227703 ""}
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{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1765447227703 ""}
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{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1765447227703 ""}
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{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" { } { } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1765447227703 ""}
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{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1765447227703 ""}
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{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "intan_m10.sdc " "Synopsys Design Constraints File file not found: 'intan_m10.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1765447228110 ""}
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{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "generated clocks " "No user constrained generated clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1765447228110 ""}
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{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1765447228111 ""}
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{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1765447228114 ""}
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{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1765447228114 ""}
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{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1765447228114 ""}
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{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C1 of PLL_1) " "Automatically promoted node clk_gen:clk_gen_inst\|altpll:altpll_component\|clk_gen_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C1 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1765447228130 ""} } { { "db/clk_gen_altpll.v" "" { Text "E:/FPGA/puart2/db/clk_gen_altpll.v" 77 -1 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 124 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1765447228130 ""}
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{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "spi_master_2164:u_spi_master_2164\|cs_n " "Automatically promoted node spi_master_2164:u_spi_master_2164\|cs_n " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1765447228130 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "cs_n~output " "Destination node cs_n~output" { } { { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 9 0 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 376 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1765447228130 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1765447228130 ""} } { { "spi_master_2164.v" "" { Text "E:/FPGA/puart2/spi_master_2164.v" 11 -1 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 119 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1765447228130 ""}
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{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1765447228429 ""}
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{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1765447228430 ""}
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{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1765447228430 ""}
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{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1765447228431 ""}
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{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1765447228431 ""}
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{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1765447228432 ""}
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{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1765447228432 ""}
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{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1765447228432 ""}
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{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1765447228442 ""}
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{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1765447228443 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1765447228443 ""}
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{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1765447228463 ""}
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{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1765447228466 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1765447228928 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1765447228977 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1765447228986 ""}
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{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1765447229349 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1765447229349 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1765447229707 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X10_Y0 X20_Y12 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X10_Y0 to location X20_Y12" { } { { "loc" "" { Generic "E:/FPGA/puart2/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X10_Y0 to location X20_Y12"} { { 12 { 0 ""} 10 0 11 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1765447230052 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1765447230052 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1765447230330 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1765447230330 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1765447230333 ""}
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{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.15 " "Total time spent on timing analysis during the Fitter is 0.15 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1765447230488 ""}
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{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1765447230493 ""}
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{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1765447230679 ""}
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{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1765447230680 ""}
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{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1765447230967 ""}
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{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1765447231409 ""}
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{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "4 MAX 10 " "4 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing MAX 10 Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "test_flag 3.3-V LVCMOS J12 " "Pin test_flag uses I/O standard 3.3-V LVCMOS at J12" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { test_flag } } } { "e:/quartuslite/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/quartuslite/quartus/bin64/Assignment Editor.qase" 1 { { 0 "test_flag" } } } } { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 4 0 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 11 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1765447231526 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "rst_n 3.3-V LVCMOS J14 " "Pin rst_n uses I/O standard 3.3-V LVCMOS at J14" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { rst_n } } } { "e:/quartuslite/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/quartuslite/quartus/bin64/Assignment Editor.qase" 1 { { 0 "rst_n" } } } } { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 3 0 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 10 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1765447231526 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "sys_clk 3.3-V LVCMOS J5 " "Pin sys_clk uses I/O standard 3.3-V LVCMOS at J5" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { sys_clk } } } { "e:/quartuslite/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/quartuslite/quartus/bin64/Assignment Editor.qase" 1 { { 0 "sys_clk" } } } } { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 2 0 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 9 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1765447231526 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "miso 3.3-V LVCMOS P4 " "Pin miso uses I/O standard 3.3-V LVCMOS at P4" { } { { "e:/quartuslite/quartus/bin64/pin_planner.ppl" "" { PinPlanner "e:/quartuslite/quartus/bin64/pin_planner.ppl" { miso } } } { "e:/quartuslite/quartus/bin64/Assignment Editor.qase" "" { Assignment "e:/quartuslite/quartus/bin64/Assignment Editor.qase" 1 { { 0 "miso" } } } } { "ddr_ctrl.v" "" { Text "E:/FPGA/puart2/ddr_ctrl.v" 7 0 0 } } { "temporary_test_loc" "" { Generic "E:/FPGA/puart2/" { { 0 { 0 ""} 0 12 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1765447231526 ""} } { } 0 169177 "%1!d! pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1765447231526 ""}
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{ "Warning" "WFIOMGR_INCONSISTENT_VCCIO_ACROSS_MULTIPLE_BANKS_OF_CONFIGURAION_PINS" "2 Internal Configuration 2 " "Inconsistent VCCIO across multiple banks of configuration pins. The configuration pins are contained in 2 banks in 'Internal Configuration' configuration scheme and there are 2 different VCCIOs." { } { } 0 169202 "Inconsistent VCCIO across multiple banks of configuration pins. The configuration pins are contained in %1!d! banks in '%2!s!' configuration scheme and there are %3!d! different VCCIOs." 0 0 "Fitter" 0 -1 1765447231527 ""}
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{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/FPGA/puart2/output_files/intan_m10.fit.smsg " "Generated suppressed messages file E:/FPGA/puart2/output_files/intan_m10.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1765447231568 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5547 " "Peak virtual memory: 5547 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1765447231939 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 11 18:00:31 2025 " "Processing ended: Thu Dec 11 18:00:31 2025" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1765447231939 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1765447231939 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1765447231939 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1765447231939 ""}
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