67 lines
614 B
Verilog
67 lines
614 B
Verilog
module ddr_ctrl_tb();
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reg sys_clk;
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reg rst_n;
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reg miso;
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wire mosi;
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wire cs_n;
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wire sclk;
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wire [24:0] state;
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wire [24:0] next;
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wire [31:0] dout;
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ddr_ctrl uut(
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.sys_clk(sys_clk),
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.rst_n(rst_n),
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.miso(miso),
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.mosi(mosi),
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.cs_n(cs_n),
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.sclk(sclk),
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.state(state),
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.next(next),
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.dout(dout)
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);
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initial
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begin
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rst_n = 0;
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miso = 0;
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#50 rst_n = 1;
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#12000 $finish;
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end
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initial begin
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forever begin
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#5 sys_clk = 0;
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#5 sys_clk = 1;
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end
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end
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initial begin
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forever begin
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#50 miso = 0;
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#50 miso = 1;
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end
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end
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initial begin
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$fsdbDumpfile("ddr_ctrl.fsdb");
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$fsdbDumpvars();
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end
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endmodule
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