130 lines
4.9 KiB
Verilog
130 lines
4.9 KiB
Verilog
module spi_master_2164(
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input sys_clk,
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input rst_n,
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input [15:0] din,
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input wire start,
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output reg [15:0] dout,
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output reg done,
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// connect to 2164
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output reg sclk,
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output reg cs_n,
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output reg mosi,
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input miso,
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// for test only
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output reg [6:0] cnt // count to 47
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);
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localparam cnt_total = 'd42;
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reg [15:0] dout_r;
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//================== cnt =====================//
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always @ (posedge sys_clk or negedge rst_n) begin
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if(!rst_n)
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cnt <= 'd0;
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else if(cnt == cnt_total)
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cnt <= 'd0;
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else
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if (start) begin
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cnt <= cnt + 1'b1;
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end
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end
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//================== send data ===============//
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always @ (posedge sys_clk or negedge rst_n) begin
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if(!rst_n) begin
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sclk <= 1'b0;
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cs_n <= 1'b1;
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mosi <= 1'b0;
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end
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else begin
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case(cnt)
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6'd0: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end
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6'd1: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end
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6'd2: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= 1'b0; end
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6'd3: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= 1'b0; end
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6'd4: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[15]; end
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6'd5: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[15]; dout_r <= {dout_r[14:0],miso}; end
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6'd6: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[14]; end
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6'd7: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[14]; dout_r <= {dout_r[14:0],miso}; end
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6'd8: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[13]; end
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6'd9: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[13]; dout_r <= {dout_r[14:0],miso}; end
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6'd10: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[12]; end
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6'd11: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[12]; dout_r <= {dout_r[14:0],miso}; end
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6'd12: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[11]; end
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6'd13: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[11]; dout_r <= {dout_r[14:0],miso}; end
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6'd14: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[10]; end
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6'd15: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[10]; dout_r <= {dout_r[14:0],miso}; end
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6'd16: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[9]; end
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6'd17: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[9]; dout_r <= {dout_r[14:0],miso}; end
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6'd18: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[8]; end
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6'd19: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[8]; dout_r <= {dout_r[14:0],miso}; end
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6'd20: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[7]; end
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6'd21: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[7]; dout_r <= {dout_r[14:0],miso}; end
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6'd22: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[6]; end
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6'd23: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[6]; dout_r <= {dout_r[14:0],miso}; end
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6'd24: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[5]; end
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6'd25: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[5]; dout_r <= {dout_r[14:0],miso}; end
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6'd26: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[4]; end
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6'd27: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[4]; dout_r <= {dout_r[14:0],miso}; end
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6'd28: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[3]; end
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6'd29: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[3]; dout_r <= {dout_r[14:0],miso}; end
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6'd30: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[2]; end
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6'd31: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[2]; dout_r <= {dout_r[14:0],miso}; end
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6'd32: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[1]; end
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6'd33: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[1]; dout_r <= {dout_r[14:0],miso}; end
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6'd34: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= din[0]; end
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6'd35: begin cs_n <= 1'b0; sclk <= 1'b1; mosi <= din[0]; dout_r <= {dout_r[14:0],miso}; end
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6'd36: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= 1'b0; end
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6'd37: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= 1'b0; end
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6'd38: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= 1'b0; end
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6'd39: begin cs_n <= 1'b0; sclk <= 1'b0; mosi <= 1'b0; end
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6'd40: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end
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6'd41: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end
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6'd42: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end
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6'd43: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end
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6'd44: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end
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6'd45: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end
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6'd46: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end
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6'd47: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end
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default: begin cs_n <= 1'b1; sclk <= 1'b0; mosi <= 1'b0; end
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endcase
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end
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end
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//================ done =================//
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always @ (posedge sys_clk or negedge rst_n) begin
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if(!rst_n)
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done <= 1'b0;
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else if(cnt == cnt_total)
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begin
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done <= 1'b1;
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end
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else
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done <= 1'b0;
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end
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//================ dout =================//
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always@(posedge sys_clk or negedge rst_n) begin
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if(!rst_n)
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dout <= 'd0;
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else if(cnt == 'd38)
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dout <= dout_r;
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else
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dout <= dout;
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end
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endmodule
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